Abstract: In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2ICL=2IL during the bypass capacitor 12 charging time, where ICL is the capacitive current and IL is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.

Abstract: A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element.

Abstract: A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element.

Abstract: In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2ICL=2IL during the bypass capacitor 12 charging time, where ICL is the capacitive current and IL is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.

Abstract: A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element.

Abstract: A device having a signal level different from a signal level of an external device includes an interface, such as an I2C interface, for providing communications with the external device. The interface is configurable to support communications with the external device either via multiple wires or via a single wire.

Abstract: A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly.

Abstract: A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly.

Abstract: An output signal is controlled with adjustable hysteresis in response to a variable voltage input signal. One or more signals derived from the input signal are respectively compared with first and second reference voltages of different magnitudes. The output signal changes from a first state to a second state when one of the derived signals reaches a first reference voltage level threshold, and changes from the second state to the first state when a second one of the derived signals reaches a second reference level voltage threshold. A first derived signal may be varied to have a voltage magnitude that is greater or lesser than the voltage magnitude of a second derived signal while maintaining a positive hysteresis level. The circuit may be configured to output a signal representing an undervoltage and/or overvoltage condition of the input signal.

Abstract: A device having a signal level different from a signal level of an external device includes an interface, such as an I2C interface, for providing communications with the external device. The interface is configurable to support communications with the external device either via multiple wires or via a single wire.

Abstract: A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly.

Abstract: Multilayered porous materials are formed by coating a porous substrate with a metal and adsorbing an organic layer comprising a recognition moiety onto the metal film. The recognition moiety interacts with an analyte of interest allowing for its detection, purification, etc. Suitable recognition moieties can be selected from a range of species including, small molecules, polymers and biomolecules and the like. The novel porous materials of the invention can be utilized in an array of methods including, ion-exchange, ion-selective ion-exchange, assays, affinity dialysis, size exclusion dialysis and the like.

Abstract: Multilayered particulate materials are formed by coating a particulate substrate with a metal and adsorbing an organic layer comprising a recognition moiety onto the metal film. The recognition moiety interacts with an analyte of interest allowing for its detection, purification, etc. Suitable recognition moieties can be selected from a range of species including, small molecules, polymers and biomolecules and the like. The novel particulate materials of the invention can be utilized in an array of methods including, ion-exchange, ion-selective ion-exchange, assays, affinity dialysis, size exclusion dialysis, as supports in solid phase synthesis, combinatorial synthesis and screening of compound libraries and the like.