Abstract: Electrical impulses are received from a beating heart. The electrical impulses are converted to an ECG waveform. The ECG waveform is converted to a frequency domain waveform, which, in turn, is separated into two or more different frequency domain waveforms, which, in turn, are converted into a plurality of time domain cardiac electrophysiological subwaveforms and discontinuity points between these subwaveforms. The plurality of subwaveforms and discontinuity points are compared to a database of subwaveforms and discontinuity points for normal and abnormal patients. An ST-T interval is identified from the plurality of subwaveforms and discontinuity points based on the comparison, the ST-T interval is divided into N number of equally spaced sections, and an average data value of detection is calculated for each section. A table is displayed that includes an average data value of detection for each section of the ST-T interval.

Abstract: An ECG system measures and annotates the I-point of in an ECG waveform from harmonic waveforms. Electrical impulses are received from a beating heart. The electrical impulses are converted to an ECG waveform. The ECG waveform is converted to a frequency domain waveform, which, in turn, is separated into two or more different frequency domain waveforms, which, in turn, are converted into a plurality of time domain cardiac electrophysiological subwaveforms and discontinuity points between these subwaveforms. The plurality of subwaveforms and discontinuity points are compared to a database of subwaveforms and discontinuity points for normal and abnormal patients. A discontinuity point is identified as the I-point of the ECG waveform from the comparison. The ECG waveform is displayed along with a marker at a location of the discontinuity point.

Abstract: An ECG system identifies and annotates cardiac electrophysiological signals in an ECG waveform from harmonic waveforms. Electrical impulses are received from a beating heart. The electrical impulses are converted to an ECG waveform. The ECG waveform is converted to a frequency domain waveform, which, in turn, is separated into two or more different frequency domain waveforms, which, in turn, are converted into a plurality of time domain cardiac electrophysiological subwaveforms and discontinuity points between these subwaveforms. The plurality of subwaveforms and discontinuity points are compared to a database of subwaveforms and discontinuity points for normal and abnormal patients. At least one subwaveform or one or more discontinuity points are identified as a normal or abnormal electrophysiological signal of the ECG waveform from the comparison. The ECG waveform is displayed along with one or more markers at a location of the at least one subwaveform or one or more discontinuity points.

Abstract: An ECG system measures and annotates the I-point of in an ECG waveform from harmonic waveforms. Electrical impulses are received from a beating heart. The electrical impulses are converted to an ECG waveform. The ECG waveform is converted to a frequency domain waveform, which, in turn, is separated into two or more different frequency domain waveforms, which, in turn, are converted into a plurality of time domain cardiac electrophysiological subwaveforms and discontinuity points between these subwaveforms. The plurality of subwaveforms and discontinuity points are compared to a database of subwaveforms and discontinuity points for normal and abnormal patients. A discontinuity point is identified as the I-point of the ECG waveform from the comparison. The ECG waveform is displayed along with a marker at a location of the discontinuity point.

Abstract: An ECG system identifies and annotates cardiac electrophysiological signals in an ECG waveform from harmonic waveforms. Electrical impulses are received from a beating heart. The electrical impulses are converted to an ECG waveform. The ECG waveform is converted to a frequency domain waveform, which, in turn, is separated into two or more different frequency domain waveforms, which, in turn, are converted into a plurality of time domain cardiac electrophysiological subwaveforms and discontinuity points between these subwaveforms. The plurality of subwaveforms and discontinuity points are compared to a database of subwaveforms and discontinuity points for normal and abnormal patients. At least one subwaveform or one or more discontinuity points are identified as a normal or abnormal electrophysiological signal of the ECG waveform from the comparison. The ECG waveform is displayed along with one or more markers at a location of the at least one subwaveform or one or more discontinuity points.

Abstract: Systems and methods for determining coefficients of an Finite Impulse Response (FIR) filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.

Abstract: The present invention is a digital dynamic compression or automatic gain control (AGC) (10) adapted for use in high quality audio and hearing aids applications. An efficient digital AGC design employs two compact ROM-based tables (ROM_CSD, ROM_SPL) in addition to two comparators (COMP_A, COMP_B) and several registers (REG_A, REG_B, ADDR_A, ADDR_B). While one ROM stores the values of discrete input signal levels, the other contains gain codes based on a canonical signed digit (CSD) coding approach that leads to a very simple gain multiplier (20). In many cases an extremely compact table for gain values can be achieved by reusing a single small-size ROM that behaves like one that is several time larger. Two design examples are shown to expound the insights of the new digital AGC design. For the less-than-half-dB-gain-step cases only two adders are required for the multiplier whereas just three adders are needed in the situations with less than quarter-dB gain steps.

Abstract: A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) shares registers which is enabled because the FIR and IIR processing do not use the registers at the same time but rather consecutively. Further, the multiplexed FIR/IIR digital filter structure (300) can offer limit-cycle-free IIR operation using two's-complement truncation in combination with positive valued allpass coefficients.

Abstract: Systems and methods for determining coefficients a filter are disclosed. The filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distnbuted values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lockup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal. Thus, the coefficient is computable in real-time without the use of previously computed and stored coefficients.

Abstract: Systems and methods for determining coefficients of an FIR filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) shares registers which is enabled because the FIR and IIR processing do not use the registers at the same time but rather consecutively. Further, the multiplexed FIR/IIR digital filter structure (300) can offer limit-cycle-free IIR operation using two's-complement truncation in combination with positive valued allpass coefficients.

Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: Systems and methods for determining coefficients of an FIR filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to &pgr;. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.

Abstract: A method for providing a multi-stage filter on an input stream of digital data. In the method, the input stream of digital data is operated on with a first polyphase filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a second polyphase filter routine. An optimizing indexing procedure is applied in performing instructions of the routines so as to execute fewer instructions that do not generate intermediate data on which the output stream of data is based.

Abstract: The present invention is a digital dynamic compression or automatic gain control (AGC) (10) adapted for use in high quality audio and hearing aids applications. An efficient digital AGC design employs two compact ROM-based tables (ROM_CSD, ROM_SPL) in addition to two comparators (COMP_A, COMP_B) and several registers (REG_A, REG_B, ADDR_A, ADDR_B). While one ROM stores the values of discrete input signal levels, the other contains gain codes based on a canonical signed digit (CSD) coding approach that leads to a very simple gain multiplier (20). In many cases an extremely compact table for gain values can be achieved by reusing a single small-size ROM that behaves like one that is several time larger. Two design examples are shown to expound the insights of the new digital AGC design. For the less-than-half-dB-gain-step cases only two adders are required for the multiplier whereas just three adders are needed in the situations with less than quarter-dB gain steps.

Abstract: A method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.