Patents by Inventor Zigmund Ramirez Camacho

Zigmund Ramirez Camacho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034692
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 9035440
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Elizar Andres, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8957515
    Abstract: An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: February 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Abelardo Jr. Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 8941219
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Patent number: 8936971
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8937393
    Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • Patent number: 8912046
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 16, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8810017
    Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8810015
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: August 19, 2014
    Assignee: STAT ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig
  • Patent number: 8802501
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8803300
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead-frame having a die attach paddle and a contact pad connected by a link; mounting an integrated circuit die over the die attach paddle; molding a package body on the lead-frame and the integrated circuit die including leaving portions of the die attach paddle, the contact pad, and the link exposed from the package body; forming an exposed edge by etching away the link between the contact pad, and the die attach paddle; and depositing a solder-resistant layer on the exposed edge.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu, Jeffrey D. Punzalan
  • Patent number: 8802555
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; attaching a circuit end of an internal interconnect to the bonding interconnect, the bonding interconnect between the circuit end and the bond pad; and connecting a lead end of the internal interconnect to the lead.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Patent number: 8786063
    Abstract: A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Arnel Senosa Trasporto
  • Patent number: 8766428
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 1, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • Patent number: 8735224
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: May 27, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Zigmund Ramirez Camacho
  • Patent number: 8729693
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 20, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Patent number: 8723338
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 8723324
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 13, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8709873
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 8698294
    Abstract: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die module is a substrate for the second die. The second die is electrically attached to the known good die module. At least the second die is additionally encapsulated.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: April 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Trasporto, Jeffrey D. Punzalan