Patents by Inventor Zoran Zivkovic

Zoran Zivkovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12282774
    Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 22, 2025
    Assignee: Intel Corporation
    Inventors: Joseph Williams, Zoran Zivkovic, Jian-Guo Chen, Hong Wan, David Dougherty, Jay O'neill
  • Publication number: 20250112659
    Abstract: Disclosed herein is an apparatus of a radio communication device, where the apparatus may include a plurality of signal paths, each signal path of the plurality of signal paths is configured to receive a radio frequency, RF, signal from a corresponding RF circuit. The apparatus may also include a processor configured to determine first signal paths and a second signal path from the plurality of signal paths, wherein the first signal paths are configured to receive first RF signals of the RF signals. The processor may also be configured to demodulate the first RF signals received from the first signal paths to decode received communication data; perform, for a frequency band, an RF environmental sensing operation based on a digital signal converted from a second RF signal of the RF signals, wherein the second RF signal is provided by the second signal path.
    Type: Application
    Filed: August 28, 2024
    Publication date: April 3, 2025
    Inventors: Wayne BALLANTYNE, David GRAHAM, Markus Dominik MUECK, Zoran ZIVKOVIC
  • Patent number: 12106101
    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Joseph Williams, Zoran Zivkovic
  • Patent number: 12072835
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: August 27, 2024
    Assignee: Intel Corporation
    Inventors: Kevin Kinney, Zoran Zivkovic
  • Publication number: 20240220249
    Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Jian-Guo Chen, David Dougherty, Madihally Narasimha, Joseph Othmer, Hong Wan, Joseph Williams, Zoran Zivkovic
  • Publication number: 20240220445
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Kannan Rajamani, Kameran Azadet, Kevin Kinney, Thomas Smith, Zoran Zivkovic
  • Publication number: 20240214248
    Abstract: An apparatus for controlling an equalizer is provided. The apparatus comprises interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer. The apparatus further comprises processing circuitry configured to determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer, select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric, and control the equalizer to operate in the selected operating mode.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Inventors: Albert MOLINA, Wayne BALLANTYNE, Kannan RAJAMANI, Benjamin JANN, Zoran ZIVKOVIC, Kameran AZADET
  • Publication number: 20240134818
    Abstract: Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 25, 2024
    Inventors: Zoran Zivkovic, Jian-Guo Chen, Jay ONeill, Joseph Williams
  • Publication number: 20240104049
    Abstract: Techniques are disclosed for a programmable processor array architecture that enables synchronized broadcasting of operation results to register files with the operation results. The architecture advantageously enables writing of operation results of a given operation to multiple destination registers in a single clock cycle for processors with partitioned register files by using common data stationary instruction encoding. This combination brings improved performance by reducing the need for costly copy operations that would otherwise occupy issue slots and thus schedule space while at the same time minimizing code size overhead. The performance gains of broadcasting are especially emphasized in highly parallel and heavily partitioned register file architectures.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Erik Rijshouwer, Jeroen Leijten, Bert Schellekens, Zoran Zivkovic
  • Publication number: 20240008045
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Kannan Rajamani, Kameran Azadet, Kevin Kinney, Thomas Smith, Zoran Zivkovic
  • Publication number: 20230418781
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Kevin Kinney, Zoran Zivkovic
  • Patent number: 11838676
    Abstract: Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventor: Zoran Zivkovic
  • Publication number: 20230205727
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • Publication number: 20230205730
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • Publication number: 20230004389
    Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.
    Type: Application
    Filed: June 25, 2021
    Publication date: January 5, 2023
    Inventors: Joseph Williams, Zoran Zivkovic, Jian-Guo Chen, Hong Wan, David Dougherty, Jay O'neill
  • Patent number: 11474825
    Abstract: An apparatus and method for performing multiply-accumulate (MAC) operations on complex numbers to generate real results.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventor: Zoran Zivkovic
  • Patent number: 11386293
    Abstract: In an example method for training image signal processors, a reconstructed image is generated via an image signal processor based on a sensor image. An intermediate loss function is generated based on a comparison of an output of one or more corresponding layers of a computer vision network and a copy of the computer vision network. The output of the computer vision network is based on the reconstructed image. An image signal processor is trained based on the intermediate loss function.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Sutic, Zoran Zivkovic, Gilad Michael
  • Publication number: 20220197640
    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Kameran Azadet, Joseph Williams, Zoran Zivkovic
  • Patent number: 11228601
    Abstract: In one embodiment, an apparatus comprises an antenna to receive one or more radio signals, wherein the antenna is associated with a proximity-based access portal. The apparatus further comprises a processor to: detect, based on the one or more radio signals, an access request from a first device, wherein the access request comprises a request to access the proximity-based access portal using an access token associated with an authorized device; determine, based on the one or more radio signals, that the first device is within a particular proximity of the proximity-based access portal; obtain a first motion history associated with movement detected near the proximity-based access portal; obtain a second motion history associated with movement detected by the authorized device; and determine, based on the first motion history and the second motion history, whether the movement detected near the proximity-based access portal matches the movement detected by the authorized device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Zoran Zivkovic, Michael E. Kounavis
  • Patent number: 11209322
    Abstract: An integrated temperature sensor comprises a chip package enclosing an integrated circuit and an ultrasonic transceiver which is integrated on top of the integrated circuit. The ultrasonic transceiver comprises a transmitting element which is arranged for emitting ultrasound waves, and a receiving element which is arranged for receiving ultrasound waves. The chip package comprises at least one barrier arranged at a defined position in the chip package. The barrier is designed to at least partly reflect ultrasound waves emitted by the transmitting element towards the receiving element. The integrated circuit comprises an actuator element to actuate the transmitting element to emit ultrasound waves according to a first signal s(t), and a converter element to convert an ultrasound wave, received by the receiving element, into a second signal y(t).
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 28, 2021
    Assignee: AMS INTERNATIONAL AG
    Inventors: Zoran Zivkovic, Casper Van Der Avoort, Willem Frederik Adrianus Besling