Method of manufacturing semiconductor device with improved gate insulation step
A first insulating film is formed on a semiconductor substrate in each of a first region in which a memory transistor is to be formed, a second region in which a selection transistor is to be formed, a third region in which a high-withstand-voltage transistor is to be formed, and a fourth region in which a low-withstand-voltage transistor is to be formed. Subsequently, the first insulating film in each of the first and second regions is removed. A second insulating film is formed on the semiconductor substrate in each of the first and second regions. A third insulating film having a trap level is formed on the second insulating film. The third insulating film in the second region and the second insulating film in the second region are removed. A fourth insulating film is formed on the third insulating film and on the semiconductor substrate in the second region.
Latest RENESAS ELECTRONICS CORPORATION Patents:
The disclosure of Japanese Patent Application No. 2020-174301 filed on Oct. 16, 2020 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
BACKGROUNDThe present invention relates to a method of manufacturing a semiconductor device, and relates to, for example, a technology effectively applied to a semiconductor device having a non-volatile memory cell.
Flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory) have been widely used as electrically programmable and erasable non-volatile memory cells. These non-volatile memory cells have a floating gate electrode or a trap insulating film sandwiched between insulating films such as oxide films under a gate electrode of a field effect transistor, and the charge state accumulated in the floating gate electrode or the trap insulating film is used as memory information. This trap insulating film refers to an insulating layer in which electric charges can be accumulated, and an example thereof is a silicon nitride film. As such a non-volatile memory cell, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistor has been widely used.
Further, in the semiconductor device, other field effect transistors such as a high-withstand-voltage transistor and a low-withstand-voltage transistor are also provided in addition to the non-volatile memory cell. Since the thickness of the gate insulating film required for each of these field effect transistors differs, each of the gate insulating films needs to be formed separately.
For example, Patent Document 1 and Patent Document 2 disclose the technology of forming two types of transistors having different withstand voltages and a non-volatile memory cell having a MONOS memory transistor and a selection transistor on a semiconductor substrate.
Also, in Patent Document 1, a first gate insulating film for a high-withstand-voltage transistor is first formed, a second gate insulating film (ONO film) for a memory transistor is formed next, and then a third gate insulating film for a low-withstand-voltage transistor is formed as shown in FIG. 6 to FIG. 13 of Patent Document 1. Here, a gate insulating film for a selection transistor is formed in the same process as the gate insulating film for the high-withstand-voltage transistor.
On the other hand, Patent Document 2 discloses a manufacturing process different from that of Patent Document 1. Specifically, a second gate insulating film (ONO film) for a memory transistor is first formed, a first gate insulating film for a high-withstand-voltage transistor is formed next, and then a third gate insulating film for a low-withstand-voltage transistor is formed as shown in FIG. 18 to FIG. 23 of Patent Document 2. Here, a gate insulating film for a selection transistor is formed in the same process as the gate insulating film for the high-withstand-voltage transistor.
There are disclosed techniques listed below.
- [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2019-79845
- [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2019-102520
In the case of the manufacturing process shown in Patent Document 1, a boundary portion between a memory transistor and a selection transistor is processed in the process of removing the first gate insulating film in the memory transistor forming region (FIG. 7 of Patent Document 1) and the process of removing the second gate insulating film in the selection transistor forming region (FIG. 10 of Patent Document 1).
However, since the margin for the misalignment of the mask is small in these processes, there is fear that the first gate insulating film is left in the memory transistor forming region or the second gate insulating film is left in the selection transistor forming region. Such a fear becomes more apparent as the miniaturization of the semiconductor device is promoted.
In order to resolve the fear and promote the miniaturization of the semiconductor device, it is necessary to precisely perform the processing of the boundary portion by using, for example, ArF excimer laser. However, the study by the inventors of this application has revealed the problem that the use of the ArF excimer laser needs the expensive exposure apparatus and the expensive exposure process.
In the case of the manufacturing process shown in Patent Document 2, the RTO (Rapid Thermal Oxidation) method is used for the process of forming the first insulating film, and the ISSG (In-Situ Steam Generation) oxidation method is used for the process of forming a top oxide film of the second insulating film (FIG. 21 of Patent Document 2).
However, the thickness of the first insulating film is larger than that of the top insulating film, and the oxidation temperature in the RTO method is higher than that in the ISSG oxidation method. Therefore, the thermal load is generated at the time of forming the first gate insulating film formed after the second gate insulating film, and this thermal load degrades the retention characteristics of the memory transistor. This problem has been revealed by the study by the inventors of this application.
In consideration of these problems, the main object of this application is to suppress the increase in the manufacturing cost of the semiconductor device and improve the reliability of the semiconductor device. Other problems and novel features will be apparent from the description of this specification and accompanying drawings.
According to an embodiment, a method of manufacturing a semiconductor device having a first region in which a memory transistor is to be formed, a second region in which a selection transistor for selecting the memory transistor is to be formed and which is adjacent to the first region, a third region in which a first field effect transistor is to be formed, and a fourth region in which a second field effect transistor is to be formed includes steps of: (a) forming a first insulating film on a semiconductor substrate in each of the first region, the second region, the third region and the fourth region; (b) after the (a), selectively removing the first insulating film in each of the first region and the second region; (c) after the (b), forming a second insulating film on the semiconductor substrate in each of the first region and the second region; (d) after the (c), forming a third insulating film having a trap level on the second insulating film in each of the first region and the second region and on the first insulating film in each of the third region and the fourth region; (e) after the (d), selectively removing the third film in the second region and the second insulating film in the second region; (f) after the (e), forming a fourth insulating film on the third insulating film in each of the first region, the third region and the fourth region and on the semiconductor substrate in the second region; (g) after the (f), selectively removing the fourth insulating film in each of the third region and the fourth region and the third insulating film in each of the third region and the fourth region; (h) after the (g), selectively removing the first insulating film in the fourth region; (i) after the (h) forming a fifth insulating film on the semiconductor substrate in the fourth region; and (j) after the (i) forming a first gate electrode of the memory transistor on the fourth insulating film in the first region, forming a second gate electrode of the selection transistor on the fourth insulating film in the second region, forming a third gate electrode of the first field effect transistor on the first insulating film in the third region, and forming a fourth gate electrode of the second field effect transistor on the fifth insulating film in the fourth region.
Further, according to an embodiment, a method of manufacturing a semiconductor device having a first region in which a memory transistor is to be formed, a second region in which a selection transistor for selecting the memory transistor to be formed and which is adjacent to the first region, a third region in which a first field effect transistor is to be formed, and a fourth region in which a second field effect transistor is to be formed includes steps of: (a) forming a first insulating film on a semiconductor substrate in each of the first region, the second region, the third region and the fourth region; (b) after the (a), selectively removing the first insulating film in each of the first region, the second region and the fourth region; (c) after the (b), forming a second insulating film on the semiconductor substrate in each of the first region, the second region and the fourth region; (d) after the (c) forming a third insulating film having a trap level on the second insulating film in each of the first region, the second region and the fourth region and on the first insulating film in the third region; (e) after the (d), selectively removing the third insulating film in the second region and the second insulating film in the second region; (f) after the (e), forming a fourth insulating film on the third insulating film in each of the first region, the third region and the fourth region and on the semiconductor substrate in the second region; (g) after the (f), selectively removing the fourth insulating film in each of the third region and the fourth region and the third insulating film in each of the third region and the fourth region; and (h) after the (g), forming a first gate electrode of the memory transistor on the fourth insulating film in the first region, forming a second gate electrode of the selection transistor on the fourth insulating film in the second region, forming a third gate electrode of the first field effect transistor on the first insulating film in the third region, and forming a fourth gate electrode of the second field effect transistor on the second insulating film in the fourth region.
According to an embodiment, it is possible to improve the reliability of the semiconductor device and suppress the increase in the manufacturing cost of the semiconductor device.
Hereinafter, embodiments will be described in detail with reference to the drawings. Note that members having the same function are denoted by the same reference characters throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In addition, the description of the same or similar portions is not repeated in principle unless particularly required in the following embodiments.
Also, in this application, hatching is omitted even in a cross-sectional view and hatching is used even in a plan view so as to make the drawings easy to see.
Further, the X direction, the Y direction and the Z direction in the description of this application orthogonally cross each other. In this application, the Z direction is described as a vertical direction, a height direction or a thickness direction of a certain structure in some cases.
First EmbodimentThe semiconductor device and the method of manufacturing the same according to the first embodiment will be described below with reference to
<Main Structure of Semiconductor Device>
The regions 1A and 2A, the region 3A, and the region 4A are partitioned by an element isolation portion STI. Each of the transistors 1Q to 4Q is formed in an active region of the semiconductor substrate surrounded by the element isolation portion STI. In
The memory transistor 1Q in the first embodiment is a MONOS transistor. A pair of the memory transistor 1Q and the selection transistor 2Q constitutes a non-volatile memory cell (memory cell) MC, and a plurality of memory cells MC is formed in the region 1A and the region 2A. A gate electrode GE1 of the memory transistor 1Q and a gate electrode GE2 of the selection transistor 2Q extend in the Y direction, and are used in common by the plurality of memory cells MC adjacent in the Y direction.
The high-withstand-voltage transistor 3Q is, for example, a field effect transistor composing part of an I/O (Input/Output) circuit. The low-withstand-voltage transistor 4Q is, for example, a field effect transistor composing a logic circuit including a CPU (Central Processing Unit) and an SRAM (Static Random Access Memory). The low-withstand-voltage transistor 4Q is driven by a voltage lower than that of the high-withstand-voltage transistor 3Q and has a gate insulating film thinner than a gate insulating film of the high-withstand-voltage transistor 3Q.
Also, in
Note that each of the transistors 1Q to 4Q is an n type field effect transistor. Actually, a p type field effect transistor is also formed in the region 3A and the region 4A, but the description of the p type field effect transistor will be omitted in the following description.
The memory transistor 1Q has a gate insulating film GI1, the gate electrode GE1 and a channel region CH1. The selection transistor 2Q has a gate insulating film GI2, the gate electrode GE2 and a channel region CH2. The high-withstand-voltage transistor 3Q has a gate insulating film GI3, a gate electrode GE3 and a channel region CH3. The low-withstand-voltage transistor 4Q has a gate insulating film GI4, a gate electrode GE4 and a channel region CH4.
Further, each of the transistors 1Q to 4Q has a sidewall spacer SW, an extension region (impurity region) EX, a diffusion region (impurity region) DR and a silicide layer SI.
The gate insulating film GI1 includes an insulating film IF2 formed on a semiconductor substrate SUB, an insulating film CSL formed on the insulating film IF2 and an insulating film IF4 formed on the insulating film CSL. The insulating film CSL is an insulating film having a trap level and functions as a charge storage layer of the memory transistor 1Q.
The gate insulating film GI2 includes the insulating film IF4 formed on the semiconductor substrate SUB. The gate insulating film GI3 includes an insulating film IF1 formed on the semiconductor substrate SUB. The gate insulating film GI4 includes an insulating film IF5 formed on the semiconductor substrate SUB.
Each of the gate electrodes GE1 to GE4 is formed on each of the gate insulating films GI1 to GI4. The sidewall spacer SW is formed on both side surfaces of each of the gate electrodes GE1 to GE4.
The extension region EX is formed in the semiconductor substrate SUB located on both sides of each of the gate electrodes GE1 to GE4, and the diffusion region DR is formed in the semiconductor substrate SUB located on both sides of each of the gate electrodes GE1 to GE4 via the sidewall spacer SW. The diffusion region DR has an impurity concentration higher than that of the extension region EX, and constitutes a source region or a drain region of each of the transistors 1Q to 4Q together with the extension region EX.
Each of the channel regions CH1 to CH4 is formed in the semiconductor substrate SUB located under each of the gate electrodes GE1 to GE4, and is formed between the extension regions EX of the regions 1A to 4A.
The silicide layer SI is formed on each upper surface of the gate electrodes GE1 to GE4 and the diffusion region DR.
The main feature of this application lies in the process for forming the gate insulating films GI1 to GI4. Hereinafter, the forming method of the configuration including each of the gate insulating films GI1 to GI4 and the thicknesses and materials of the gate insulating films GI1 to GI4 will be described.
<Method of Manufacturing Semiconductor Device>
Next, the method of manufacturing the semiconductor device according to the first embodiment will be described below with reference to
First, as shown in
Next, p type well regions PW1 to PW3 are formed in the semiconductor substrate SUB by the photolithography technique and the ion implantation method. First, the well region PW1 is formed in the semiconductor substrate SUB in the region 1A and the region 2A. Next, the well region PW2 is formed in the semiconductor substrate SUB in the region 3A, and the channel region CH3 is subsequently formed in the surface of the well region PW2 by performing the ion implantation for adjusting the threshold of the high-withstand-voltage transistor 3Q. Then, the well region is formed in the semiconductor substrate SUB in the region 4A, and the channel region CH4 is subsequently formed in the surface of the well region PW3 by performing the ion implantation for adjusting the threshold of the low-withstand-voltage transistor 4Q.
Note that the order of forming each of the well regions PW1 to PW3 is not particularly limited, and any of the regions may be formed first.
Next, as shown in
Note that the RTO method in the first embodiment is the method of forming a silicon oxide film by placing the semiconductor substrate SUB in a chamber of a heating apparatus and heating the semiconductor substrate SUB by irradiating the semiconductor substrate SUB with a large number of lamps while introducing oxygen gas into the chamber. The oxidation treatment for forming the insulating film IF1 is performed under the conditions of, for example, 1050° C. to 1100° C. and 10 to 20 seconds.
Further, when it is simply described as “by the thermal oxidation method” in the following description, the “thermal oxidation method” is the method generally referred to as dry oxidation or steam oxidation. These oxidation treatments are performed under the conditions of 800° C. to 950° C. and several minutes to several tens of minutes, though depending on the thickness of the insulating film to be formed.
Next, as shown in
Next, the insulating film IF1 in the region 1A and the region 2A is selectively removed using the resist pattern RP1 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Thereafter, the resist pattern RP1 is removed by, for example, the ashing treatment.
Here, since the resist pattern RP1 can be used in both the process of forming the channel region CH1 and the process of removing the insulating film IF1, the number of masks can be reduced.
Next, as shown in
Next, the insulating film CSL made of, for example, silicon nitride is formed on the insulating film IF2 in each of the region 1A and the region 2A and on the insulating film IF1 in each of the region 3A and the region 4A by, for example, the CVD (Chemical Vapor Deposition) method or the ALD (Atomic Layer Deposition) method. The thickness of the insulating film CSL is, for example, 7 nm to 10 nm.
Next, an insulating film IF3 made of, for example, silicon oxide is formed on the insulating film CSL in each of the regions 1A to 4A by, for example, the CVD method. The thickness of the insulating film IF3 is, for example, 4 nm to 6 nm. The insulating film IF3 is formed so as to function mainly as a protective film (mask) for protecting each insulating film formed below the insulating film IF3 when removing the insulating film CSL in the subsequent manufacturing process.
Next, as shown in
Next, the insulating film IF3 in the region 2A is selectively removed using the resist pattern RP2 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Thereafter, the resist pattern RP2 is removed by, for example, the asking treatment.
Here, since the resist pattern RP2 can be used in both the process of forming the channel region CH2 and the process of removing the insulating film IF3, the number of masks can be reduced. Note that either the process of forming the channel region CH2 or the process of removing the insulating film IF3 may be performed first.
Next, as shown in
Next, as shown in
Next, as shown in
Note that the ISSG oxidation method in the first embodiment is the method of forming a silicon oxide film by placing the semiconductor substrate SUB in the chamber of the heating apparatus, directly introducing hydrogen and oxygen into the chamber, and generating water vapor on the heated semiconductor substrate SUB to cause the radical oxidation reaction. The oxidation treatment for forming the insulating film IF4 is performed under the conditions for example, 900° C. and the hydrogen concentration of 10% or more.
Further, in the ISSG oxidation method, not only the surface of the semiconductor substrate SUB made of silicon but also the surface of the insulating film CSL made of silicon nitride can be oxidized. Since the oxidation rates of these are slightly different, the thickness of the insulating film IF4 in the region 2A is larger than the thickness of the insulating film IF4 in each of the region 1A, the region 3A and the region 4A.
Next, as shown in
Next, the insulating film IF4 in the region 3A and the region is selectively removed using the resist pattern RP3 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Then, the resist pattern RP3 is removed by, for example, the ashing treatment.
Next, as shown in
Next, as shown in
Next, the insulating film IF1 in the region 4A is selectively removed using the resist pattern RP4 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Then, the resist pattern RP4 is removed by, for example, the ashing treatment.
Next, as shown in
Next, as shown in
In this manner, the gate electrode GE1 of the memory transistor 1Q is formed on the insulating film IF4 in the region 1A, the gate electrode GE2 of the selection transistor 2Q is formed on the insulating film IF4 in the region 2A, the gate electrode GE3 of the high-withstand-voltage transistor 3Q is formed on the insulating film IF1 in the region 3A, and the gate electrode GE4 of the low-withstand-voltage transistor 4Q is formed on the insulating film IF5 in the region 4A.
Thereafter, each of the transistors 1Q to 4Q shown in
First, each insulating film exposed from each of the gate electrodes GE1 to GE4 is removed by performing the dry etching process and the wet etching process to the exposed insulating film.
Consequently, the insulating film IF4, the insulating film CSL and the insulating film IF2 left under the gate electrode GE1 in the region 1A become the gate insulating film GI1. Also, the insulating film IF4 left under the gate electrode GE2 in the region 2A becomes the gate insulating film GI2, the insulating film IF1 left under the gate electrode GE3 in the region 3A becomes the gate insulating film GI3, and the insulating film IF5 left under the gate electrode GE4 in the region 4A becomes the gate insulating film GI4.
Next, the n type extension region EX is formed in the semiconductor substrate SUB on both sides or each of the gate electrodes GE1 to GE4 by the photolithography technique and the ion implantation method.
Next, an insulating film made of, for example, silicon nitride is formed by, for example, the CVD method so as to cover each of the gate electrodes GE1 to GE4 in each of the regions 1A to 4A. Subsequently, by performing the anisotropic etching to this insulating film, the sidewall spacer SW is formed on each side surface of each of the gate electrodes GE1 to GE4.
Next, the n type diffusion region DR is formed in the semiconductor substrate SUB on both sides of each of the gate electrodes GE1 to GE4 via the sidewall spacer SW by the photolithography technique and the ion implantation method.
Next, the silicide layer SI is formed on each upper surface of the gate electrodes GE1 to GE4 and the diffusion region DR by the salicide (Self Aligned Silicide) technique. The silicide layer SI can be formed by reacting the materials composing the gate electrodes GE1 to GE4 and the semiconductor substrate SUB with the metal film. The metal film is made of, for example, cobalt, nickel or nickel-platinum alloy, and the silicide layer SI is made of, for example, cobalt silicide (CoSi2), nickel silicide (NiSi) or nickel platinum silicide (NiPtSi).
The semiconductor device according to the first embodiment is manufactured in the manner described above.
Here, the relationship in the thickness of each of the gate insulating films GI2 to GI4 will be summarized. In the first embodiment, at the time of the manufacturing process of
In Patent Document 1 described above, the gate insulating film GI1 and the gate insulating film GI2 are processed at the boundary portion between the memory transistor 1Q (region 1A) and the selection transistor 2Q (region 2A), and there is fear that the gate insulating film GI1 or the gate insulating film GI2 is left in the boundary portion. Namely, in Patent Document 1 described above, the gate insulating film for the memory transistor and the gate insulating film for the selection transistor are completed in different manufacturing processes. Thus, in order to resolve such a fear and promote the miniaturization of the semiconductor device, for example, the use of the ArF excimer laser is necessary, and there is the problem that the expensive exposure apparatus and the expensive exposure process are required.
On the other hand, in the first embodiment, after the insulating film IF3, the insulating film CSL and the insulating film IF2 in the region 2A are removed by the manufacturing process of
Also, the use of the expensive ArF excimer laser for resolving such a fear is not required. For example, the resist patterns RP1 to RP4 used in the first embodiment are formed using the KrF excimer laser. Therefore, it possible to suppress the increase in the manufacturing cost of the semiconductor device. Also, according to the manufacturing method described with reference to
Further in Patent Document 2 described above, the oxidation treatment by the RTO method is performed after the oxidation treatment by the ISSG oxidation method (after forming the gate insulating film GI2), and thus, there is a problem that the retention characteristics of the memory transistor 1Q are degraded due to the thermal load of the oxidation treatment by the RTO method.
On the other hand, in the first embodiment, the gate insulating film GI1 is formed after the RTO method is used for forming the insulating film IF1 in
Further, in the manufacturing method according to the first embodiment, as shown in
Incidentally, with the miniaturization of the semiconductor device, the performance improvement such as high speed operation and low power consumption has been demanded for the memory cell MC (memory transistor 1Q, selection transistor 2Q) and the low-withstand-voltage transistor 4Q. Meanwhile, it is necessary for the high-withstand-voltage transistor 3Q to ensure the withstand voltage rather than the high speed operation and the low power consumption due to its nature of being used for the I/O circuit or the like.
In Patent Document 1 and Patent Document 2, since the gate insulating film GI2 of the selection transistor 2Q is formed in the same process as the gate insulating film GI3 of the high-withstand-voltage transistor 3Q, the gate insulating film GI2 is a relatively thick insulating film. Also, in Patent Document 1 and Patent Document 2, the thickness of the gate insulating film GI2 of the selection transistor 2Q is the same as the thickness of the gate insulating film GI3 of the high-withstand-voltage transistor 3Q. Therefore, it is difficult to improve the performance of the selection transistor 2Q.
On the other hand, in the first embodiment, the gate insulating film GI2 of the selection transistor 2Q is the insulating film IF4 and is a relatively thin insulating film. Namely, the thickness of the gate insulating film GI2 of the selection transistor 2Q is smaller than the thickness of the gate insulating film GI3 of the high-withstand-voltage transistor 3Q. Here, in recent years, not only the miniaturization of the semiconductor device but also the low power consumption has been demanded. For example, the gate length of the field effect transistor is 45 nm or less (45 nm or more in conventional art) and the operational voltage is 2.5 V or lower (2.5 V or higher in conventional art). Therefore, in the semiconductor device taking the low power consumption into consideration, it is not always necessary that the gate insulating film GI2 of the selection transistor 2Q is formed to have a relatively large thickness as in Patent Document 1 and Patent Document 2. Consequently, from the viewpoint of improving performance such as high speed operation and low power consumption, the semiconductor device according to the first embodiment is superior to the semiconductor devices of Patent Document 1 and Patent Document 2.
Though not described in detail, the process of cleaning the main surface of the semiconductor substrate SUB is performed many times during the manufacturing process shown in
By these cleaning process and wet etching process, the upper surface of the element isolation portion STI is gradually recessed. Further, on the upper surface of the element isolation portion STI, a divot (dent) DV provided at the time of forming the element isolation portion STI is present around the boundary between the element isolation portion STI and the active region of the semiconductor substrate SUB.
In each of the manufacturing processes of
The method of manufacturing the semiconductor device according to the second embodiment will be described below with reference to
In the second embodiment, the transistors 1Q to 4Q are manufactured by the manufacturing process different from that of the first embodiment. The manufacturing process of the second embodiment is the same as that of the first embodiment up to
Since the thicknesses of the insulating films IF1 to IF4 and the insulating film CSL in the second embodiment are the same as those of the first embodiment, the description thereof will be omitted.
As shown in
Next, the insulating film IF1 in each of the region 1A, the region 2A and the region 4A is selectively removed using the resist pattern RP5 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Thereafter, the resist pattern RP5 is removed by, for example, the asking treatment.
Here, since the resist pattern RP5 can be used in both the process of forming the channel region CH1 and the process of removing the insulating film IF1, the number of masks can be reduced.
Next, as shown in
Next, the insulating film CSL made of, for example, silicon nitride is formed on the insulating film IF2 in each of the region 1A, the region 2A and the region 4A and on the insulating film IF1 in the region 3A by, for example, the CVD method or the ALD method. Next, the insulating film IF3 made of, for example, silicon oxide is formed on the insulating film CSL in each of the regions 1A to 4A by, for example, the CVD method.
Next, as shown in
Next, the insulating film IF3 in the region 2A is selectively removed using the resist pattern RP6 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Thereafter, the resist pattern RP6 is removed by, for example, the ashing treatment.
Here, since the resist pattern RP6 can be used in both the process of forming the channel region CH2 and the process of removing the insulating film IF3, the number of masks can be reduced. Note that either the process of forming the channel region CH2 or the process of removing the insulating film IF3 may be performed first.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, the insulating film IF4 in the region 3A and the region 4A is selectively removed using the resist pattern RP7 as a mask by, for example, the wet etching process using a solution containing hydrofluoric acid. Then, the resist pattern RP7 is removed by, for example, the ashing treatment.
Next, as shown in
Next, as shown in
In this manner, the gate electrode GE1 of the memory transistor 1Q is formed on the insulating film IF4 in the region 1A, the gate electrode GE2 of the selection transistor 2Q is formed on the insulating film IF4 in the region 2A, the gate electrode GE3 of the high-withstand-voltage transistor 3Q is formed on the insulating film IF1 in the region 3A, and the gate electrode GE4 of the low-withstand-voltage transistor 4Q is formed on the insulating film IF2 in the region 4A.
Thereafter, each of the transistors 1Q to 4Q shown in
The relationship in the thickness of each of the gate insulating films GI2 to GI4 in the second embodiment will be described below. In the second embodiment, at the time of the manufacturing process of
The method of manufacturing a semiconductor device according to the second embodiment can obtain the same effect as that of the first embodiment and can simplify the manufacturing process. This is because, unlike the first embodiment, the gate insulating film GI4 in the region 4A in the second embodiment is composed of the insulating film IF2 composing the gate insulating film GI1 of the memory transistor 1Q. Namely, the gate insulating film GI4 in the region 4A can be formed by the same process as the process of forming the insulating film IF2 which is part of the gate insulating film GI1 in the region 1A.
Further, the thickness of the insulating film IF2 is preferably designed by giving priority to the characteristics of the memory transistor 1Q. Therefore, for example, the case in which the thickness of the gate insulating film GI4 is too small to satisfy the characteristics required for the low-withstand-voltage transistor 4Q is assumed. However, in such a case, by forming a high-dielectric-constant film on the insulating film IF2 in the region 4A, the gate insulating film GI4 composed of the insulating film IF2 and the high-dielectric-constant film can be formed.
For example, the high-dielectric-constant film can be formed through the following manufacturing process.
First, after the manufacturing process of
Next, the high-dielectric-constant film in each of the region 1A, the region 2A and the region 3A is selectively removed using the resist pattern as a mask by, for example, the dry etching process. Then, the resist pattern is removed by, for example, the ashing treatment. The subsequent manufacturing process is the same as that in
Note that the high-dielectric-constant film has a dielectric constant higher than that of the silicon oxide film and is made of a metal oxide film. As the metal oxide film, for example, a hafnium oxide film (HfO2 film), a hafnium silicate film (HfSiO film), an aluminum oxide film (Al2O3 film), a tantalum oxide film (Ta2O5 film), a zirconium oxide film (ZrO2 film) or a stacked film of these films can be applied.
(First Modification)
As the first modification of the first embodiment and the second embodiment, the technique of adopting an SOI (Silicon On Insulator) substrate in the region 4A can be presented. In this case, the low-withstand-voltage transistor 4Q is formed on the SOI substrate.
The SOI substrate includes a semiconductor substrate SUB as a support substrate, an insulating layer BOX formed on the semiconductor substrate SUB and a semiconductor layer SL formed on the insulating layer BOX. The insulating layer BOX is made of, for example, silicon oxide, and the thickness of the insulating layer BOX is, for example, 10 nm to 20 nm. The semiconductor layer SL is made of single crystal silicon, and the thickness of the semiconductor layer SL is, for example, 10 nm to 20 nm.
The manufacturing method in the case of adopting such an SOI substrate is as follows.
First, before the manufacturing process in
Thereafter the manufacturing process shown in
(Second Modification)
As the second modification of the first embodiment and the second embodiment, the technique of composing the memory transistor 1Q from another memory element different from the MONOS transistor can be presented.
As the different memory element, for example, a memory element having a memory film MF shown in
The memory film MF is a high-dielectric-constant film having a trap level and the high-dielectric-constant film is, for example, a hafnium silicate film (HfSiO film). As another example of the memory film MF, a ferroelectric film can be presented. The ferroelectric film is, for example, a BZT film composed as (Ba, Ca) TiO3 or a PLZT film composed as PbZrTiO3.
The memory film MF like this can be formed by the process replaced with the process of forming the insulating film CSL. Also, the thickness relationship of each of the gate insulating films GI2 to GI4 is the same as that of the first embodiment and the second embodiment.
In the foregoing, the present invention has been specifically described based the embodiments, but the present invention is not limited to the embodiments described above and can be variously modified within the range not departing from the gist thereof.
For example, it has been described that the insulating film IF1 is formed by the RTO method in the first embodiment, the second embodiment, the first modification and the second modification, but the insulating film IF1 may be formed by the ISSG oxidation method or by the combined use of the RTO method and the ISSG oxidation method.
Claims
1. A method of manufacturing a semiconductor device having a first region in which a memory transistor is to be formed, a second region in which a selection transistor for selecting the memory transistor is to be formed and which is adjacent to the first region, a third region in which a first field effect transistor is to be formed, and a fourth region in which a second field effect transistor is to be formed, comprising steps of:
- (a) forming a first insulating film on a semiconductor substrate in each of the first region, the second region, the third region and the fourth region;
- (b) after the (a), selectively removing the first insulating film in each of the first region and the second region;
- (c) after the (b), forming a second insulating film on the semiconductor substrate in each of the first region and the second region;
- (d) after the (c), forming a third insulating film having a trap level on the second insulating film in each of the first region and the second region and on the first insulating film in each of the third region and the fourth region;
- (e) after the (d), selectively removing the third insulating film in the second region and the second insulating film in the second region;
- (f) after the (e), forming a fourth insulating film on the third insulating film in each of the first region, the third region and the fourth region and on the semiconductor substrate in the second region;
- (g) after the (f), selectively removing the fourth insulating film in each of the third region and the fourth region and the third insulating film in each of the third region and the fourth region;
- (h) after the (g), selectively removing the first insulating film in the fourth region;
- (i) after the (h), forming a fifth insulating film on the semiconductor substrate the fourth region; and
- (j) after the (i), forming a first gate electrode of the memory transistor on the fourth insulating film in the first region, forming a second gate electrode of the selection transistor on the fourth insulating film in the second region, forming a third gate electrode of the first field effect transistor on the first insulating film in the third region, and forming a fourth gate electrode of the second field effect transistor on the fifth insulating film in the fourth region.
2. The method of manufacturing the semiconductor device according to claim 1,
- wherein, in the (j), a thickness of the first insulating film in the third region is larger than each of a thickness of the fourth insulating film in the second region and a thickness of the fifth insulating film in the fourth region, and the thickness of the fourth insulating film in the second region is larger than the thickness of the fifth insulating film in the fourth region.
3. The method of manufacturing the semiconductor device according to claim 1,
- wherein each of the first insulating film, the second insulating film, the fourth insulating m and the fifth insulating film is a silicon oxide film, and
- wherein the third insulating film is a silicon nitride film.
4. The method of manufacturing the semiconductor device according to claim 3,
- wherein, in the (f), the fourth insulating film is formed by ISSG oxidation method.
5. The method of manufacturing the semiconductor device according to claim 4,
- wherein, in the (a), the first insulating film is formed by RTO method.
6. The method of manufacturing the semiconductor device according to claim 3, further comprising a step of:
- (k) after the (d) and before the (e), forming a sixth insulating film which is a silicon oxide film on the third insulating film in each of the first region, the second region, the third region and the fourth region,
- wherein the (e) includes steps of: (e1) selectively removing the sixth insulating film in the second region; (e2) after the (e1), selectively removing the third insulating film in the second region by using the sixth insulating film in each of the first region, the third region and the fourth region as a mask; and (e3) after the (e2), removing the sixth insulating film in each of the first region, the third region and the fourth region and the second insulating film in the second region.
7. The method of manufacturing the semiconductor device according to claim 6,
- wherein the (e1) includes steps of: (e11) forming a resist pattern having an opening pattern exposing the second region so as to cover the first region, the third region and the fourth region; (e12) after the (e11), performing ion implantation for adjusting a threshold of the selection transistor to the semiconductor substrate in the second region by using the resist pattern as a mask; (e13) after the (e11), selectively removing the sixth insulating film in the second region by using the resist pattern as a mask; and (e14) after the (e12) and the (e13), removing the resist pattern.
8. The method of manufacturing the semiconductor device according to claim 1, further comprising steps of:
- (l) before the (a), providing an SOI substrate having the semiconductor substrate, an insulating layer formed on the semiconductor substrate and a semiconductor layer formed on the insulating layer; and
- (m) after the (l) and before the (a), selectively removing the semiconductor layer in each of the first region, the second region and the third region and the insulating layer in each of the first region, the second region and the third region,
- wherein each of the first insulating film in the fourth region formed in the (a) and the fifth insulating film in the fourth region formed in the (i) is formed on the semiconductor layer.
10211213 | February 19, 2019 | Mihara |
10411121 | September 10, 2019 | Yamamoto |
10446401 | October 15, 2019 | Makiyama |
10546865 | January 28, 2020 | Katou |
20030030123 | February 13, 2003 | Ichige |
20030198086 | October 23, 2003 | Shukuri |
20050195630 | September 8, 2005 | Arigane |
20070293029 | December 20, 2007 | Ogawa |
20100025754 | February 4, 2010 | Shiba |
20140179076 | June 26, 2014 | Shinohara |
20140227839 | August 14, 2014 | Shinohara |
20140227843 | August 14, 2014 | Tsukamoto |
20160064507 | March 3, 2016 | Amo |
20160086961 | March 24, 2016 | Owada |
20160260795 | September 8, 2016 | Abe |
20170062445 | March 2, 2017 | Yamashita |
20180047742 | February 15, 2018 | Yamakoshi |
20190244968 | August 8, 2019 | Abe |
2019-079845 | May 2019 | JP |
2019-102520 | June 2019 | JP |
Type: Grant
Filed: Oct 13, 2021
Date of Patent: Nov 5, 2024
Patent Publication Number: 20220123000
Assignee: RENESAS ELECTRONICS CORPORATION (Tokyo)
Inventor: Yuto Omizu (Tokyo)
Primary Examiner: Didarul A Mazumder
Assistant Examiner: Gustavo G Ramallo
Application Number: 17/500,297
International Classification: H10B 41/35 (20230101); H01L 27/12 (20060101); H10B 43/35 (20230101);