METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN
A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
This application is related to our copending U.S. Patent Application, (Attorney Docket No. SC-13377TP) entitled “Double Gate Device Having A Heterojunction Source/Drain and a Strained Channel”, filed simultaneously herewith and assigned to the assignee hereof.
FIELD OF THE INVENTIONThis invention relates generally to semiconductor, and more specifically, to making semiconductor devices having very small dimensions.
BACKGROUND OF THE INVENTIONSemiconductor devices, such as transistor structures, continue to be scaled to smaller dimensions as process lithography improves. However, different challenges have been encountered in the scaling of transistor structures much below 100 nm. Additionally, when transistor dimensions on the order of 100 nm and smaller are used, implants cannot be adequately controlled with conventional semiconductor fabrication equipment. Channel dopant fluctuations adversely affect device uniformity within circuits. To control a conventional bulk transistor's threshold voltage which is the voltage at which the transistor becomes conductive, dopants in the channel are used. However, channel doping is not an efficient method for ultra-thin devices due to the large amount of channel impurities that are required. Therefore, highly doped ultra-thin devices are even more susceptible to threshold voltage fluctuations. Additionally, high channel doping concentrations degrade both electron and hole mobility and promote source/gate and drain/gate junction leakage.
A technique to improve bulk transistor performance is to provide a bulk transistor having a strained channel. Such devices are structured to place a strain on the transistor's channel. An appropriately strained channel results in electron and hole mobility enhancement that increases the conduction current which provides a higher device drive performance.
One method to form a transistor having a strained channel is to recess silicon material in those areas where the source and drain are to be formed and re-grow a stressor material in the recessed areas. However, when thin-body devices are being implemented, the depth available for the stressor material is insufficient to adequately strain the channel. Another issue with this technique is that the silicon material is recessed with an etch process. Stopping the etch process at a desired depth is a challenge and subject to variation. Additionally, re-growth of the stressor material on the remaining ultra-thin silicon is problematic. Also, the ultra-thin silicon can agglomerate at temperatures required for growing the stressor material. Additionally, this method does not apply to the known FINFET structures or any thin-body transistor devices.
Another known method to induce stress into a channel is the use of a substrate as a stressor material. A shortcoming with this approach is that when the stressor material is SiGe, the SiGe causes degradation of the gate dielectric due to increased interface states when the Ge diffuses to the dielectric semiconductor interface. The material SiGe has a narrow bandgap. Therefore, another issue with this approach is that the presence of SiGe in the transistor's channel increases the transistor's off-state current leakage. Additionally, this method does not apply to the known FINFET structures or any vertical thin body double gate transistor.
Yet another known method of stressing a transistor channel is the use of overlying stress inducing layers over the active regions of the transistor. However, the stressor material is located far enough from the channel so that the influence of the stressor material on the channel is diminished.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
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In an alternative form, the diffusion of Ge into stressor material layer 30 is continued with additional thermal processing or oxidation according to the requirements of a particular semiconductor device. In one embodiment the additional processing is continued until a uniform material exists in both the stressor material layer 30 and the strained channel 17. In this form, a compressive material exists uniformly laterally in the source, the channel and the drain. The substantially uniform compressive layer that extends through the channel from the source and the drain is desirable for P-channel conductivity transistors. The remaining drawings will however illustrate a structure wherein such additional processing is not implemented and will illustrate different channel and source/drain materials.
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In an alternative form, the diffusion of Ge into stressor layer 76 is continued with additional thermal processing or oxidation according to the requirements of a particular semiconductor device. In one embodiment the additional processing is continued until a uniform material exists in both the stressor layer 76 and the strained channel 63. In this form, a compressive material exists uniformly laterally in the source, the channel and the drain. The substantially uniform compressive layer that extends through the channel from the source and the drain is desirable for P-channel conductivity transistors. In such an embodiment, there are no heterojunctions in the channel.
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By now it should be appreciated that there have been provided methods for forming a semiconductor device having a strained channel that provides improved transistor performance. A heterojunction, raised source/drain regions and strained channel combine to significantly improve transistor device performance. Methods of formation are herein described in the context of forming both a bulk transistor device and a double gate transistor device. In one form there is provided a method for forming a semiconductor device by providing a semiconductor layer and providing a gate dielectric overlying a first portion of the semiconductor layer. A gate electrode is provided overlying the gate dielectric. The gate electrode and the gate dielectric are encapsulated. A stressor source material is selectively grown overlying a second portion of the semiconductor layer outside the first portion. The stressor material is changed into a diffusion source, wherein changing the stressor material into the diffusion source includes tailoring an amount of diffusion of the stressor material into a channel region of the underlying semiconductor layer. The channel becomes a strained channel.
As the dimensions of thin body transistors continue to grow smaller, a thinner channel region causes threshold voltage of the transistor to increase. By using the materials described herein, such as SiGe, etc., for the semiconductor layer from which the channel is formed, the threshold voltage is lowered and thereby offsets the increase in conventional thin body transistors when scaled to a smaller dimension. Additionally, when mid-gap metals are used as a gate material, a higher transistor threshold voltage. To counteract the rising threshold voltage, the body of the transistor can be doped. However, the doping degrades electrical performance of the transistor and results in increased variability in operating parameters. The use of a source material to provide controlled diffusion into the source/drain and channel regions allows low Vt transistors with mid-gap metal gates and without doping the body.
In one form there is herein provided a method for forming a semiconductor device wherein a semiconductor layer is provided. A gate dielectric is provided overlying a first portion of the semiconductor layer. A gate electrode is provided overlying the gate dielectric. The gate electrode and the gate dielectric are encapsulated with an encapsulant. A semiconductor material is selectively grown overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material is a material different from a material of the semiconductor layer. The semiconductor material is used as a diffusion source to control an amount of diffusion of the semiconductor material into a channel region of the semiconductor layer. The diffusion of the semiconductor material into the channel region produces a strained channel. In one form the semiconductor material is used as a diffusion source and a thermal anneal process is used to control an amount of diffusion source diffusion into the channel region of the semiconductor layer. In another form the thermal anneal process includes is a short duration high temperature anneal and a long duration low temperature anneal, wherein short is less than long and high is greater than low. In another form the thermal anneal process further includes one of a hydrogen chloride (HCl) ambient and an inert gas ambient of different temperature and time duration to control an amount of semiconductor material diffusion into the channel region and an amount of strain to be induced in the strained channel of the semiconductor device. In another form the semiconductor material includes at least one selected from the group consisting of a source of germanium, carbon doped silicon, boron, phosphorus and arsenic. In another form the inert gas ambient includes at least one of nitrogen and argon. In one form the semiconductor material is used as a diffusion source and an oxidation of the semiconductor material is performed to produce effects of condensation as one component of the semiconductor material is preferentially consumed and diffused by formation of an oxide and diffused by a semiconductor material enrichment of the semiconductor layer. The oxide is selectively removed with respect to the encapsulant that encapsulates the gate electrode and the gate dielectric. In one form a layer of another semiconductor material is selectively grown by selective epitaxy. In another form the another semiconductor material includes one of a same initial semiconductor material and a different semiconductor material. In another form the semiconductor material is repeatedly used as a diffusion source, the oxide is selectively removed, and the layer of another semiconductor material is selectively grown to achieve a desired amount of semiconductor material enrichment in the channel region of the semiconductor layer. In another form the selectively removing includes using a wet etch process. In one form the semiconductor material includes SiGe, and Si is preferentially consumed and Ge is preferentially diffused and enriched by formation of the oxide SiO2. In another form the method further includes selectively removing the oxide SiO2 with respect to the encapsulant that encapsulates the gate electrode and the gate dielectric. A layer of another semiconductor material is selectively grown by epitaxy. In another form source/drain extension region implants are formed and a dopant activation anneal implemented. Sidewall spacers are formed adjacent the gate electrode. Source/drain region implants are performed to create a source/drain. Regions of the source/drain and the gate electrode are silicided in one form. In one form the semiconductor layer includes providing a semiconductor on insulator substrate. In another form the semiconductor on insulator substrate includes a silicon on insulator substrate. In another form the encapsulating includes using an encapsulant for minimizing oxygen diffusion into the gate electrode and the gate dielectric. In yet another form encapsulating the gate electrode includes using an encapsulatant selected from the group of nitride, oxide and a combination of nitride and oxide. In another form the semiconductor material includes silicon germanium (SiGe) with a predetermined Ge concentration. In yet another form for a predetermined thickness of the semiconductor material, the predetermined Ge concentration is inversely proportional to the predetermined thickness, and a function of an oxidation time, in order to preserve a total amount of Ge to be diffused into the semiconductor layer. In yet another form the predetermined Ge concentration is greater than 15%. In another form the semiconductor material diffuses vertically into the semiconductor layer and further diffuses laterally within the semiconductor layer to a source/channel interface and a drain/channel interface to form heterojunctions at respective interfaces of the channel region. In one form the semiconductor device includes one of a lateral device and a FinFET device. In yet another form the semiconductor material is a material selected for obtaining a desired threshold voltage for the semiconductor device.
In yet another form there is provided a method for forming a transistor. A semiconductor layer is provided. A gate dielectric overlying a first portion of the semiconductor layer is provided. A gate electrode overlying the gate dielectric is provided. The gate electrode and the gate dielectric are encapsulated with a dielectric layer. A semiconductor material is selectively grown overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer. The semiconductor material is oxidized in an oxygen ambient to form a stressor layer from the second portion of the semiconductor layer thereby forming a strained channel within the first portion of the semiconductor layer. Source and drain regions are formed in the second portion of the semiconductor layer and the semiconductor material.
In a further form there is provided a method for forming a transistor. A semiconductor layer is provided. A gate dielectric is provided overlying a first portion of the semiconductor layer. A gate electrode of the transistor is provided overlying the gate dielectric. The gate electrode and the gate dielectric are encapsulated. A semiconductor material containing germanium is selectively grown overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material is a material different from a material of the semiconductor layer. The semiconductor material is heated to diffuse germanium into the second portion of the semiconductor layer thereby forming a strained channel underlying the gate dielectric. Source and drain regions of the transistor are formed in the second portion of the semiconductor layer and the semiconductor material.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, silicon carbon or any material that forms an alloy with silicon may be used in lieu of silicon germanium. Various conductivities may be used and differing doping concentrations may be used. Various transistor structures may implement the strained channel methods taught herein including various multiple gate structures, including double gate structures. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
Claims
1. A method for forming a semiconductor device, comprising:
- providing a semiconductor layer;
- providing a gate dielectric overlying a first portion of the semiconductor layer;
- providing a gate electrode overlying the gate dielectric;
- encapsulating the gate electrode and the gate dielectric with an encapsulant;
- selectively growing a semiconductor material overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer; and
- using the semiconductor material as a diffusion source by oxidizing the semiconductor material to control an amount of diffusion of the semiconductor material into a channel region of the semiconductor layer, wherein the diffusion of the semiconductor material into the channel region produces a strained channel.
2. The method of claim 1, wherein using the semiconductor material as a diffusion source modifies the semiconductor layer underlying the semiconductor material to become a stressor material layer.
3. The method of claim 2, wherein the stressor material layer comprises silicon germanium.
4. The method of claim 3, further wherein the oxidizing of the semiconductor material forms a dielectric which is removed and replaced by source/drain extensions on respective sides of the gate electrode.
5. The method of claim 1, wherein the semiconductor material includes at least one selected from the group consisting of a source of germanium, carbon doped silicon, boron, phosphorus and arsenic.
6. The method of claim 4, further comprising forming a conductive contact above each of the source/drain extensions and the gate electrode.
7. The method of claim 1, wherein oxidizing the semiconductor material further comprises performing an oxidation of the semiconductor material to produce effects of condensation as one component of the semiconductor material is preferentially consumed and diffused by formation of an oxide and diffused by a semiconductor material enrichment of the semiconductor layer; the method further comprising:
- selectively removing the oxide with respect to the encapsulant that encapsulates the gate electrode and the gate dielectric; and
- selectively growing a layer of another semiconductor material by selective epitaxy.
8. The method of claim 7, wherein the another semiconductor material includes one selected from the group consisting of a same initial semiconductor material and a different semiconductor material.
9. The method of claim 7, further comprising:
- selectively growing a layer of another semiconductor material and oxidizing the layer of another semiconductor material to achieve a desired amount of semiconductor material enrichment in the channel region of the semiconductor layer.
10. The method of claim 7, wherein selectively removing includes using a wet etch process.
11. The method of claim 7, wherein the semiconductor material includes SiGe, and Si is preferentially consumed and Ge is preferentially diffused and enriched by formation of the oxide SiO2; the method further comprising:
- selectively removing the oxide SiO2 with respect to the encapsulant that encapsulates the gate electrode and the gate dielectric; and
- selectively growing a layer of another semiconductor material by epitaxy.
12. The method of claim 1, further comprising:
- performing source/drain extension region implants and a dopant activation anneal;
- forming sidewall spacers adjacent the gate electrode;
- performing source/drain region implants to create a source/drain; and
- siliciding regions of the source/drain and the gate electrode.
13. The method of claim 1, wherein providing the semiconductor layer includes providing a semiconductor on insulator substrate.
14. The method of claim 13, wherein the semiconductor on insulator substrate includes a silicon on insulator substrate.
15. The method of claim 1, wherein encapsulating includes using an encapsulant for minimizing oxygen diffusion into the gate electrode and the gate dielectric.
16. The method of claim 1, wherein encapsulating the gate electrode includes using an encapsulant selected from the group consisting of nitride, oxide and a combination of nitride and oxide.
17. The method of claim 1, wherein the semiconductor material includes silicon germanium (SiGe) with a predetermined Ge concentration.
18. The method of claim 17, further wherein for a predetermined thickness of the semiconductor material, the predetermined Ge concentration is inversely proportional to the predetermined thickness, and a function of an oxidation time, in order to preserve a total amount of Ge to be diffused into the semiconductor layer.
19. The method of claim 17, further wherein the predetermined Ge concentration is greater than 15%.
20. The method of claim 1, wherein the semiconductor material diffuses vertically into the semiconductor layer and further diffuses laterally within the semiconductor layer to a source/channel interface and a drain/channel interface to form heterojunctions at respective interfaces of the channel region.
21. The method of claim 1, wherein the semiconductor device includes one selected from the group consisting of a lateral double gate device and a vertical double gate device.
22. The method of claim 1, wherein the semiconductor material comprises one selected for obtaining a desired threshold voltage for the semiconductor device.
23. A method for forming a transistor, comprising:
- providing a semiconductor layer;
- providing a gate dielectric overlying a first portion of the semiconductor layer;
- providing a gate electrode overlying the gate dielectric;
- encapsulating the gate electrode and the gate dielectric with a dielectric layer;
- selectively growing a semiconductor material overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer;
- oxidizing the semiconductor material in an oxygen ambient to form a stressor layer from the second portion of the semiconductor layer thereby forming a strained channel within the first portion of the semiconductor layer; and
- forming source and drain regions in the second portion of the semiconductor layer and the semiconductor material.
24. A method for forming a transistor, comprising:
- providing a semiconductor layer;
- providing a gate dielectric overlying a first portion of the semiconductor layer;
- providing a gate electrode of the transistor overlying the gate dielectric;
- encapsulating the gate electrode and the gate dielectric;
- selectively growing a semiconductor material containing germanium overlying a second portion of the semiconductor layer outside the first portion, wherein the semiconductor material comprises a material different from a material of the semiconductor layer;
- heating the semiconductor material to diffuse germanium into the second portion of the semiconductor layer thereby forming a strained channel underlying the gate dielectric; and
- forming source and drain regions of the transistor in the second portion of the semiconductor layer and the semiconductor material.
Type: Application
Filed: Sep 29, 2004
Publication Date: Mar 30, 2006
Inventors: Voon-Yew Thean (Austin, TX), Mariam Sadaka (Austin, TX), Ted White (Austin, TX), Alexander Barr (Crolles), Venkat Kolagunta (Austin, TX), Bich-Yen Nguyen (Austin, TX), Victor Vartanian (Dripping Springs, TX), Da Zhang (Austin, TX)
Application Number: 10/954,121
International Classification: H01L 21/336 (20060101);