System and method for concurrently checking availability of data in extending memories
This invention discloses an extended memory comprising a first tag RAM for storing one or more tags corresponding to data stored in a first storage module, and a second tag RAM for storing one or more tags corresponding to data stored in a second storage module, wherein the first and second storage modules are separated and independent memory units, the numbers of bits in the first and second tag RAMs differ, and an address is concurrently checked against both the first and second tag RAMs using a first predetermined bit field of the address for checking against a first tag from the first tag RAM and using a second predetermined bit field of the address for checking against a second tag from the second tag RAM.
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The present invention relates generally to computer memory architectures, and, more particularly, to a system and method for extending memories in stacked chips with multicore microprocessors.
A recent trend to pack more functions into a small form factor is a so-called system-in-package (SiP) technology which is to enclose a number of integrated circuit (IC) dies in a single package or module. The dies may be stacked vertically or placed horizontally alongside one another inside the package. They are internally connected by fine wires that are buried in the package, or joined by solder bumps through a flip-chip technology.
Referring to
These SiPs can greatly extend cache capacity in a computer system. But with added levels of caches, memory management becomes more complicated.
Cache memories work like temporary storages. When the processing unit 246 wishes to read or write to a location in the main memory 220, it first checks whether that memory location is in the Level 1 cache 242. This is accomplished by comparing the address of the memory location to all tags stored in the Level 1 cache 242 that might contain that address. If the processing unit 246 finds that the memory location is in the cache, then the data corresponding to the address will be accessed directly from the Level 1 cache 242, and a cache hit will have occurred. Otherwise the data is not in the Level 1 cache 242, and it is a cache miss.
SiP extends computer cache capacity; however, with the aforementioned hierarchical memory management approach, the Level 2 cache 230 can not be simultaneously checked with the Level 1 cache 242. The execution unit 246 can only check the Level 1 cache 242 directly. For Data to be accessed, they have to be transferred to the lower memories in the hierarchy. This lowers memory management efficiency.
As such, what is desired is a memory management system and method that can simultaneously check multiple memories either in the same or different levels, and hence directly accesses data stored in those memories.
SUMMARYThis invention discloses an extended memory comprising a first tag RAM for storing one or more tags corresponding to data stored in a first storage module, and a second tag RAM for storing one or more tags corresponding to data stored in a second storage module, wherein the first and second storage modules are separated and independent memory units, the numbers of bits in the first and second tag RAMs differ, and an address is concurrently checked against both the first and second tag RAMs using a first predetermined bit field of the address for checking against a first tag from the first tag RAM and using a second predetermined bit field of the address for checking against a second tag from the second tag RAM.
The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The drawings accompanying and forming part of this specification are included to depict certain aspects of the invention. A clearer conception of the invention, and of the components and operation of systems provided with the invention, will become more readily apparent by referring to the exemplary, and therefore non-limiting, embodiments illustrated in the drawings, wherein like reference numbers (if they occur in more than one view) designate the same elements. The invention may be better understood by reference to one or more of these drawings in combination with the description presented herein. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale.
The present invention discloses a memory management system and method that can simultaneously check multiple caches either in the same level or in different levels, and hence directly accesses data stored in the caches.
When the physical address 302 is checked against the cache 308, the 9 index bits 304 are used to select a tag line 322 in the tag RAM 310. First is to check the attribute bits 324 of the selected tag line by a block 330. The modified bit may indicate whether this line of data has been modified or not and determines any line update when it is swapped back to a hard disk. Any match result may be ignored if the invalidate bit is set. The block 330 may be implemented as a multi-bit comparator circuit. After all the attribute bits are checked, the output of the tag portion may be compared with the tag bits 303 of the physical address 302 also at the block 330. If the comparison produces a match, then a chunk of data the physical address 302 intends to address is stored in the cache 308 and can be fetched directly, i.e., a cache hit has occurred.
In fact, the cache 308 illustrated in
Because different bit fields of the physical address 402 are used by different caches 410 and 420, the same physical address can reach completely different line of tag RAMs with totally different tags, in such a way, the two caches 410 and 420 can be checked concurrently for data availability by the single physical address 402.
As both the first and second caches 410 and 420 are implemented in two-way set association, two pairs of hit signals, Hit0[1:2] and Hit1[1:2] may be produced between them, and are sent to a control logic circuit 430 which controls a multiplexer 440. If one of the signals Hit0[1] and Hit1[1] is hit, then the multiplexer 440 will output a chunk of line[1] data from the first cache 410. Similarly, if one of the signals Hit0[2] and Hit1[2] is hit, then the multiplexer 440 will output a chunk of line[2] data from the second cache 420.
Although only two-way set association is described here, one having skill in the art would recognize that any other way set association may work with the present invention.
Referring to
There should be internal/external cache placement algorithms to prevent both caches 410 and 420 from storing the same line. One embodiment is to use random replacement, namely, the physical address is randomized through LFSR (Linear Feedback Shift Register) algorithm to generate a bit. Select internal cache occurs when this bit is set or external if not set. Another embodiment is to use a portion of physical addresses to determine accessing internal or external caches. For example, according to the physical address, the lowest 8 KB in a page will be assigned to internal cache. Others will be assigned to external cache.
Since off-chip memories have longer inter-connects to a mother die, a stacked cache may be slower than an on-die cache. Therefore, the stacked cache may need longer latency than the on-die cache.
The controls of stacked caches remain better on die, while the stacked memory only provides additional data storage. The tag for the stacked memory may or may not be on die, though it makes more sense to remain on die due to the number of logic involved in cache operations. With this concurrent accessing method, there is more freedom in the way of building a SiP chip.
Referring to
Referring to
Although the present disclosure uses cache memories as an embodiment of the present invention, one having skill in the art would appreciate the present invention can be applied to memory systems where multiple modules exist and tags are used for keeping track of the data stored in the modules.
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
Claims
1. A memory system for a multi-core computer system, the memory system comprising:
- a first tag random access memory (RAM) for storing one or more tags corresponding to data stored in a first storage module; and
- a second tag RAM for storing one or more tags corresponding to data stored in a second storage module,
- wherein the first and second storage modules are separated and independent memory units, and
- wherein the numbers of bits in the first and second tag RAMs differ, and
- wherein a number is concurrently checked against both the first and second tag RAMs using a first predetermined bit field of the number for checking against a first tag from the first tag RAM and using a second predetermined bit field of the number for checking against a second tag from the second tag RAM.
2. The memory system of claim 1, wherein
- the first tag is addressed by a third predetermined bit field of the number; and
- the second tag is addressed by a fourth predetermined bit field of the number,
- wherein the numbers of bits in the third and fourth predetermined bit fields differ.
3. The memory system of claim 1, wherein the number is an address of a chunk of data intended to access.
4. The memory system of claim 1, wherein the first and second predetermined bit fields of the number have one or more overlapping bits.
5. The memory system of claim 1, wherein the first storage module is a stacked cache memory.
6. The memory system of claim 1, wherein both the first and second storage modules are stacked cache memories.
7. The memory system of claim 6, wherein the first and second storage modules are in different stacked dies.
8. The memory system of claim 1, wherein the first storage module is a Level 1 or Level 2 cache and the second storage module is a Level 3 cache.
9. The memory system of claim 1, wherein the first and second tag RAMs reside in the same memory die.
10. The memory system of claim 1, wherein the first or second tag RAMs further comprises one or more attribute bits for memory coherent operations.
11. A cache memory system for a multi-core computer system, the cache memory system comprising:
- a first tag random access memory (RAM) for storing one or more tags corresponding to data stored in a first cache memory; and
- a second tag RAM for storing one or more tags corresponding to data stored in a second cache memory,
- wherein the first and second cache memories are separated and are independent memory units, and
- wherein the numbers of bits in the first and second tag RAMs differ, and
- wherein a data address is concurrently checked against both the first and second tag RAMs using a first predetermined bit field of the data address for checking against a first tag from the first tag RAM and using a second predetermined bit field of the data address for checking against a second tag from the second tag RAM.
12. The memory system of claim 11, wherein
- the first tag is addressed by a third predetermined bit field of the data address; and
- the second tag is addressed by a fourth predetermined bit field of the data address,
- wherein the number of bits of the third and fourth predetermined bit fields differ.
13. The memory system of claim 11, wherein the first cache memory is a Level 1 cache and the second cache memory is either a Level 2 or Level 3 cache.
14. The memory system of claim 11, wherein the first and second tag RAMs reside in the same memory die.
15. The memory system of claim 11, wherein the first and second cache memories are in different stacked dies.
16. A method for concurrently checking availability of data in extended memories of a multi-core computer system, the method comprising:
- addressing a first tag line in a first tag random access memory (RAM) by a first predetermined bit field of a data address;
- addressing a second tag line in a second tag RAM by a second predetermined bit field of the data address;
- comparing a third predetermined bit field of the data address against the first tag line;
- comparing a fourth predetermined bit field of the data address against the second tag line;
- wherein a chunk of data in the data address is intended to address is stored in a first memory module and the first tag RAM associated to when the third predetermined bit field matches the first tag line and the chunk of data is stored in a second memory module when the fourth predetermined bit field matches the second tag line, and
- wherein the first and second memory modules are separated and are independent memory units.
17. The method of claim 16, wherein the numbers of bits in the third and fourth predetermined bit fields differ.
18. The method of claim 16, wherein the first and second tag RAMs reside in the same memory die.
19. The method of claim 16, wherein the first and second memory modules are in different stacked dies.
20. The method of claim 16 further comprising accessing one or more attribute bits in the first or second tag RAM for memory coherent operations.
Type: Application
Filed: Mar 15, 2007
Publication Date: Sep 18, 2008
Applicant:
Inventor: Shine Chung (Sanchong)
Application Number: 11/724,568
International Classification: G06F 12/00 (20060101);