SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.
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This application claims the priority benefit of Taiwan Patent Application Serial Number 097119025, filed on May 23, 2008, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to a package, and more particularly to a semiconductor package, wherein the mechanical robustness of a stiffener that can prevent a carrier (e.g. substrate) from warping during subsequent thermal processes. Also, the stiffener can be directly mounted on the carrier by the attaching force of an encapsulant. It is not necessary that the stiffener is attached on the carrier by an extra adhesive, thereby decreasing the processing step of the semiconductor package.
2. Description of the Related Art
Due to chips having high performance are required, a chip package having a thin type substrate is increasingly put in use. For example, the chip package having the thin type substrate is applied to a high-end memory, an application specific integrated circuit (ASIC) and a microprocessor having a high electrical performance demand, a high frequency demand and a high speed demand.
A typical chip package having a thin type substrate includes various conductive and insulating materials which have different coefficients of thermal expansions (CTE). For example, a chip is disposed on an upper surface of a substrate by a wire bonding process or a flip chip bonding process. An encapsulant is adapted to seal the chip and disposed on the upper surface of the substrate. A plurality of solder balls are disposed a low surface of the substrate so as form a conventional ball grid array (BGA) package. However, a thin type substrate has a problem of warping. Due to the different CTE's of various conductive and insulating materials used in the BGA package after the BGA package is packaged, the BGA package having the thin type substrate may be warped seriously during subsequent thermal processes (e.g. a reflow process). The warping of the BGA package may cause the substrate not to be co-plane so as to further have a problem of solder ball joints.
Referring to
Although the reference of U.S. Pat. No. 6,894,229 discloses that the stiffener 140 is adapted to be acted as a heat spreader and to increase the mechanical robustness of the substrate 120, the stiffener 140 needs to cover the whole area that the chip 110 is disposed on so as to affect the layout of other components (e.g. passive components). Furthermore, the height of the stiffener 140 (i.e. the heat spreader) must be higher than that of bonding wires 130 of the chip 110 so as to prevent the bonding wires 130 of the chip 110 from damage. In addition, the stiffener 140 must be attached on the substrate 120 by an adhesive 136.
Referring to
However, the height of the carrier ring 240 must be higher than that of the chip 210, whereby the predetermined encapsulation thickness of the chips 210 cannot be less than the height of the chips 210. In addition, the carrier ring 240 must be attached on the substrate 220 by an adhesive 236.
Accordingly, there exists a need for a semiconductor package capable of solving the above-mentioned problems.
SUMMARY OF THE INVENTIONIt is an object of the present invention to provide a semiconductor package, wherein the mechanical robustness of a stiffener that can prevent a carrier (e.g. substrate) from warping during subsequent thermal processes. Also, the stiffener can be directly mounted on the carrier by the attaching force of an encapsulant. It is not necessary that the stiffener is attached on the carrier by an extra adhesive, thereby decreasing the processing step of the semiconductor package.
In order to achieve the foregoing object, the present invention provides a semiconductor package including a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.
The stiffener includes metal or any other solid material which has an enough mechanically robustness. The height of the stiffener of the present invention can be smaller than that of the chip, and the enough mechanical robustness of the stiffener that can prevent the carrier (e.g. substrate) from warping during subsequent thermal processes. Compared with the prior art, the height of the stiffener of the present invention is smaller than that of the chip so as to cause the stiffener of the present invention to have smaller volume. Thus, the stiffener of the present invention is more economical, and is easily sawed. Furthermore, the stiffener can include a groove adjacent to the carrier. The groove can increase an attaching area (i.e. an attaching force) between the encapsulant and the stiffener so as to directly mount the stiffener on the carrier. In addition, the stiffener of the present invention can be directly mounted on the carrier by the attaching force of the encapsulant. It is not necessary that the stiffener of the present invention is attached on the carrier by an extra adhesive, thereby decreasing the processing step of the semiconductor package.
The foregoing, as well as additional objects, features and advantages of the invention will be more apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
Referring to
The stiffener 342 directly contacts the substrate 320, and is mounted on the substrate 320 by an attaching force of the encapsulant 360. The stiffener 342 is disposed around the chip 310, and the stiffener 342 includes a through opening 344, which is located around the chip 310. In other words, the chip 310 is located within the through opening 344. The stiffener 342 includes metal or any other solid material which has an enough mechanically robustness. The height of the stiffener 342 of the present invention can be smaller than that of the chip 310, and the enough mechanical robustness of the stiffener 342 can prevent the substrate 120 from warping during subsequent thermal processes. Preferably, the stiffener 342 can be made of a ceramic material.
Compared with the prior art, the height of the stiffener of the present invention is smaller than that of the chip so as to cause the stiffener of the present invention to have smaller volume. Thus, the stiffener of the present invention is more economical, and is easily sawed.
Referring to
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Compared with the prior art, the stiffener of the present invention can be directly mounted on the substrate by the attaching force of the encapsulant. It is not necessary that the stiffener of the present invention is attached on the substrate by an extra adhesive, thereby decreasing the processing step of the semiconductor package.
Referring to
Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Claims
1. A semiconductor package comprising:
- a carrier;
- a chip disposed on the carrier and electrically connected to the carrier;
- a stiffener disposed around the chip, directly contacting the carrier, and mounted on the carrier; and
- an encapsulant adapted to seal the chip and cover the stiffener.
2. The semiconductor package as claimed in claim 1, wherein the stiffener includes a surface contacting the carrier, and the surface has a groove.
3. The semiconductor package as claimed in claim 2, wherein the cross-section of the groove is triangular.
4. The semiconductor package as claimed in claim 2, wherein the cross-section of the groove is rectangular.
5. The semiconductor package as claimed in claim 1, wherein the stiffener comprises a through opening and the chip is located within the through opening.
6. The semiconductor package as claimed in claim 1, wherein the stiffener is made of a ceramic material.
7. The semiconductor package as claimed in claim 1, wherein the carrier comprises at least one first positioning hole, the stiffener comprises at least one second positioning hole, and the first positioning hole is corresponding to the second positioning hole.
8. The semiconductor package as claimed in claim 1, wherein the height of the stiffener is smaller than that of the chip.
9. A method for manufacturing semiconductor packages comprising the following steps of:
- providing a carrier, wherein the carrier includes at least one first positioning hole;
- disposing at least one chip on the carrier;
- disposing a stiffener on the carrier, wherein the stiffener directly contacting the carrier, the stiffener is disposed around the chip, and the stiffener comprises at least one second positioning hole corresponding to the first positioning hole;
- temporarily mounting the stiffener on the carrier by an alignment step; and
- sealing the chip and the stiffener and mounting the stiffener on the substrate by an encapsulation step so as to form at least one semiconductor package.
10. The method as claimed in claim 9, further comprising the following step of:
- sawing the encapsulant, the substrate and the stiffener, thereby singularizing the semiconductor package, wherein the semiconductor package still include the stiffener.
11. The method as claimed in claim 9, further comprising the following step of:
- sawing the encapsulant and the substrate, thereby singularizing the semiconductor package, wherein the semiconductor package does not include the stiffener.
12. The method as claimed in claim 9, wherein the alignment step comprises the following processes of: providing a tool for aligning the second positioning hole of the stiffener with the first positioning hole of the substrate, and temporarily mounting the stiffener on the substrate.
13. The method as claimed in claim 12, wherein the alignment step further comprises the following process of: removing the tool.
14. The method as claimed in claim 13, wherein the tool comprises an upper mold and a lower mold.
15. The method as claimed in claim 14, wherein the lower mold comprises a positioning pin for inserting the second positioning hole and the first positioning hole, thereby aligning the second positioning hole of the stiffener with the first positioning hole of the substrate.
16. The method as claimed in claim 14, wherein the upper mold is adapted to press the stiffener and the substrate, thereby temporarily mounting the stiffener on the substrate.
17. The method as claimed in claim 9, wherein the encapsulation step comprises the process of molding an encapsulant.
18. The method as claimed in claim 17, wherein the stiffener is mounted on the substrate by an attaching force of the encapsulant.
19. The method as claimed in claim 9, wherein the stiffener includes a surface contacting the carrier, and the surface has a groove.
20. The method as claimed in claim 9, wherein the height of the stiffener is smaller than that of the chip.
Type: Application
Filed: May 12, 2009
Publication Date: Nov 26, 2009
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC. (Kaohsiung)
Inventors: Chia Chien HU (Kaohsiung City), Chao Cheng Liu (Kaohsiung County), Chien Liu (Kaohsiung County), Chih Ming Chung (Tainan County)
Application Number: 12/464,315
International Classification: H01L 23/28 (20060101); H01L 21/56 (20060101);