Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.
The invention relates to the technology involved in the fabrication of insulating wafer structural elements each having an array of sub 100 micrometer size electrical pathways that are to serve as interface substrates between different types of wiring in electronic apparatus.BACKGROUND AND RELATION TO THE PRIOR ART
The fabrication of insulating wafers that can serve as carriers or substrates for electronic circuitry in which there are to be thousands of vias or through holes of micrometer dimensions that are completely filled with metal and have acceptable electrical impedance and electromigration performance is a subject of considerable importance in the electronic Industry. At the present state of electronic packaging there is generally a lower density of interconnection and wiring in most carriers and substrates than would be available with the integrated semiconductor chip technology. Intense study is taking place on the performance and design advantages of combining different circuitry types and organizations on a dense carrier or substrate with effort being directed to interface problems such as spacing mismatch and the difficulty of bringing signal and power lines in from peripheral supporting members. The technology is at times in the art referred to as System On Package (SOP) technology.
One example of effort in the field, is described in U.S. patent application Ser. No. 09/838,725 Filed Apr. 1, 2001 in which a structure is being contemplated where an interconnecting wafer supports multichip devices attached on one side, while on the opposite side of the wafer connections are made to other modules or boards with a different interconnection technology.
A discussion of the state of studies in the field appears in a 7 page technical article by J. Baliga, titled “Packaging Provides Viable Alternatives to SOC” in the publication “Semiconductor International” in July, 2000.
While much of the reported work is conducted on silicon about which much is known serving as the insulating wafer material, the parameters involved in the invention can readily be extended to other insulating materials; an example being work on the material glass which is reported in the 2001 IEEE Proceedings, pages 98-102 by Li et al titled “High Density Electrical Feedthroughs Fabricated by Deep Reactive Ion Etching of PYREX Glass”.
At the present state of the art however, many problems are being encountered as dimensions shrink into the sub 100 micrometer range, such as getting the dimensions of the via openings accurate and uniformly filled with metal yet being sufficiently structurally rigorous that the ability to use the Chemical Mechanical Polishing (CMP) type of processing which involves a combination of abrasion and chemical modifications, is preserved.SUMMARY OF THE INVENTION
The invention is the technology of providing a packaging intermediate product that serves as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, an array of spaced vias through the wafer is arranged with each via filled with metal surrounded by an adhesion layer for promotion of electroless metal deposition on the exposed insulating material in the vias, and with each via terminating flush with an area surface.
The wafer structure is achieved by a technological process in which there is the formation of an array of blind via openings of about 5-50 micrometer in diameter made through the first surface of the dielectric
wafer to a depth of about 50-250 micrometers which is approaching the via design length. There is then a conditioning of the walls of the via openings for providing adhesion of a metal delivered through a chemical reaction such as electroless plating. The blind via openings are completely filled with a metal. There is CMP type removal of all material at the first wafer surface, thereby planarizing the filled vias. There is then removal of material at the second wafer surface thereby thinning the wafer until exposing the blind side of the metal filled vias, which are at the design via length.
In accordance with the invention, a major solution to many of the problems encountered in electronic packaging involving different types of circuitry and technology as packaging interconnect dimensions shrink into the sub 100 micrometer range can be achieved through the construction of an interface substrate for interconnecting the different types of circuitry and technology.
The technology of the invention is illustrated in connection with
The principles of the invention are further illustrated in detail in two examples of the metal 17 filling process as illustrated in
The wafer is placed in a sputtering chamber. A layer of 400 Angstrom TaN/400 Angstrom Ta/800 Angstrom Cu is deposited all over the wafer surface 4, the mask 13 and onto the walls and bottom of the blind holes 15. The TaN/Ta is to serve as an adhesion layer 16. It has a special advantage for metallization of the sites inside cavities such as the blind holes 15 a thin layer of Copper (not shown) is deposited to a depth of about 0.6 to 0.8 micro meters followed by a simple mechanical polish or CMP to remove the copper on the surface but leave it in the walls and bottom of the blind holes 15.
The wafer is next immersed in a dilute acid solution to clean any oxides from the thin layer of Cu. Next the wafer is placed in a dilute solution of palladium sulfate, where the reaction of Eq. 1 occurs on the surface and bottom of the blind vias 15.
Pd(++)+Cu . . . Pd(o)+Cu(++) Eq. 1.
As result of this exchange reaction, the surface of the walls and bottom of the blind vias 15 are covered by nanoparticles of a Pd active catalyst illustrated as layer 16 in
Following the catalyst activation, the electroless plating takes place. The wafer is placed in a fast rate electroless Ni plating bath whereby nickel metal is deposited uniformily all along the blind via 15 cavity walls and bottom with good plating uniformity. The plating bath is made up of a Ni salt, a stabilizing or complexing agent, a p H buffer, a reducing agent, and a surfactant. The surfactant insures a low surface tension in the fluid which allows a quick removal of gas bubbles and other reaction products. The resulting plating is uniform without voids.Example B
Referring again to
The wafer is Silicon and is immersed in a polyfunctional cationic surfactant. As the Si and Si/SiO2 surfaces are generally covered with negative Silanol groups (Si—OH(−)), upon immersion in the cationic surfactant, positive charges are created in all the exposed Si surfaces, both on the surface and inside the via walls, by electrostatic attraction. At this point, a multitude of cationic groups (+) are considered to be present on the Si.
The wafer is immersed for about 5-8 minutes in a suspension of a Pd/Sn particulate colloid. The particles of this colloid are charged with a negative charge (−) resulting in a strong attraction and good adhesion strength which makes particles of Pd strongly adhere to all Si surfaces. The Pd colloid may be selectively removed from unwanted areas, by polishing the surface of the wafer, with a mild mechanical buffing of the surfaces leaving the only the Pd catalytic areas on the cavity walls and bottom.
The wafer is then immersed in an electroless plating bath of a lower deposition rate for about 5 minutes to initiate the plating reaction, then followed by immersion in an electroless plating that deposits at a faster rate.
What has been described is the procedural and structural principles of providing a wafer via interface to be positioned between and supporting different circuitry types in electrical apparatus.
1. An electrical apparatus wherein first and second different types of circuitry are interconnected into a functional electrical apparatus unit,
- the improvement comprising:
- an interface supporting substrate member of dielectric material having first and second essentially parallel planar surfaces, said first type of circuitry being positioned on said first planar surface of said substrate member, said second type of circuitry positioned on said second planar surface of said substrate member, said substrate further having a plurality of electrical pathways from said first planar surface to said second planar surface through said dielectric material, a plurality of electrical pathways through said dielectric material joining circuit locations in said first and second types of circuitry, and, said electrical pathways through said dielectric material being filled with chemically deposited metal.
2. The improvement of claim 1 wherein said dielectric material is silicon.
3. The improvement of claim 2 wherein said electrical pathways are surrounded with an adhesion promoting layer.
4. The improvement of claim 3 wherein said adhesion promoting layer is a reaction product of Pd and Cu.
5. The improvement of claim 3 wherein said adhesion promoting layer is selected from the group consisting of Ta, TaN, a Pd catalytic layer and combinations thereof.
6. The improvement of claim 1 where said chemically deposited metal is electroless plated metal.
7. The improvement of claim 6 wherein said electroless deposited metal is selected from the group consisting of Ni, Co, Cu, Au and combinations thereof.
8. The method of providing an interface supporting substrate with electrical pathways through said substrate for use between entities of different circuitry in electrical apparatus,
- comprising in combination the steps of:
- providing a wafer structure of dielectric material having first and second area surfaces separated by a distance of the material of said wafer,
- forming an array of via openings through said first area surface into said material of said wafer, said via openings ending blind at a depth less than said distance,
- providing a chemical metal deposition promoting adhesion coating on at least the walls of said blind via openings,
- filling said blind via openings with chemically deposited metal, removing all material from said first area surface thereby planarizing said via openings, and, removing said material of said wafer through said second area surface until said filled vias are exposed and said second surface is planarized.
9. The method of claim 8 where said distance is said electrical pathway design length.
10. The method of claim 9 where said material of said wafer is silicon.
11. The method of claim 10 wherein said chemical deposited metal is by electroless plating.
12. The method of claim 11 wherein said metal is selected from the group consisting of Ni, Co, Cu, and Au and combinations thereof.
13. The method of claim 12 where said chemical metal deposition providing coating is a catalyst.
14. In the fabrication of electrical apparatus where there are different circuitry entities the packaging method comprising the steps of:
- providing for positioning one circuitry entity on one surface of a supporting member of dielectric material and positioning different one of said entities on the remaining surface of said supporting member, providing said supporting member with a plurality of electrical pathways in an array arrangement between locations in said surfaces through said dielectric material, said plurality of electrical pathways through said dielectric material joining circuit locations in said circuitry entities, and, said electrical pathways through said dielectric material being filled with chemically deposited metal.
15. The packaging method of claim 14 here said metal is Ni.
16. The packaging method of claim 17 wherein said chemical depositing of metal step involves the use of a catalyst.
Filed: Aug 11, 2009
Publication Date: Dec 10, 2009
Inventors: Yu- Ting Cheng (Elmsford, NY), Sherif A. Goma (Hawthorne, NY), John Harold Magerlein (Yorktown Heights, NY), Sampath Purushothaman (Yorktown Heights, NY), Carlos Juan Sambucetti (Croton on Hudson, NY), George Frederick Walker (New York, NY)
Application Number: 12/462,980
International Classification: H01L 23/48 (20060101); H01L 21/768 (20060101);