SEMICONDUCTOR DEVICE
A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.
The present application claims priority from Japanese Patent Application No. 2016-211435 filed on Oct. 28, 2016, the content of which is hereby incorporated by reference into this application.
TECHNICAL FIELD OF THE INVENTIONThe present invention relates to a semiconductor device. For example, the present invention relates to a semiconductor device in which a part of a lead connected with a wire is sealed with a resin sealer.
BACKGROUND OF THE INVENTIONJapanese Patent Application Laid-open Publication No. 2014-27293 (Patent Document 1) describes a power semiconductor device in which a plurality of wires are connected to one source electrode pad of a semiconductor chip and also describes a semiconductor device in which wires are connected to a plurality of source electrode pads of a semiconductor chip, respectively.
Japanese Patent Application Laid-open Publication No. 2013-102233 (Patent Document 2) describes a method of bonding one aluminum ribbon to a plurality of pads and lead posts of a semiconductor chip by using a wedge tool serving as a bonding tool.
SUMMARY OF THE INVENTIONThe inventors of the present invention have studied techniques for improving a performance of a semiconductor device. For example, a technique of bonding one wire to a plurality of positions of one electrode pad of a semiconductor chip is cited. An electrode formation surface of the semiconductor chip is covered with an insulating film serving as a protective film. When the wire is bonded to the plurality of positions of the electrode pad, the wire is easy to be bonded by increasing an opening area of an opening formed on the protective film. However, it has been found out that a resin (resin sealer) that seals the wire is separated from a part of the electrode pad, the part being not connected with the wire and being exposed from the protective film, because of the weakness at the bonded interface between a metal material making up the electrode pad and the resin material sealing the wire. Even if the electrode pad and the resin sealer are separated from each other, the function of the semiconductor device is not immediately damaged. However, in consideration of long-term product quality such as the service life of the semiconductor device or others, it is preferable to suppress the separation between the resin sealer and the electrode pad.
Other object and novel characteristics will be apparent from the description of the present specification and the accompanying drawings.
A semiconductor device according to one embodiment includes a first conductive member bonded to a first bonding surface at a plurality of positions in a first opening formed on an insulating film of a semiconductor chip. The semiconductor device also includes a sealer that seals the semiconductor chip and the first conductive member so as to be in contact with the first bonding surface. An area of a part of the first bonding surface, the part not overlapping the first conductive member, is small.
According to the above-described one embodiment, the performance of the semiconductor device can be improved.
(Explanation of Description Form, Basic Term and Method in Present Application)
In the present application, the invention will be described in a plurality of sections or others when required as a matter of convenience. However, these sections or others are not irrelevant to each other unless otherwise particularly stated, and the one of each part of a simple example relates to a detailed part, a part, or the entire of the other as a modification example or others, regardless of before and after the description. Also, in principle, the repetitive description of the same part is omitted. Further, each element in the embodiment is not indispensable unless otherwise particularly stated not to be so, logically limited to the number, and clearly not to be so from the contexts.
Similarly, when “X made of A” or others is described for materials, compositions, and others in the description of the embodiment and others, the one containing other components than A is not eliminated unless otherwise stated not to be only the component and clearly not to be so from the contexts. For example, the component means “X containing A as a main component” or others. For example, it is needless to say that a “silicon material” and others includes not only pure silicon but also SiGe (silicon germanium) or other multicomponent alloy containing silicon as a main component, or a member containing other additives or others. Also, gold plating, a Cu layer, nickel plating, and others include not only pure material but also members containing gold, Cu, nickel, and others as a main component, respectively, unless otherwise specified not to be so.
Further, even when a specific numerical value and numerical amount are mentioned, they may exceed the specific numerical values or smaller than the specific numerical values unless otherwise specified not to be so, logically limited to the number, and clearly described to be so from the contents.
Still further, in each drawing of the embodiment, the same or similar parts are denoted by the same or similar symbol or reference number, and the description thereof is not repeated.
Also, in the attached drawings, hatching or others is omitted in some cases even in a cross-sectional view in a conversely complicated case or in a case in which a space is clearly distinguished therefrom. In respect to this, in a case in which it is clear from the description or others, an outline of the background is omitted even in a hole which is closed in a plan view in some cases. Further, hatching or a dot pattern is added to a drawing even if the drawing is not a cross-sectional view in order to explicitly illustrate so as not to be the space or explicitly illustrate a boundary between regions.
In the following description, terms “contact”, “adhesion”, “bonding”, “separation”, and “connection” are used in the following meanings. The term “contact” represents a state in which two separable members are in contact with each other in at least a part of them. The term “adhesion” represents a state in which two separable members (bonded materials) are coupled and fixed to each other via an adhesive in at least apart of them. The term “bonding” represents a state in which two separable members (bonded materials) are coupled and fixed to each other in at least a part of them. The above-described term “coupling” includes mechanical coupling such as an anchoring effect, coupling caused by a physical interaction such as intermolecular force, and coupling caused by a chemical interaction such as covalent bonding. The term “bonding” includes not only a case in which a different material (e.g., adhesive) is interposed between the bonded materials but also a case in which no different material is interposed therebetween. That is, a “bonded state” includes an “adhered state”. The term “separation” represents a state in which the above-described “bonded state” is released and changed into a separable state. A simply-termed “separation” includes not only a case in which the coupling is released in the entire bonded part between two members but also a case in which the coupling is released in a part of the bonded part. The term “connection” represents a state in which two members communicate with each other (in which a connection path is not interrupted in its middle and is continuously linked). It is irrelevant whether a different member is interposed between two members or not. For example, “state in which a member A and a member B are electrically connected” represents an electrical conductible state between the member A and the member B, and also includes a case in which a member C is interposed between the member A and the member B. A simple term “state in which the member A and the member B are connected” represents a state in which the member A and the member B are fixed to each other, and also includes a case in which the member C is interposed between the member A and the member B. For example, “state in which the member A and the member B are connected” also includes a case in which the member A and the member B are formed integrally into an inseparable single object and yet are distinguished from each other in terms of shape and function. Such a state in which the member A and member B are formed into the single object is termed as “joint” in some cases.
In the following description, when solder, solder member, solder material, or solder component is mentioned, the term represents, for example, Sn-Pb solder containing lead (Pb) or so-called lead-free solder substantially containing no lead. As examples of the lead-free solder, for example, only tin (Sn), tin and bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu) and others are cited. Here, the lead-free solder represents the one having lead (Pb) content of 0.1 wt % or less. This content is defined as standards of the RoHS (Restriction of Hazardous Substances) directive.
In the present embodiment, as an example of a semiconductor device, a power device embedded into a power control circuit of a power circuitry, etc., or a semiconductor device referred to as power semiconductor device will be exemplified and described. A semiconductor device described below is embedded into a power conversion circuit, and functions as a switching element.
<Example of Circuit Configuration>
Some semiconductor devices for power control, each of which is referred to as power semiconductor device, include semiconductor elements such as diodes, thyristors, and transistors. A transistor is used in various fields. As described in the present embodiment, a transistor embedded into a power control circuit through which a large current of, for example, 1 A (ampere) or larger flows to function as a switching element is called power transistor. A semiconductor device PKG1 of the present embodiment includes a semiconductor chip 10 having a transistor Q1 serving as a power transistor as shown in
The above-described MOSFET is used as a term that widely represents a field-effect transistor having a structure in which a gate electrode made of a conductive material is disposed on a gate insulating film. Therefore, even when the MOSFET is mentioned, a gate insulating film other than an oxide film is not excluded. Also, even when the MOSFET is mentioned, a gate electrode material such as polysilicon other than metal is not excluded.
The transistor Q1 shown in
In the example shown in
On the epitaxial layer EP, a channel formation region CH, which is a p+-type semiconductor region, is formed. On this channel formation region CH, a source region SR (which corresponds to a source “S” illustrated in
On the inner wall of the trench TR1, a gate insulating film GI is formed. On the gate insulating film GI, a stacked gate electrode G is formed so that the trench TR1 is embedded. The gate electrode G is electrically connected to the gate electrode pad (electrode, gate electrode) GE of the semiconductor chip 10 via a leading-out wiring.
In the transistor Q1, the drain region and the source region SR are arranged across the channel formation region CH in the thickness direction, and therefore, a channel is formed in the thickness direction (which will hereinafter be referred to as “vertical channel structure”). In this case, an occupation area of the element in a plan view can be smaller than that of a field-effect transistor having a channel formed along the main surface WHt. Therefore, a plane size of the semiconductor chip 10 can be reduced.
In the case of the above-described vertical channel structure, a channel width per unit area in a plan view can be increased, and therefore, an on-resistance can be reduced. Note that
When the MOSFET is made up so that the plurality of the transistors Q1 having the vertical channel structure are connected in parallel as described above, the electrical characteristics (mainly, breakdown characteristics, on-resistance characteristics, capacity characteristics) of the MOSFET changes in accordance with the plane size of the semiconductor chip 10. For example, by the increase in the plane area of the semiconductor chip 10, the number of cells of the transistors Q1 connected in parallel is increased, and therefore, the on-resistance decreases, and the capacity increases.
In
<Semiconductor Device>
Next, the package structure of the semiconductor device PKG1 shown in
The semiconductor device PKG1 of the present embodiment includes the semiconductor chip 10 (see
According to the present embodiment, in a plan view, the plurality of leads 30 are arranged side by side with the die pad 20 in the Y direction and are arranged side by side with each other in the X direction intersecting (to be orthogonal to in
As shown in
As shown in
As shown in
The semiconductor device PKG1 includes the die pad (metal plate, chip mounting portion, heat sink) 20 on which the semiconductor chip 10 is mounted. As shown in
As shown in
In the present embodiment, note that the lower surface 20b of the die pad 20 is exposed from the sealer 40. Therefore, the die pad 20 itself may be handled as the drain terminal. In the present embodiment, the explanation has been made while exemplifying the aspect of usage of the MOSFET as the power transistor, and therefore, the lead 30 and the die pad 20 operate as the drain terminal of the semiconductor device PKG1 in the term of a circuit. However, when an IGBT is used as the power transistor as a modification example, a collector electrode is formed on the back surface of the semiconductor chip. Therefore, when the power transistor is the IGBT, the lead 30 and the die pad 20 operate as the collector terminal of the semiconductor device PKG1 in terms of a circuit.
As shown in
As shown in
Since the lower surface 20b of the die pad 20 which is connected to the lead 30D serving as the external terminal is exposed from the sealer 40, the cross-sectional area of the conductive path through which the current flows is increased. Therefore, an impedance component of the conductive path can be reduced. Particularly when the lead 30D serves as an external terminal for supporting an output node of a circuit included in the semiconductor device PKG1, the reduction in the impedance component of the conductive path connected to the lead 30D is preferable in that power loss of an output wiring can be directly reduced.
The die pad 20 has a base material 21 made of the same metal material as a metal material making up the leads 30, such as copper (Cu) or an alloy material mainly containing copper (Cu) as a main component. Each of the plurality of leads 30 has a base material 31 made of the same metal material as a metal material making up the die pad 20, such as copper (Cu) or an alloy material mainly containing copper (Cu) as a main component.
The part (outer portion, exposed portion) of the die pad 20 that is exposed from the sealer 40 is covered with the metal film 22. Similarly, the part (outer portion 30X) of lead 30 that is exposed from the sealer 40 is covered with a metal film 32. These metal films 22 and 32 are metal films that are for improving the wetness of the solder material used as a connection material in the mounting of the semiconductor device PKG1 on amounting substrate. The metal films 22 and 32 are, for example, plating metal films formed by an electroplating method. Although described in detail later, each of the metal films 22 and 32 is made of, for example, a solder material containing tin (Sn).
The die bond material (bonding material) 11 shown in
As shown in
As shown in
As shown in
In the power semiconductor device, through a wiring path connected to the source electrode pad SE, a current flows to be larger than a current flowing through a wiring path connected to the gate electrode pad GE. For this reason, in the example shown in
The semiconductor chip 10, the plurality of leads 30, and the plurality of wires 12 are sealed with the sealer 40. The sealer 40 is a resin material that seals the semiconductor chip 10 and the plurality of wires 12. Specifically, the sealer 40 is the resin material that seals the semiconductor chip 10 and the plurality of wires 12 so as to be in contact with a bonding surface SEt1 and with a bonding surface SEt2 that are exposed surfaces of the source electrode pad SE as shown in
<Details of Connected Parts between Wires and Electrode Pads>
Here, the details of a part at which the electrode pad of the semiconductor chip is connected to the wire will be described.
As shown in
A plurality of openings are formed in the insulating film 13. In an example shown in
A wire (source wire) 12S1 is bonded to the bonding surface SEt1, while a wire (source wire) 12S2 is bonded to the bonding surface SEt2. A wire (gate wire) 12G is bonded to the bonding surface GEt. Specifically, the wire 12S1 has a connecting portion (bonding portion, stitch portion) 12B1 bonded to the bonding surface SEt1, a connecting portion (bonding portion, stitch portion) 12B2 bonded to the bonding surface SEt1, and a loop portion 12L1 located between the connecting portion 12B1 and the connecting portion 12B2 in the Y direction in a plan view. Each of the connecting portions 12B1 and 12B2 is a part of the wire 12, the part being thermally compression-bonded to the electrode pad of the semiconductor chip 10, and each lower surface of the connecting portions 12B1 and 12B2 is bonded to the same (common) bonding surface SEt1. The loop portion 12L1 is a portion that couples the connecting portions 12B1 to the connecting portions 12B2, and is separated from the bonding surface SEt1 (see
Although the wire 12S2 is not denoted with a reference character in
In other words, each of the wire 12S1 and the wire 12S2, which are connected to the source electrode pad SE, is bonded to one bonding surface SEt1 (or bonding surface SEt2) at a plurality of parts. In this case, a (total) bonding area between the wire 12S1, the wire 12S2 and the bonding surface SEt1, the bonding surface SEt2 becomes large, and therefore, an impedance of a supply path for a potential supplied through the wires 12S1 and 12S2 can be reduced.
The wire 12G connected to the gate electrode pad GE is different in a structure from the wires 12S1 and 12S2. That is, the wire 12G is bonded to one bonding surface GEt at one part. Specifically, the wire 12G has a connecting portion (bonding portion, stitch portion) 12B2 bonded to the bonding surface GEt, a connecting portion (bonding portion, stitch portion) 12B3 (see
Incidentally, as shown in
However, according to the studies of the inventors of the present application, it has been found that separation of the sealer 40 from the source electrode pad SE occurs at the bonding interface therebetween because of the low bonding strength between the sealer 40 (see
Even if the sealer 40 separates from the source electrode pad SE, the function of the semiconductor device PKG1 (see
As described above, the separation at the bonding interface between the insulating film 13 and the sealer 40 is more difficult to occur than the separation at the bonding interface between the source electrode pad SE that is the metal film and the sealer 40. For example, when the insulating film 13 is made of polyimide which is an organic-based material, an adhesive property with the sealer 40 is high, so that the bonding strength can be improved. Also when the insulating film 13 is made of an inorganic insulating film made of silicon oxide, silicon nitride, etc., as a modification example, the adhesive property with the sealer 40 can be higher than that in a case of a metal film. When the insulating film 13 is an inorganic insulating film made of silicon oxide, silicon nitride, etc., a difference in the linear expansion coefficient from the sealer 40 can be reduced, and therefore, the above-described separation is difficult to occur.
In the above-described manner, it is preferable to reduce an area of apart of the source electrode pad SE, the part being exposed from the insulating film 13, from the viewpoint of suppressing the separation between the sealer 40 and the source electrode pad SE. As shown in
In other words, in a plan view, each of the openings 13H1 and 13H2 of the insulating film 13 has the side HS3 extending in the X direction, the side HS4 extending in the X direction and opposite to the side HS3, the side HS1 extending in the Y direction intersecting the X direction, and the side HS2 extending in the Y direction and opposite to the side HS1. In a plan view, the side HS2 of the opening 13H1 and the side HS1 of the opening 13H2 are arranged adjacent to each other across the region 13R1 of the insulating film 13.
The configuration of the periphery of each of the bonding surface SEt1 and bonding surface SEt2 shown in
In the present embodiment, the distance between the bonding surface SEt1 and the bonding surface SEt2 (in other words, the distance between the opening 13H1 and the opening 13H2) is large. For example, in the example shown in
In the present embodiment, the loop portion 12L1 of each of the wires 12S1 and 12S2 extends in the Y direction orthogonally intersecting the X direction. Therefore, the width (thickness) WW2 of the loop portion 12L1 in the X direction is almost equal to the diameter of each of the wires 12S1 and 12S2, and the width (thickness) WW2 is 400 μm in the present embodiment. That is, in the X direction, the width (thickness) P1 of the region 13R1 is larger than the width (thickness) WW2 of the loop portion 12L1 of the wire 12S1.
The width (thickness) WW2 of the loop portion 12L1 of each of the wires 12S1 and 12S2 can be defined as follows. That is, in a plan view, each of the loop portion 12L1 of the wire 12S1 and the loop portion 12L1 of the wire 12S2 has a side LS1 extending from the connecting portion 12B1 to the connecting portion 12B2 in the Y direction and a side LS2 opposite to the side LS1. The width (thickness) WW2 of the loop portion 12L1 is defined as a width (length) of a part sandwiched between the side LS1 and the side LS2 in the X direction.
In this manner, by the large width P1 of the region 13R1 sandwiched between the bonding surface SEt1 and the bonding surface SEt2, a width of an exposed part of the bonding surface SEt1 in the X direction, in other words, an opening width of the opening 13H1, can be reduced. For example, in the example shown in
In the present embodiment, in the X direction, the maximum width of the region of the bonding surface SEt1, the region being sandwiched between the wire 12S1 and the side HS2 of the bonding surface SEt1, is smaller than the width P1 of the region 13R1 of the insulating film 13. Note that the above-described maximum width means the maximum of a plurality of widths, if any, in the region sandwiched between the wire 12S1 and the side HS2 of the bonding surface SEt1. For example, in the example shown in
In the example shown in
In the present embodiment, in the X direction, the total of the maximum width (width WR1) of the region of the bonding surface SEt1, the region being sandwiched between the wire 12S1 and the side HS2 of the bonding surface SEt1, and the maximum width (width WR3) of the region of the same, the region being sandwiched between the wire 12S1 and the side HS1 of the bonding surface SEt1, is smaller than the width P1 of the region 13R1 of the insulating film 13. According to the present embodiment, since the values of the widths WR1 and WR3 are small, the separation between the sealer 40 (see
In the present embodiment, the structure of the bonding between the bonding surface SEt2 and the wire 12S2 shown in
When the structure of the bonding between the bonding surface SEt2 and wire 12S2 is the same as the structure of the bonding between the bonding surface SEt1 and wire 12S1, the following can be described. That is, in the X direction, in the region sandwiched between the wire 12S1 and the wire 12S2, the total of the maximum width (width WR1) of the region sandwiched between the wire 12S1 and the side HS2 of the bonding surface SEt1 and the maximum width (width WR5) of the region sandwiched between the wire 12S2 and the side HS1 of the bonding surface SEt2 is smaller than the width P1 of the region 13R1 of the insulating film 13.
Each value of the widths WR1, WR2, WR3, and WR4 shown in
As described above, according to the present embodiment, in the X direction that is the short-side direction of the rectangular-shaped bonding surfaces SEt1 and SEt2, the width of the part of the bonding surfaces SEt1 and SEt2, the part not overlapping the wires 12, is made small. In this manner, the area of the part from which the sealer 40 of
As seen in the case of the present embodiment, when the width P1 of the region 13R1 is made small while the opening area of the opening 13H1 and the opening area of the opening 13H2 are smaller than the wire diameters (diameters) of the wires 12S1 and 12S2, the distance between the wire 12S1 and the wire 12S2 adjacent to each other is short. If more wires 12 can be bonded to the source electrode pad SE by the short distance between the adjacent wires 12S1 and wire 12S2, a cross-sectional area of the conductive path becomes large, and therefore, this manner is preferable from the viewpoint of the impedance reduction. However, if the distance between the adjacent wires 12S1 and wire 12S2 is extremely short, there is a possibility of causing a bonding tool (e.g., wedge tool WT shown in
In the present embodiment, each value of the width WR2 of the region sandwiched between the connecting portion 12B1 of the wire 12S1 and the side HS2 of the bonding surface SEt1 and the width WR6 of the region sandwiched between the connecting portion 12B1 of the wire 12S2 and the side HS1 of the bonding surface SEt2 shown in
Regarding the small exposed area of each of the bonding surfaces SEt1 and SEt2 in the present embodiment, the area of the region 13R1 is defined as follows as shown in
As shown in
In this manner, in order to bond the thick wires 12S1 and 12S2 to the source electrode pad SE, the areas of the bonding surfaces SEt1 and SEt2 become large. However, in the present embodiment, the area of each region of the bonding surfaces SEt1 and SEt2, the region tending to cause the separation, that is, the area of the part of the bonding surfaces SEt1 and SEt2, the part not overlapping the wires 12S1 and 12S2, is reduced, the separation between the sealer 40 (see
A structure shown in a study example shown in
However, the example shown in
Since the size of the source electrode pad SE in the example shown in
The short length LE2 of the source electrode pad SE in the Y direction is preferable in the following points. That is, a stress caused by a difference in the linear expansion coefficient between the source electrode pad SE and the sealer 40 becomes large in proportion to the length of the source electrode pad SE. Therefore, as shown in
The sealer 40 shown in
<Method of Manufacturing Semiconductor Device>
Next, a method of manufacturing the semiconductor device PKG1 having been described with reference to
<Semiconductor Chip Preparation Step>
At a semiconductor chip preparation step shown in
The semiconductor chip 10 prepared at this step includes the front surface 10t on which the insulating film 13 and the source electrode pad (electrode) SE, a part of which is exposed from the insulating film, are formed. The source electrode pad SE has the bonding surface SEt1 that is exposed from the insulating film 13 at the opening 13H1 formed on the insulating film 13, and the bonding surface SEt2 that is exposed from the insulating film 13 at the opening 13H2 formed on the insulating film 13. On the front surface 10t of the semiconductor chip 10, the gate electrode pad (electrode) GE is also formed. The gate electrode pad GE has the bonding surface GEt that is exposed from the insulating film 13 at the opening 13H3 formed on the insulating film 13. The semiconductor chip 10 includes also the back surface 10b opposite to the front surface 10t, as shown in
As shown in
The semiconductor chip 10 of
<Lead Frame Preparation Step>
At a lead frame preparation step shown in
As shown in
The lead frame LF is made of a metal material containing, for example, copper (Cu) as a main component, and has a thickness of, for example, about 125 μm to 400 μm. Each of the device formation portions LFd is connected to the frame portion LFf. The frame portion LFf is a support portion that supports each member formed in the device formation portion LFd until start of a lead separation step shown in
As shown in
Each of the plurality of leads 30 is coupled to the frame portion LFf, and is supported by the frame portion LFf. The plurality of leads 30 extend in the Y direction, and are arranged side by side so as to be adjacent to each other in the X direction. The plurality of leads 30 are coupled to each other via a tie bar LFt.
The plurality of leads 30 include the plurality of leads 30S that are the source leads. The plurality of leads 30S are arranged side by side in the X direction so as to be adjacent to each other, and are coupled to the wire bonding portion (lead post, pad, bonding pad, wire connecting portion, bonding portion) 30W. The plurality of leads 30 include also the lead 30G that is the gate lead. The wire bonding portion 30W is provided to a tip of the lead 30G, the tip being closer to the die pad 20. The plurality of leads 30 include also the lead 30D that is the drain lead. The lead 30D is located between the lead 30G and the leads 30S in the X direction, and has a tip closer to the die pad 20 in the Y direction, the tip being coupled to the die pad 20.
According to the present embodiment, the upper surface 20t of the die pad 20 is located at a height different from a height of the upper surface 30t of the wire bonding portion 30W of the lead 30. The lead 30D supporting the die pad 20 and a portion connecting the die pad 20 to the frame portion LFf are bent to offset the die pad 20. According to the present embodiment, the die pad 20 is offset downward from other members of the lead frame LF. As a result, as shown in
<Semiconductor Chip Mounting Step>
Next, at a semiconductor chip mounting step shown in
At the present step, the semiconductor chip 10 is mounted via the die bond material 11 on (adhesively fixed to) the upper surface 20t of the die pad 20 formed integrally with the lead 30D serving as the drain terminal. The semiconductor chip 10 is adhesively fixed to the upper surface 20t via the die bond material 11 so that the back surface 10b (see
At the present step, after the die bond material 11 is applied to the upper surface 20t of the die pad 20, the semiconductor chip 10 is mounted on the die bond material 11. The die bond material is cured, so that the semiconductor chip 10 and die pad 20 are fixed to each other.
As the die bond material 11, for example, a solder material may be used. Alternatively, as the die bond material 11, a conductive resin adhesive that is a so-called silver (Ag) paste containing a plurality of silver (Ag) particles (Ag filler) may be used. When the die bond material 11 is the solder material, a reflow process is performed as a method of curing the die bond material. When the die bond material 11 is the conductive resin adhesive, a thermosetting resin component contained in the die bond material 11 is heated to be cured.
<Wire Bonding Step>
Next, at a wire bonding step shown in
As shown in
Various modification examples are applicable to a method of connecting the wire 12. Meanwhile, according to the present embodiment, a wire 12 made of aluminum is bonded while using a bonding tool shown in
The wire bonding step has the first bonding step shown in
In the wedge bonding method, as shown in
Incidentally, a cross-sectional shape of the connecting portion 12B1 is determined by the distance between the tip surface WThb of the body WTh and the source electrode pad SE. For example, when the width WH1 of the bonding surface SEt1 (or width WH2 of the bonding surface SEt2) is larger than the width WWT of the tip surface WThb in the X direction in
However, according to the present embodiment, as described above with reference to
Note that the tip surface (tip portion) WThb of the wedge tool WT is a surface that is at least partially in contact with the wire 12 and faces the front surface 10t of the insulating film 13 at the wire bonding step, and does not include a surface WThs (see
In the present embodiment, the width WWT of the tip surface WThb in the X direction is about 600 μm to 800 μm. Therefore, in the X direction, the width P1 of the region 13R1 of
Next, the wire bonding step has a first loop formation step shown in
Next, the wire bonding step has the second bonding step shown in
Next, the wire bonding step has a second loop formation step shown in
The loop portion 12L2 extends from the semiconductor chip 10 to the leads 30. As a result, after the second loop formation step, the loop portion 12L2 intersects any one of the plurality of sides of the opening 13H1 (or opening 13H2) in a plan view, as shown in
Next, the wire bonding step has the third bonding step shown in
Next, the wire bonding step has a wire cutting step shown in
In
<Sealing Step>
Next, at a sealing step shown in
At the present step, the sealer 40 is formed by, for example, a so-called transfer mold method using a molding die 62 having a top mold (first mold) 62T and a bottom mold (second mold) 62B as shown in
In the example shown in
At this time, as shown in
As shown in
As described above, when the contact area between the sealer 40 and the bonding surface SEt1 or SEt2 made of a meal material is large, the separation may occur at the bonding interface between the sealer 40 and the bonding surface SEt1 or SEt2 after the present step. However, as described above, the present embodiment can reduce the area of the part of the bonding interface between the sealer 40 and the bonding surface SEt1 or SEt2, the part where the separation tends to occur, and therefore, the separation can be suppressed.
After the formation of the sealer 40, the sealer 40 is heated until part of the thermosetting resin contained in the sealer 40 cures (this step causes a so-called temporary curing state). When the lead frame LF can be removed from the molding die 62 by this temporary curing, the lead frame LF is removed from the molding die 62. The lead frame LF is transferred to a heating furnace, and is further subjected to a heat treatment (cure baking). In this manner, the rest of the thermosetting resin cures, so that the sealer 40 of
The sealer 40 is made of the insulating resin as a main component. The functions of the sealer 40 (e.g., resistance to warping distortion) can be improved by, for example, mixing filler particles such as silica (silicon dioxide: SiO2) particles into the thermosetting resin.
<Plating Step>
Next, at a plating step shown in
At the present step, by an electroplating method, the metal films 22 and 32 (
Although illustration is omitted in
The metal films 22 and 32 of the present embodiment are made of so-called lead-free solder such as tin (Sn) only, tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag) that does not substantially contain the lead (Pb) as described above. For this reason, the plating solution used at the present plating step is the electroplating solution containing metal salt such as Sn2+ and Bi3+. Note that the following explanation will be made about Sn-Bi alloy metal as an example of the lead-free solder plating. However, the electroplating solution can be replaced with electroplating solution obtained by replacing bismuth (Bi) with copper (Cu) and/or silver (Ag), or obtained by adding not only bismuth (Bi) but also copper (Cu) and/or silver (Ag).
In the present embodiment, the plating step is performed while the die pad 20 shown in
<Individualization Step>
Next, at an individualization step shown in
At the present step, the frame portion LFf coupled to the plurality of die pads 20 is cut so that the die pads 20 that are coupled to each other by the flame portion LFf are divided from each other. At the present step, the tie bar LFt is cut, and the boundaries between the plurality of leads 30 and the frame portion LFf are cut, so that the plurality of leads 30 are divided from each other.
As a method of cutting the tie bar LFt, the frame portion LFf, and the leads 30, a machining method (press working) for shearing by pressing a cutting jig to a part to be cut can be used. Since the present step is performed after the plating step, a side surface newly created by the shearing at the present step is exposed from the plating films (the metal films 22 and 33 of
After the present step, necessary inspections and tests such as an appearance inspection and an electrical test are performed, and a part having passed the tests becomes the semiconductor device PKG1 shown in
In the foregoing, the invention made by the present inventors has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention. A typical modification example will be described below.
First Modification ExampleAs shown in
However, in consideration of downsizing of the plane area of the semiconductor chip 10 and improvement in the arrangement density of the wires 12, it is preferable to reduce the width P1 of the region 13R1 as small as the contact at the wire bonding does not occur.
A semiconductor chip 10B shown in
The wire 12S3 has the same structure as that of each of the wires 12S1 and 12S2. For example, as similar to the wire 12S1, the wire 12S3 has the connecting portions 12B1 and 12B2 and the loop portions 12L1 and 12L2. Although not shown in the drawing, the wire 12S3 has the connecting portion 12B3 that is bonded to the upper surface 30t of the wire bonding portion 30W of the lead 30S shown in
The insulating film 13 has a region 13R2 located between the bonding surface SEt2 and the bonding surface SEt5 in a plan view. In the X direction in the example shown in
In the case of the semiconductor chip 10B, each of the three wires 12S1, 12S2, and 12S3 arrange side by side in the X direction is connected to the source electrode pad SE, and therefore, the length of the front surface 10t in the X direction is larger than that of the semiconductor chip 10 of
Each of the semiconductor chip 10A of
For example, as a modification example of
Although not illustrated, the width P1 of the region 13R1 may be made equal to or larger than the width WH1 of the bonding surface SEt1 as another modification example of
The number of the wires 12 connected to the source electrode pad SE is not limited to two or three and may be, for example, four or more. By the increase in the number of the wires 12, the impedance of the conductive path can be decreased. However, from the viewpoint of suppressing the increase in the plane area of the semiconductor chip 10, it is preferable to reduce each width (the width P1 and width P2 shown in
The embodiment has described, for example, the aspect as shown in
A semiconductor chip 10C shown in
In the case of the semiconductor chip 10C of
Similarly, in the case of the semiconductor chip 10C, the gate electrode pad GE is electrically connected to the plurality of gate electrodes G of the plurality of transistors Q1 via a wiring (gate wiring) GW.
The semiconductor chip 10C of
The embodiment has described, for example, the aspect as shown in
In the X direction in the semiconductor chip 10D of
In the X direction shown in
In the case of the modification example shown in
Such a method as reducing the overall impedance as much as possible by making the width WW1 and the width WW3 shown in
As a modification example of the example shown in
In the example shown in
As another modification example of
The embodiment has described, for example, the case as shown in
When it is difficult to determine apexes at the peripheries as seen in the bonding surfaces SEt1 and SEt2 included in a semiconductor chip 10E shown in
That is, in a plan view, the bonding surface SEt1 and the bonding surface SEt2 are arranged side by side in the X direction intersecting the Y direction. In the X direction, the periphery (outline) of each of the bonding surface SEt1 and the bonding surface SEt2 has a portion HP1 (equivalent to the side HS1 of
In the definition as described above, the side HS1 (see
As another modification example of
In a case of the large number of the bonding parts between the wire 12S1 and the bonding surface SEt1, the length of the bonding surface SEt1 in the Y direction (for example, the lengths of the sides HS1 and HS2 in the example shown in
In the above-described embodiment, a MOSFET is exemplified as an example of a power transistor included in a power semiconductor device. However, various modification examples are applicable. For example, an IGBT may be provided instead of the MOSFET. This case can be achieved by interpreting the drain of the MOSFET in the embodiment described above as the collector of the IGBT and interpreting the source of the MOSFET as the emitter of the IGBT. When the IGBT is used, a diode (free wheeling diode (FWD)) chip that controls a flow direction of a load current is mounted separately from an IGBT chip in many cases. Thus, on the die pad 20 shown in
In the above-described embodiment, the power semiconductor device has been exemplified and described as an example of a semiconductor device to which severe demands in environment temperature and temperature cycle load resistance tend to be required. However, even in a case of a semiconductor device other than the power semiconductor device, such as a control-system semiconductor device and a communication-system semiconductor device, if a specification of the demands in the environment temperature and the temperature cycle load resistance is high, performances concerning the environment temperature and the temperature cycle load resistance can be improved by applying the techniques described in the above-described embodiment and modification examples. In the semiconductor device other than the power semiconductor device, a gold (Au) wire is used as the wire, and the ball bonding method is used as the wire bonding method in many cases.
Seventh Modification ExampleThe above embodiment has described the aspect in which, for example, the X direction which is the direction of arrangement of the bonding surfaces SEt1 and SEt2 and the Y direction which is the direction of extension of the bonding surfaces SEt1 and SEt2 extend the respective outer peripheral sides of the front surface 10t of the semiconductor chip 10 as seen in the semiconductor chip 10 of
A semiconductor chip 10F shown in
In a case of the modification example shown in
As shown in
The various modification examples have been explained as described above. However, for example, the modification examples described above can be combined with one another and applied. And, parts of the modification examples may be extracted and combined with one another.
Technical concepts of the semiconductor device and the method of manufacturing the semiconductor device described above in the embodiment are extracted as follows.
[Statement 1]
A semiconductor device includes: a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface; a first conductive member bonded to the first bonding surface of the semiconductor chip; a second conductive member bonded to the second bonding surface of the semiconductor chip; and a sealer that seals the semiconductor chip, the first conductive member, and the second conductive member so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip. The first conductive member includes: a first connecting portion bonded to the first bonding surface; a second connecting portion bonded to the first bonding surface; and a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface. The second conductive member includes: a third connecting portion bonded to the second bonding surface; a fourth connecting portion bonded to the second bonding surface; and a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface. In a plan view, the first bonding surface and the second bonding surface are arranged side by side in a second direction intersecting the first direction. A periphery of each of the first bonding surface and the second bonding surface includes: a first portion (first side) closer in the second direction to one side of a wire bonded to each of the bonding surfaces; and a second portion (second side) closer in the second direction to the other side of the wire. In the second direction, the second portion of the first bonding surface and the first portion of the second bonding surface are arranged so as to be adjacent to each other across a first region of the insulating film. In the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first conductive member and the second portion of the first bonding surface, is smaller than a width of the first region of the insulating film.
[Statement 2]
A semiconductor device includes: a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface; a first conductive member bonded to the first bonding surface of the semiconductor chip; a second conductive member bonded to the second bonding surface of the semiconductor chip; and a sealer that seals the semiconductor chip, the first conductive member, and the second conductive member so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip. The first conductive member includes: a first connecting portion bonded to the first bonding surface; a second connecting portion bonded to the first bonding surface; and a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface. The second conductive member includes: a third connecting portion bonded to the second bonding surface; a fourth connecting portion bonded to the second bonding surface; and a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface. In a plan view, the first bonding surface and the second bonding surface are arranged side by side in a second direction intersecting the first direction. A periphery of each of the first bonding surface and the second bonding surface includes: a first portion (first side) closer in the second direction to one side of a wire bonded to each of the bonding surfaces; and a second portion (second side) closer in the second direction to the other side of the wire. In the second direction, the second portion of the first bonding surface and the first portion of the second bonding surface are arranged so as to be adjacent to each other across a first region of the insulating film. In a plan view, an area of the first region sandwiched between the second portion of the first bonding surface and the first portion of the second bonding surface is larger than an area of a part of the first bonding surface, the part not overlapping the first conductive member.
[Statement 3]
In the Statement 2, in a plan view, each of the first opening and the second opening of the insulating film includes: a first side extending in the first direction; a second side extending in the first direction and being opposite to the first side; a third side extending in the second direction intersecting the first direction; and a fourth side extending in the second direction and being opposite to the third side. In a plan view, an outer periphery of the first region includes: the second side of the first opening; the first side of the second opening; a fifth side extending from an intersection between the third side and the second side of the first opening to an intersection between the third side and the first side of the second opening; and a sixth side extending from an intersection between the fourth side and the second side of the first opening to an intersection between the fourth side and the first side of the second opening. An area of the first region and an area of the first opening are equal to each other.
[Statement 4]
In the Statement 2, in a plan view, each of the first opening and the second opening of the insulating film includes: a first side extending in the first direction; a second side extending in the first direction and being opposite to the first side; a third side extending in the second direction intersecting the first direction; and a fourth side extending in the second direction and being opposite to the third side. In a plan view, an outer periphery of the first region includes: the second side of the first opening; the first side of the second opening; a fifth side extending from an intersection between the third side and the second side of the first opening to an intersection between the third side and the first side of the second opening; and a sixth side extending from an intersection between the fourth side and the second side of the first opening to an intersection between the fourth side and the first side of the second opening. An area of the first region and an area of the first opening are different from each other.
[Statement 5]
In the Statement 2, in a plan view, an area of the first opening and an area of the second opening are equal to each other.
[Statement 6]
A method of manufacturing a semiconductor device includes the following steps.
The steps include: (a) a step of preparing a semiconductor chip including a first main surface formed with an insulating film and a first electrode covered with the insulating film and having bonding surfaces exposed from a plurality of openings formed in the insulating film, and including a first back surface being opposite to the first main surface; (b) a step of preparing a lead frame having a chip mounting portion having a second main surface to which the semiconductor chip is fixed, a first lead extending from the chip mounting portion, and a second lead extending so as to be side by side with the first lead; (c) a step of, after the step (a) and the step (b), mounting the semiconductor chip on the chip mounting portion so that the first back surface of the semiconductor chip faces the second main surface of the chip mounting portion; (d) a step of, after the step (c), electrically connecting the first lead to the bonding surfaces of the first electrode, the bonding surface being exposed from the plurality of openings of the semiconductor chip, via a plurality of conductive members by using a first bonding tool; and (e) a step of, after the step (d), sealing the semiconductor chip, a part of the chip mounting portion, the plurality of conductive members, a part of the first lead, and a part of the second lead, with a resin so that the resin is in contact with the bonding surfaces of the first electrode. At the step (a), the plurality of openings are arranged in the first direction in a plan view, each of the plurality of openings of the insulating film includes, in a plan view, a first side extending in the first direction, a second side extending in the first direction and being opposite to the first side, a third side extending in a second direction intersecting the first direction, and a fourth side extending in the second direction and being opposite to the third side, and the fourth side of a first opening of the plurality of openings and the third side of a second opening of the plurality of openings are located adjacent to each other across a first region of the insulating film in a plan view. The step (d) includes: (d-1) a step of, at the first opening of the plurality of openings, bonding the bonding surface to a first connecting portion of a first conductive member of the plurality of conductive members; (d-2) a step of, after the step (d-1), at the first opening, bonding the bonding surface to a second connecting portion of the first conductive member; and (d-3) a step of, after the step (d-2), bonding the first lead to a third connecting portion of the first conductive member. In the first direction, a width of the first opening is smaller than a width of a tip portion of the first bonding tool. At the steps (d-1) and (d-2), a part of the tip portion of the first bonding tool is arranged at a position at which the part of the tip portion covers a part of the insulating film.
[Statement 7]
In the Statement 6, the step (d) includes a step of, after the step (d-1) and before the step (d-2), moving the first bonding tool to be away from the bonding surface, and then, moving the first bonding tool in the second direction.
[Statement 8]
In the Statement 6, the step (d) includes a step of, after the step (d-2) and before the step (d-3), moving the first bonding tool to be away from the bonding surface, and then, moving the first bonding tool toward the first lead.
[Statement 9]
In the Statement 6, after the step (d), the first conductive member intersects any one of a plurality of sides of the first opening in a plan view.
[Statement 10]
In the Statement 6, in the first direction, a width of the first region of the insulating film, the first region being sandwiched between the fourth side of the first opening and the third side of the second opening, is smaller than a width of a tip portion of the first bonding tool.
Claims
1. A semiconductor device comprising:
- a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface;
- a first wire bonded to the first bonding surface of the semiconductor chip;
- a second wire bonded to the second bonding surface of the semiconductor chip; and
- a sealer that seals the semiconductor chip, the first wire, and the second wire so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip,
- wherein each of the first bonding surface and the second bonding surface is made of a metal material,
- the sealer is made of a resin material,
- the first wire includes: a first connecting portion bonded to the first bonding surface; a second connecting portion bonded to the first bonding surface; and a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface,
- the second wire includes: a third connecting portion bonded to the second bonding surface; a fourth connecting portion bonded to the second bonding surface; and a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface,
- in a plan view, the first loop portion includes: a fist side extending from the first connecting portion to the second connecting portion in the first direction; and a second side being opposite to the first side,
- in a plan view, the second loop portion includes: a third side extending from the third connecting portion to the fourth connecting portion in the first direction; and a fourth side being opposite to the third side,
- in a plan view, the first opening and the second opening are arranged in a second direction intersecting the first direction so that the second side of the first loop portion and the third side of the second loop portion are adjacent to each other,
- in a plan view, a width of a first region of the insulating film, the first region being sandwiched between the second side of the first wire and the third side of the second wire, is larger than a width of a region sandwiched between the first side and the second side of the first wire, and
- each of the width of the first region and the width of the region sandwiched between the first side and the second side of the first wire is defined as a length in the second direction.
2. The semiconductor device according to claim 1,
- wherein the first bonding surface is a first part of a first electrode formed on the first main surface and covered with the insulating film, and
- the second bonding surface is a second part of the first electrode formed on the first main surface and covered with the insulating film.
3. The semiconductor device according to claim 1,
- wherein the first bonding surface is a first part of a first electrode formed on the first main surface and covered with the insulating film, and
- the second bonding surface is a first part of a second electrode formed on the first main surface and covered with the insulating film.
4. The semiconductor device according to claim 1,
- wherein, in the second direction, a width of the third connecting portion of the second wire is smaller than a width of the first region of the insulating film and is different from a width of the first connecting portion of the first wire.
5. The semiconductor device according to claim 1,
- wherein, in the second direction, a width of the third connecting portion of the second wire is equal to a width of the first connecting portion of the first wire.
6. The semiconductor device according to claim 1,
- wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, is smaller than a width of the first region of the insulating film.
7. The semiconductor device according to claim 1,
- wherein, in the second direction, a total of a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, and a maximum width of another region of the first bonding surface, the another region being sandwiched between the first wire and the first side of the first bonding surface, is smaller than a width of the first region of the insulating film.
8. The semiconductor device according to claim 1,
- wherein, in the second direction, a total of a maximum width of a region sandwiched between the first wire and the second side of the first bonding surface in a region sandwiched between the first wire and the second wire and a maximum width of a region sandwiched between the second wire and the first side of the second bonding surface in the region is smaller than a width of the first region of the insulating film.
9. The semiconductor device according to claim 1,
- wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, is smaller than a width of the first loop portion of the first wire.
10. The semiconductor device according to claim 1,
- wherein, in the second direction, a total of a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second side of the first bonding surface, and a maximum width of another region of the first bonding surface, the another region being sandwiched between the first wire and the first side of the first bonding surface, is smaller than a width of the first loop portion of the first wire.
11. A semiconductor device comprising:
- a semiconductor chip including a first main surface formed with an insulating film and a first electrode covered with the insulating film, the first electrode having bonding surfaces exposed from a plurality of openings formed in the insulating film;
- a chip mounting portion including a second main surface on which the semiconductor chip is mounted;
- a first lead extending from the chip mounting portion and a second lead extending along the first lead;
- a plurality of conductive members electrically connecting the second lead to the bonding surfaces of the first electrode, the bonding surfaces being exposed from the plurality of openings, respectively; and
- a sealer that seals the semiconductor chip, apart of the chip mounting portion, a part of the first lead, a part of the second lead, and the plurality of conductive members so that the sealer is in contact with the bonding surfaces,
- wherein each of the bonding surfaces is made of a metal material,
- the sealer is made of a resin material,
- in a plan view, the plurality of openings are arranged so as to be adjacent to each other in the first direction,
- in a plan view, each of the plurality of openings of the insulating film includes: a first side extending in the first direction; a second side extending in the first direction and being opposite to the first side; a third side extending in a second direction intersecting the first direction; and a fourth side extending in the second direction and being opposite to the third side,
- in a plan view, the fourth side of a first opening of the plurality of openings and the third side of a second opening of the plurality of openings are located so as to be adjacent to each other across a first region of the insulating film,
- a first conductive member of the plurality of conductive members includes: a first connecting portion connected to the first electrode at the first opening of the insulating film; a second connecting portion connected to the first electrode at the first opening of the insulating film; and a loop portion located between the first connecting portion and the second connecting portion, the loop portion being separated from the bonding surface of the first electrode, and,
- in the first direction, a thickness of the first region of the insulating film, the first region being sandwiched between the fourth side of the first opening and the third side of the second opening, is larger than a thickness of the loop portion of the first conductive member.
12. The semiconductor device according to claim 11,
- wherein, in the first direction, thicknesses of parts of the plurality of conductive members, the parts being connected to the first electrode, are different from each other.
13. The semiconductor device according to claim 11,
- wherein, in a plan view, an area of the first opening and an area of the second opening are different from each other.
14. The semiconductor device according to claim 11,
- wherein each of the plurality of conductive members has the first connecting portion, the second connecting portion, and the loop portion that are connected to the first electrode at each of the plurality of openings.
15. The semiconductor device according to claim 11,
- wherein, in a plan view, an outer periphery of the first region includes: the fourth side of the first opening; the third side of the second opening; a fifth side extending from an intersection between the first side and the fourth side of the first opening to an intersection between the first side and the third side of the second opening; and a sixth side extending from an intersection between the second side and the fourth side of the first opening to an intersection between the second side and the third side of the second opening, and,
- in a plan view, an area of a part of the first opening, the part not overlapping the first conductive member, is smaller than an area of the first region.
16. A semiconductor device comprising:
- a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface;
- a first wire bonded to the first bonding surface of the semiconductor chip;
- a second wire bonded to the second bonding surface of the semiconductor chip; and
- a sealer that seals the semiconductor chip, the first wire, and the second wire so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip,
- wherein each of the first bonding surface and the second bonding surface is made of a metal material,
- the sealer is made of a resin material,
- the first wire includes: a first connecting portion bonded to the first bonding surface; a second connecting portion bonded to the first bonding surface; and a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface,
- the second wire includes: a third connecting portion bonded to the second bonding surface; a fourth connecting portion bonded to the second bonding surface; and a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface,
- in a plan view, the first bonding surface and the second bonding surface are arranged side by side in a second direction intersecting the first direction,
- a periphery of each of the first bonding surface and the second bonding surface includes: a first portion closer in the second direction to one side of a wire bonded to each of the bonding surfaces; and a second portion closer in the second direction to the other side of the wire,
- in the second direction, the second portion of the first bonding surface and the first portion of the second bonding surface are located adjacent to each other across a first region of the insulating film,
- in the second direction, a width of the first region is larger than a width of the first loop portion of the first wire, and
- each of the width of the first region and the width of the first loop portion of the first wire is defined as a length in the second direction.
17. The semiconductor device according to claim 16,
- wherein, in a plan view, the first wire intersects a part of a periphery of the first opening, and the second wire intersects a part of a periphery of the second opening.
18. The semiconductor device according to claim 16,
- wherein, in the second direction, a maximum width of a region of the first bonding surface, the region being sandwiched between the first wire and the second portion of the first bonding surface, is smaller than a width of the first region of the insulating film.
19. The semiconductor device according to claim 16,
- wherein, in the second direction, the width of the first region includes a plurality of values, and
- a minimum value of the plurality of values included in the width of the first region is larger than a width of the first loop portion.
Type: Application
Filed: Oct 11, 2017
Publication Date: May 3, 2018
Inventors: Noriko OKUNISHI (Tokyo), Toshinori KIYOHARA (Tokyo)
Application Number: 15/729,715