APPARATUS AND METHODS FOR REMOVING A LARGE-SIGNAL VOLTAGE OFFSET FROM A BIOMEDICAL SIGNAL
Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
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This application is a divisional of U.S. patent application Ser. No. 17/477,213, filed Sep. 16, 2021, now allowed, which is a continuation of U.S. patent application Ser. No. 17/065,566, filed Oct. 8, 2020 (now U.S. Pat. No. 11,123,003), which is a divisional of Ser. No. 16/718,996, filed Dec. 18, 2019 (now U.S. Pat. No. 10,841,232), which is a divisional of U.S. patent application Ser. No. 16/195,562, filed Nov. 19, 2018 (now U.S. Pat. No. 10,686,715), which claims the benefit of U.S. Provisional Patent Application No. 62/669,345, filed May 9, 2018, entitled “Acquisition and Preservation of Electrical Signal Information in a Multi-Signal-Source Environment,” all of which are hereby incorporated by reference.
TECHNICAL FIELDEmbodiments included herein generally relate to cardiac electrophysiology (EP) signal acquisition and recording systems. More particularly, apparatus and method embodiments are disclosed for removing a large-signal voltage offset from a biomedical signal.
BACKGROUNDCatheter ablation is a procedure to treat arrhythmias such as atrial fibrillation, a disease of the heart muscle characterized by abnormal conduction. Depending on the severity of the problem, multiple ablation procedures may be necessary to achieve effective results. This is because current electrophysiology (EP) technology has limitations in precisely locating the tissue to ablate that is the source of the abnormality.
The conventional diagnostic process starts with an electrocardiogram (ECG) taken from electrodes attached to the surface of the skin of a subject (e.g., a patient). A medical team evaluates the ECG signal and determines whether medication and/or ablation are/is indicated. If ablation is indicated, an EP study is performed. A catheter is inserted into the heart via the patient's neck or groin and the electrical activity of the heart is recorded. Based on this EP study, ablation is performed on the area(s) of the heart that the medical team suspects is causing the abnormal heart rhythm(s).
An ablation catheter is inserted into the patient's blood vessel and guided to the site of the tissue that is causing the abnormal electrical propagation in the heart. The catheter may use different energy sources (the most common being heat or cold) to scar the tissue, reducing its ability to initiate and/or transmit abnormal electrical impulses, which eliminates the abnormal heart rhythm. ECG signals are recorded from a surface electrode on a patient's skin, and intracardiac (IC) signals may be obtained from catheters inside the patient's heart and recorded as an electrogram (EGM). Both ECG and IC (EGM) signals are small signals that require conditioning and amplification to be accurately evaluated.
In conventional EP systems, to confirm whether the ablation treatment of a certain tissue site is successful, the medical team must often stop the ablation process and collect physiologic signals (e.g., cardiac) from a monitoring device (e.g., ECG monitor). This is because current systems do not allow accurate simultaneous detection, acquisition, and isolation of small cardiac signals (on the order of 0.1-5 mV over a range of frequencies) in near real-time during the application of large ablation signals (on the order of a few hundred volts at frequencies around 450 kHz).
Specifically, U.S. Patent Application Publication No. US 2006/0142753A1 to Francischelli, et al. propose a system and method for ablation and assessing their completeness or transmurality by monitoring the depolarization ECG signals from electrodes adjacent to the tissue to be ablated. Francischelli, et al. point out that, to minimize noise-sensing problems during measurements of the ECG signals from the electrodes on the ablation device, the measurements are preferably made during interruptions in the delivery of ablation energy to the ablation electrodes.
Generally, some current EP recording systems can effectively support treatment of arrhythmias such as atrial flutter and supra ventricular tachycardia, which show up as large-amplitude, low-frequency signals. However, more complex and prevalent arrhythmias, such as atrial fibrillation and ventricular tachycardia, which are characterized by low-amplitude, high-frequency signals, have not found effective evaluation of all relevant signals.
This signal detection, acquisition, and isolation can be further complicated by equipment line noise and pacing signals. To remove noise and artifacts from the various electrical signal information, current EP recorders use low-pass, high-pass, and notch filters. Unfortunately, conventional filtering techniques can alter signals and make it difficult or impossible to see low-amplitude, high-frequency signals that can be inherent in cardiac monitoring, the visualization of which signals could help treat atrial fibrillation and ventricular tachycardia. It has been recently recognized that the assurance of waveform integrity, such as for noise-free acquisition of IC and ECG signals in an EP environment, had not been previously accomplished due to contamination of various signals by artifacts and noise.
Specifically, in an article titled Waveform Integrity in Atrial Fibrillation: The Forgotten Issue of Cardiac Electrophysiology (Annals of Biomedical Engineering, Apr. 18, 2017), Martinez-Iniesta, et al. point out that high-frequency and broadband equipment noise is “unavoidably recorded” during signal acquisition, and that further complications of acquisition result from a variety of other signals, including 50 or 60 Hz electrical mains, high-frequency patient muscle activity, and low-frequency baseline wander from respiratory or catheter movements or unstable catheter contact. Martinez-Iniesta, et al. further point out that regular filtering causes significant alteration of waveforms and spectral properties, as well as poor noise reduction. Yet aggressive filtering between 30 and 300 Hz is still a routine EP practice.
Conventional practices distort morphological features in resulting signals, causing loss of relevant (of interest) signal information and affecting signal validity. Martinez-Iniesta, et al. propose a partial software solution for only mid- and high-frequency noise reduction using preprocessing and de-noising methods, yet no solution exists combining low-frequency noise-reduction components in software with noise-reduction components in hardware. A desired feature of EP systems is the ability to preserve the integrity of original signal information using a combination of hardware and software that can remove noise from signals (or promote a high signal-to-noise ratio) while minimizing hardware filtering that would otherwise remove signal content of interest.
Currently, the predominant approach for ablation treatment of paroxysmal and persistent atrial fibrillation is pulmonary vein isolation (PVI), wherein a medical team, using a cardiac mapping system, recreates the heart geometry in 3D and performs ablation on anatomical locations such as the pulmonary vein from which the atrial fibrillation emanates. The procedure is a long 2-8 hours, and a physician may not achieve a durable lesion/scar to isolate the tissue causing the problem from the left atrium. Thus, patients are often required to return for additional ablation procedures to complete the treatment. However, additional ablation procedures, and possible complications, can be avoided by being able to clearly visualize the cardiac signals during ablation and determine whether an ablation lesion is transmural.
Conventional EP systems may suffer from several other limitations. First, a user often wants to process and display multiple versions of signals in near real-time. For example, a medical team may want to simultaneously display various and multiple versions of ECG, IC, and other physiologic signals in near real-time to evaluate different signal attributes. But conventional EP systems are often unable to simultaneously process and display multiple versions of signals in near real-time.
Second, a user often wants to dynamically apply a new digital signal processing function to a signal without interfering with other digital signal processing functions already being applied to the signal. But conventional solutions do not enable a user to dynamically apply a new digital signal processing function to a signal without stopping the capture of the signal, or interfering with other digital signal processing functions already being applied to the signal.
Finally, a user often wants to synchronize the processing and display of multiple signals in near real-time. For example, a user may want to synchronize the display of multiple processed versions of the same signal. Further, a medical team may want to synchronize the display of multiple processed versions of ECG, IC, and other physiologic signals. This is because the ability of the medical team to make an effective clinical diagnosis may depend on comparing multiple signals at the same point in time. But conventional solutions may not be able to process and synchronize the display of multiple processed signals in near real-time.
SUMMARY OF THE EMBODIMENTSApparatus, systems, and methods are disclosed for EP signal acquisition and recording with multiple improvements in noise cancellation, sampling rate, and dynamic range in various biomedical applications.
The embodiments of the disclosed EP system can record raw (unaltered) cardiac and other physiologic signals with multiple display options and with low noise and large input signal dynamic range. This is achieved using a low-noise amplifier topology, with minimal filtering to band-limit the signal, and a high-resolution A/D converter. In addition, the disclosed EP system can provide large-signal (e.g., from a defibrillator) input protection and radio frequency (RF) signal (e.g., from ablation) noise suppression. In this architecture, there is no need for gain switching, and the full range of input signals is digitized with high resolution.
Raw signals acquired by an acquisition module are filtered and processed in accompanying software using a digital processing module, with minimal use of filters in the hardware (e.g., hardware filters are only used for AC coupling, anti-aliasing, and RF suppression). The use of software-based digital signal processing algorithms allows the display of signals in real-time as a raw signal, or as a combination of raw and processed signals simultaneously in real-time in a single window or in multiple windows. Furthermore, the visualization and review capabilities of the disclosed EP system allow a user to mark features specified in algorithms on real-time tracings.
The disclosed EP system allows for the display of signals with more than one signal processing algorithm applied at the same time, a feature not found in conventional systems. This allows a user to look at signals filtered in multiple ways for specific reasons. In the real-time window, waveforms of interest can be displayed as raw signals or as any combination of raw and filtered signals to enable better visualization of signals in the presence of noise and artifacts.
All displayed signals are time synchronized. On a review screen, the user has the option of opening multiple review windows, with the ability to display the results of various signal-processing algorithms, independent of the real-time tracings. The disclosed EP system also uses novel optimal biphasic waveforms and signal processing algorithms for signal enhancement during pacing, and novel algorithms for enhanced user visualization.
From a clinical perspective, the disclosed EP system can significantly assist in a medical team's decision making for patients undergoing various medical therapies (such as ablation), with benefits including, but not limited to: suppression of RF energy for cleaner, more reliable recordings of intracardiac signals, less wander, and noise reduction; improved dynamic range for better visualization, especially of very low amplitude signals temporally situated within large-amplitude signals; real-time digital processing and recording of raw signals to facilitate signal filtering without affecting original information and to reduce artifacts and noise; high-quality unipolar signals to assist in the determination of tissue type and catheter location; improved waveform integrity and reduced artifacts that are byproducts of signal processing, allowing a medical team to enhance procedure outcomes; and improved signal information, allowing a medical team to provide more accurate catheter tip position for ablation and other therapeutic levels and durations for therapy effectiveness.
Some embodiments herein describe a circuit for removing a large-signal voltage offset from a biomedical signal. The circuit includes a first operational amplifier having a differential input and a differential output, and is configured to receive the biomedical signal with the large-signal voltage offset at the differential input. The circuit also includes a second operational amplifier having a common mode voltage input and configured to output a common mode reference voltage at a common mode node. A first pair of diode stages is coupled between the differential output and respective ones of a first differential node and a second differential node and is configured to monitor an amplitude of the large-signal voltage offset. A plurality of timing banks is coupled between the respective ones of the first differential node and the second differential node and the common mode node. The first pair of diode stages and the plurality of timing banks may be configured to attenuate the large-signal voltage offset persisting for a duration of at least the time constant, wherein the large-signal voltage offset is above an activation threshold. Further, a second pair of diode stages is coupled between the respective ones of the first differential node and the second differential node and the common mode node, wherein the large-signal voltage offset is attenuated at an output of each of the second pair of diode stages. The second pair of diode stages is configured to limit a saturation duration of the large-signal voltage offset to shorter than a saturation recovery time.
Various method embodiments are described for removing a voltage offset from an electrical signal (e.g., a biomedical signal in some embodiments), including receiving, at a differential input of a first operational amplifier, the electrical signal, and amplifying, by the first operational amplifier, the electrical signal by a first gain. Method embodiments include monitoring, by a first pair of diode stages coupled to a differential output of the first operational amplifier, an amplitude of the electrical signal for the voltage offset. Further, the method embodiments include attenuating, by the first pair of diode stages and a plurality of timing banks, the amplitude of the electrical signal. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks from the electrical signal and producing, by the plurality of timing banks, a differential signal. The attenuating further includes charging of a resistor-capacitor network of the plurality of timing banks and setting, by the plurality of timing banks, a time constant based on the charging of the resistor-capacitor network. The method allows for attenuating the amplitude of the differential signal to remove the voltage offset persisting at an activation threshold for a duration of at least the time constant.
Some method embodiments include limiting, by a second pair of diode stages, the differential signal from the plurality of timing banks and further limiting a saturation duration of the differential signal to less than a saturation recovery time. Some method embodiments further include pulling an output voltage of the second pair of diode stages toward a common mode reference voltage at a common mode node coupled to the plurality of timing banks. Some method embodiments may include pulling, by the second pair of diode stages, a positive input node voltage of the first operational amplifier down toward the common mode reference voltage and a negative input node voltage of the first operational amplifier up toward the common mode reference voltage. Some method embodiments further include limiting, by the second pair of diode stages, the differential signal from the plurality of timing banks, wherein the positive input node voltage and the negative input node voltage are gradually pulled into monitoring range after about the saturation recovery time.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present embodiments and, together with the description, further serve to explain the principles of the present embodiments and to enable a person skilled in the relevant art(s) to make and use the present embodiments.
The features and advantages of the present embodiments will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION OF THE INVENTIONApparatus, systems, and methods related to a unique amplifier topology are disclosed for conditioning cardiac (e.g., ECG and IC) and other physiologic signals, specifically to clearly define and record low-amplitude, low-frequency information, which may be acquired during ablation and other similar large-signal perturbations, such as pacing and stimulation. During procedures, the tip of a catheter (or other electrodes) can be connected to pacing, ablation, and stimulator systems to allow visualization, pacing, ablation, and stimulation without mode switching. For example, the disclosed apparatus, systems, and methods can effectively separate ablation signals from cardiac signals during ablation while simultaneously providing input protection against high voltage, such as from defibrillation signals. Similarly, the disclosed apparatus, systems, and methods can effectively separate stimulation signals from physiologic signals during stimulation.
As different system recording requirements cannot be satisfied simultaneously for each signal type, each block, or module, of the system can be performance optimized to achieve multiple signal conditioning requirements desired by clinicians. The various embodiments can enable the system to handle cardiac, pacing, ablation, defibrillation, stimulator, and other physiologic signal types simultaneously by detecting, conditioning, and displaying the signal of interest, to monitor, for example, the effect of an ongoing procedure on a cardiac signal.
Additionally, the various embodiments can ensure the acquisition of multiple low-amplitude cardiac signals in the presence of numerous sources of electrical noise and environmental interference aside from the large signals injected during ablation and stimulation procedures, pacing, or defibrillation. The cardiac signals of interest can also be displayed in an uncomplicated and clinically-relevant way, processing the signals in real-time, or near-real-time, to display a comprehensive cause-and-effect relationship between physician-initiated procedures and resulting cardiac signals, while contemporaneously identifying signal artifacts and removing unwanted noise. This disclosure identifies both hardware and software embodiments to achieve these objectives.
This disclosure refers to both “unipolar” and “bipolar signals,” which are both widely used in EP recordings, but for complementary purposes. Both unipolar and bipolar signals are taken from the potential difference recorded at two (or more) different, separated electrodes on a patient's body, specifically the limbs and chest of the patient, for example, to measure ECG signals, or at two (or more) different, separated catheters placed directly on cardiac tissue, for another example, to measure IC signals.
It is conventional to use a 12-lead ECG system consisting of a connection to each of the limbs: right arm (RA), left arm (LA), right leg (RL), and left leg (LL), and six precordial connections V1 through V6 from six separate electrodes placed at various locations on the patient's chest. The individual ECG electrode wires are connected to a terminal block at the end of a patient table, routing from there to a data acquisition system. All leads are conventionally connected to protection circuitry to prevent damage to the instrumentation caused by defibrillation potentials or static electricity from the environment.
Bipolar signals are standard for certain ECG measurements (lead I, II, III), but they may also be obtained directly from the heart surface to collect IC signals. Bipolar signals may be obtained by attaching two (or more) electrodes in close proximity in a specific area of the heart or cardiac tissue and measuring the potential difference between the electrodes, providing information about local electrical activity, such as late potentials caused by damaged heart muscle. Bipolar IC signals do not, however, provide information about electrical impulse propagation direction.
Unipolar signals arise from a point source, such as may be obtained from an IC potential, by placing one IC electrode on the surface of the patient's heart and the other electrode at a distance from the first to serve as a reference signal. Unipolar leads from IC electrodes are connected in such a way that one lead serves as the active lead while the other lead(s) is/are at an inactive location or the result of a calculated inactive location (WCT, discussed below). In this way, the current flowing towards the active electrode produces a positive deflection, while current flowing away from the active electrode produces a negative deflection. This provides information about cardiac signal propagation direction. Unipolar recordings are especially useful when directionality information is desired, such as in the determination of depolarization and repolarization pathways in the endocardium and epicardium.
Leads may also be connected to the limbs to create an imaginary triangle called “Einthoven's triangle.” In this way, true bipolar leads can be obtained by referencing each connection to one of the other two (e.g., LA referenced to RA is Lead I; LL to RA is Lead II, and finally, LA to LL is Lead III). Then, an average of the three limb wires RA, LA, and LL can approximate a zero potential point to provide a reference electrode (WCT, discussed below). Here, the vector sum of Lead I and Lead III is Lead II.
Using the concept of Einthoven's triangle, the Wilson Central Terminal (WCT) is an electrical circuit concept used in the art (and discussed further in this disclosure) that can be used as an indifferent electrode that acts as an electrical center of the heart as a reference. The WCT can be used when IC signals are desired to be displayed in unipolar fashion. When using the WCT as a reference for unipolar signals, the unipolar signals can approximate widely-spaced bipolar signals for consistent unipolar recording. The WCT can prevent an additional catheter from having to be used as a reference for unipolar recordings of IC signals.
In this disclosure, “near real-time” refers to the acquisition and visualization of signals through the EP system from the time they occur at the input of the hardware circuitry of the EP system to the time they are first displayed on the EP system display monitor(s), either in raw (unprocessed) form or after being processed by the EP system Main Processing Unit (MPU) and one or more digital signal processing (DSP) module(s). “Near real-time” for a raw signal can be less than approximately five (5) milliseconds, and for a processed signal can be less than approximately fifty (50) milliseconds.
As the number of connections to the patient 118 increases, the leakage current 122 from all patient connections through the patient 118 to earth ground 120 increases, increasing the likelihood of interference and adverse effects. Total leakage current 122 when such equipment is connected and operating at the same time may safely and allowably be up to several tens of microamperes at a fundamental mains frequency of 50 or 60 Hz, with harmonics extending to several thousand Hertz. This leakage current 122 can interfere substantially with the processing of ECG and IC signals. Furthermore, the patient 118 can be both capacitively coupled 124 and inductively coupled 126 to the 120/240 AC power mains 102. The patient 118 may additionally pick up RF interference 116 from equipment in proximity to the EP environment, such as wireless headsets, mobile phones, and wireless monitors.
For reference, TABLE 1 outlines signals that may be found in a conventional medical instrumentation/EP environment, both wanted and unwanted, and their signal characteristics.
As a result of equipment noise and other EP environment interference, measured voltages on a patient's body can be upwards of 1-3 V RMS (root mean squared) over a frequency spectrum ranging from 50 Hz to several tens of megahertz. Yet, the amplitude of cardiac signals can measure in the range of 25 microvolts to 5 mV. To display these signals amongst the noisy environment, the cardiac signals are conventionally amplified and displayed with no loss of detail (so as not to miss relevant information, for example) and minimal added noise (so as not to cover up signal details, for example), while delivering RF ablation energy at about 70 V RMS at 500 kHz, or cardiac stimulation up to 25 mA, for example.
To properly acquire and identify cardiac signals of interest in such an environment, a very high signal-to-noise (SNR) ratio (on the order of 30 dB) is desirable but not achievable without an approach to minimize or eliminate sources of electrical interference before having to process them electrically through software methods. Conventional hardware approaches used to condition the signals in such a noisy environment include shielding of cables, grounding of equipment, balancing inputs and outputs, differential amplification, filtering, lowering circuit impedances, electric isolation, or signal enhancement techniques. These conventional methods have had limited success in achieving sufficient SNR.
The disclosed hardware embodiments can decrease interference while applying novel electrical circuit topology to minimize noise, isolate the IC and ECG signals of interest, condition those signals, and remove unwanted artifacts. This can be done before the signals are passed to processing software that provides an electrophysiologist the power of near real-time visualization and comprehensive signal review. Embodiments of the EP system described herein can achieve considerable SNR improvement.
The EP console 214 can include one or more ECG amplifiers 218, one or more unipolar amplifiers 220 to process unipolar signals, and one or more bipolar amplifiers 222 to process bipolar signals from a plurality of ECG and EGM monitoring units 224. The EP console 214 can also include a dedicated AC input filter 234, a AC/DC power supply 236, and a DC/DC power supply 238 to condition and transform mains 120/240 V, 50/60 Hz source power 240 into DC power for use by the diagnostic equipment. ECG and EGM electrode inputs 232 can enter the EP console 214 through a yoke 226 that provides additional input impedance for protection. Junction boxes (1 and 2) 228, 230 can provide convenient plug-in interfaces for IC catheter inputs (not shown) for subsequent processing by EGM monitoring units 224.
In
In
In
The functionality of the specific Blocks 1-11 of
The analog input protection/filtering stage 530 of the EP system, shown in
Specifically, the analog input protection/filtering stage 530 can reduce high voltage transients at the ECG, IC, and other electrode lead inputs, which are connected to the patient's body, to less than ten (10) volts, for example, at the inputs to the EP system buffers. The analog input protection/filtering stage 530 can stop a large signal, for example, from a defibrillator, from damaging other portions of the system. In addition, the analog input protection/filtering stage 530 can perform these functions without sinking more than 10%, for example, of the energy of an applied defibrillation pulse, without clamping, or without adding non-linearities when ablation signals are applied.
Conventionally, a defibrillation signal of approximately 5000 V would be clamped to +/− 5 V to prevent harm. In the case of this disclosure, defibrillation signals can be similarly clamped, but ablation signals with an ablation voltage of approximately 200 V at 500 kHz, for example, can be passed linearly and attenuated by the input resistors RCable, 602, 604 and Block 2 (
The input overvoltage protection circuitry 600 does not clamp the ablation signal; rather, the ablation signal is attenuated linearly (e.g., reduced in direct proportion by the input resistors RCable, 602, 604 and RF filter 702) so that it is not inadvertently altered. For example, if the ablation signal is clamped by the input overvoltage protection circuitry 600, there would be no further access to the contents of that signal above the clamping. Advantageously, linear attenuation of the ablation signal by the disclosed EP system can permit recording small cardiac signals of a few millivolts during ablation. A person of ordinary skill in the art will appreciate that the apparatus, systems, and methods disclosed herein apply similarly to other high-frequency signals that may need to be passed through the protection circuit (e.g., not clamped) to prevent generation of non-linearities that would affect the signals of interest.
Transient voltage suppressor (TVS) diodes 628, 630 can provide ESD protection exceeding 16 kV by shunting excess current when the induced voltage exceeds their breakdown voltage. TVS diodes 628, 630 can function as “clamping,” or limiting, devices to suppress an overvoltage above their breakdown voltage and can automatically reset when the overvoltage subsides. TVS diodes 622, 630 can also respond to overvoltages faster than other common overvoltage protection components; e.g., “clamping” occurs in about one picosecond. TVS diodes generally can be advantageous for protection against very fast and potentially damaging voltage transients.
The ESD voltage suppressor diodes 610 in
The next stage in
Finally, as shown in
A person of ordinary skill in the art will understand that the combination of input protection circuitry shown in
For example,
RF Filter Circuitry with Low-Frequency Feedback and Shield Drive
In addition to its contribution to the input protection circuitry to filter and linearly attenuate ablation signals at the EP system input, RF filter 702 can function in concert with the low-frequency feedback circuit of Block 10 (see
The RF filter 702 can be designed to linearly attenuate the amplitude of the ablation signal by at least 75% in some embodiments, or even by at least 90% in other embodiments, for example. The RF filter 702 can be designed to provide substantially no attenuation to an input signal having a frequency less than 5 kHz, for example. This RF filter 702 can also function in concert with the shield drive 730 of Block 11 (see
Block 10 (see
Specifically, high input impedance at the instrumentation amplifier 1001 of
To mitigate that loss and maintain high common mode rejection (e.g., on the order of 100 dB), it is desirable to maintain high impedances at the power line frequencies so that variations in source impedance do not convert common mode signals into differential signals. The Block 10 low-frequency feedback circuit 1600 illustrated in
When the Block 10 low-frequency feedback circuit 1600 drives the RF filter 702 at low frequencies, there is little or no voltage variation across the capacitors 714, 716. Thus, at low frequencies, capacitors 706, 714, 716 act as open circuits and the high input impedance is maintained. But at higher frequencies, the feedback from the Block 10 low-frequency feedback circuit 1600 is reduced due to the low-pass filtering functionality of Block 10.
Specifically, the combination of a capacitor 1666 and a resistor 1693 at the inverting input to the operational amplifier 1606 filters high frequencies. The output of this circuit no longer tracks the input and holds the Shield1 728 (also the reference node of the RF filter 702) to a fixed level with respect to high frequency signals. This enables the RF filter's 702 passive RLC network 706, 708, 710, 712, 714, 716 to attenuate the high frequency signals.
Specifically, the Block 10 low-frequency feedback circuit 1600 (see also
The RF filter 702 of Block 2 404a, 404b is enabled for filtering at high frequencies, but the RF filter 702 is disabled at low frequencies when receiving feedback from the low-frequency feedback circuit 1600 of Block 10 420a, 420b. At high frequencies, the capacitors 706, 714, 716 in the RF filter 702 function as shunting capacitors that effectively short circuit signals at RF frequencies. The impedance of the capacitors 706, 714, 716 decreases linearly as the frequency becomes higher. The low-frequency feedback circuit 1600 does not affect the EP system at high frequencies.
At low frequencies, the low-frequency feedback correcting signal, Shield1 728 from Block 10 (see
The goal of the low-frequency feedback is to drive the difference between Shield1 728 and Buf1 1602 to zero, such that Shield1 728 equals Buf1 1602. When this occurs, input capacitance can be eliminated. At high frequencies, the positive feedback from operational amplifier 1606 is reduced to zero. In addition, at high frequencies capacitor 722 (which is 30 times larger than other capacitors in the circuit, for example) acts as a short circuit between Shield1 728 and ground. This effectively grounds the reference node of the RF filter 702, fully enabling it to attenuate RF frequencies. Thus, the Block 10 low-frequency feedback circuit 1600 works in concert with a unique arrangement of the Block 2 RF filter 702 elements to remove the loading effect of the RF filter 702 before passing signals to the Block 5 instrumentation amplifier 1001.
In this manner, the instrumentation amplifier 1001 can condition cardiac signals without the overlying ablation signal. The result is that the input to the overall circuit at low frequencies still sees a very high input impedance (e.g., on the order of 10s of MOhms) that is advantageous to visualizing high-fidelity cardiac signals in an EP environment. Additionally, Block 10 is a symmetric (e.g., mirrored) circuit, so that common mode noise is subtracted as the signal propagates through the circuit. Another advantage of the low-frequency feedback circuit 1600 is that its output Shield1 728 can be used to drive the outer shields of the input cables, for example, at OutS1 of the shield drive 730 of
Block 11 (see
Block 3 (see
Block 4, the DC Block (see
The signal amplification stage 532 (see
Block 5 (see
Block 6 (see
At an output of Block 6, having a first fully differential amplifier 1020 referenced to common mode, the common mode level is set to 2.5 V as the signals enter Block 7 differential amplifier #2 1021. The circuit continues the low-pass filtering of the ablation signal to the outputs (B2OutP, B2OutN) of Block 7. Block 7, having a second fully differential amplifier 1034 similar to Block 6's differential amplifier 1020, has a gain of about 0.5, with additional filtering for RF attenuation provided by circuit elements 1022, 1024, 1026, 1028, 1030, 1032, 1036, 1038, 1040, 1042. This part of the signal amplification stage 532 maintains the fully differential signal path to continue rejection of noise.
The gain introduced by Block 7 allows the circuit to clip the signal at the input limits of the A/D converter, Block 8 (see
The overall gain of the signal amplification stage 532 of the disclosed EP system can be less than or equal to 20 in some embodiments, or can be less than or equal to 50 in other embodiments, for example. For example, in some embodiments, a gain of about 20 at the output of the instrumentation amplifier 1001, a unity gain at the output of differential amplifier #1 1017, and a gain of about 0.5 at the output of differential amplifier #2 1021 produce a system gain of about 10 at the inputs of the A/D converter 416. Generally, the signal amplification stage 532 can include an instrumentation amplifier 1001 with a gain greater than one (1) at its output, a differential amplifier #1 1017 with a gain of about one (1) at its output, and a differential amplifier #2 1021 with a gain of less than one (1) at its output.
The overall low gain of the system, due to its improved ability to remove noise, provides further improvement over conventional systems. Conventional systems that have a 16-bit A/D converter require high gain in order to visualize small signals that are obscured in the presence of higher-amplitude signals. Conventional systems can have gain of up to 5000, for example, causing saturation of signals to occur quickly. Further, if lower gain is used with a 16-bit converter, quantization noise can adversely affect the output results. With the disclosed system having a low gain of about 10, coupled to a 24-bit A/D converter, saturation is prevented until at least 250 mV, for example, of small-signal input, and quantization noise is avoided.
Fast Recovery/Large-Signal Detection/Fast Recovery CircuitryThe outputs from the Block 6 differential amplifier #1 1017, in addition to being passed to the Block 7 differential amplifier #2 1021, also are passed to Block 9 (see
Specifically, the large-signal detection/fast recovery circuit 1100 can detect that the differential input signal has been in excess of 100 mV, for example, for a duration of at least 10 milliseconds, which is identified as an abnormal operating range. On detection of this state, the large-signal detection/fast recovery circuit 1100 can reduce the time constant after the Block 4 DC blocking stage (see
In an embodiment, the first stage of the large-signal detection/fast recovery circuit 1100 has two operational amplifiers 1108, 1112, for example. The gain of the operational amplifier 1108 (e.g., about 40) determines the activation threshold, that is, at which signal amplitude the large-signal detection/fast recovery circuit 1100 can operate to limit (or “soft clamp”) a signal. The activation threshold determines how large the signal must be before the large-signal detection/fast recovery circuit 1100 becomes active and begins to pull the voltages at nodes In14 and In24 toward the common mode level. For example, operational amplifier 1108, with a gain of about 80, can activate the large-signal detection/fast recovery circuit 1100 at about 50 mV; with a gain of about 40, can activate the large-signal detection/fast recovery circuit 1100 at about 100 mV; and with a gain of about 20, can activate the large-signal detection/fast recovery circuit 1100 at about 200 mV. When the signal amplitude reaches the set amplitude level determined by the gain, the voltage will be enough to overcome the activation threshold of a first pair of diode stages 1114, 1116 to activate the large-signal detection/fast recovery circuit 1100.
Operational amplifier 1112 produces a unity gain to buffer the common mode (CM) signal, which provides a common mode reference for the signals through operational amplifier 1108. Operational amplifier 1108 receives U4Out1 and U4Out2 signals from Block 6 (see
The capacitors 1120, 1124, 1128, 1132 form an RC network at nodes C, D, E, and F with resistors 1118, 1122, 1126, 1130, which together serves as a timing network that determines a time constant. The time constant determines how long the signals can be at their maximum amplitude before the large-signal detection/fast recovery circuit 1100 pulls the voltages at nodes In14 and In24 toward CM. This RC network is hereinafter referred to as “timing banks” 1158. Some embodiments of the timing banks 1158 may be designed to produce a time constant of at least 10 milliseconds, for example, to prevent activation of the large-signal detection/fast recovery circuit 1100 during pacing signals of 2-milliseconds to 10-milliseconds duration, for example. Other embodiments may be designed to produce a time constant of at least five (5) milliseconds.
When the capacitors 1120, 1124, 1128, 1132 charge up, a difference is detected, and the signal passes through a second pair of diode stages 1146, 1148, which limits (or “soft clamps”) the input to between about +/− 100 mV, for example. This prevents the system from saturating for any appreciable amount of time (e.g., less than 100 milliseconds). The second pair of diode stages 1146, 1148 also ensures that there is no interaction between the large-signal detection/fast recovery circuit 1100 and the EP system if a signal is not large/long enough to require limiting. In other words, when it is not advantageous to activate the large-signal detection/fast recovery circuit 1100, the second pair of diode stages 1146, 1148 disconnects the large-signal detection/fast recovery circuit 1100. The Block 9 large-signal detection/fast recovery circuit 1100 ensures that the EP system is not affected by large signal spikes, and allows a steady-state response where the difference between the inverting and non-inverting U4Out1 and U4Out2 signals is about 100 mV, for example, where operational amplifier 1108 has a gain of about 40, for example.
The Block 9 large-signal detection/fast recovery circuit 1100 is situated in the EP system at a location to remove a large-signal voltage offset. A person of ordinary skill in the art will appreciate that the large signal detection/fast recovery circuit 1100 could be located elsewhere in the EP system where potential large signal spikes may occur and are unwanted. A person of ordinary skill in the art will also appreciate that electronic components, such as the capacitors 1120, 1124, 1128, 1132 and the resistors 1118, 1122, 1126, 1130 of the timing banks 1158, can be substituted within the large signal detection/fast recovery circuit 1100 to change circuit activation levels and times. The large-signal detection/fast recovery circuit 1100 can be used in various embodiments of other signal acquisition and processing systems to remove a large-signal voltage offset from other types of electrical signals, as would be appreciated by a personal of ordinary skill in the art.
In some embodiments, the outputs In14, In24 of the Block 9 large-signal detection/fast recovery circuit 1100 (see
The exemplary embodiment of the large-signal detection/fast recovery circuit 1100 of
Resistors 1002 and 1004, located before the instrumentation amplifier 1001 of
The plots in
As shown in plot V(C) of
The diodes in the large-signal detection/fast recovery circuit 1100 of
The A/D Converter 416, Block 8 (see
In some embodiments, the A/D converter 416 is highly linear, a characteristic of delta-sigma converters. The high linearity allows accurate digital signal processing to be performed in the software, as described below. This configuration minimizes hardware filtering to that advantageous for RF attenuation and anti-aliasing, and allows more flexibility of filtering and signal processing in software. The advantage of choosing a fully differential A/D converter is that common mode noise signals from any digital circuitry (e.g., a digital clock signal) are rejected.
Wilson Central Terminal-Right Leg Drive (WCT-RLD) CircuitAlthough input common mode signals can be at any frequency, the dominant signals are generally at the power line frequency: 60 Hz in the U.S., for example. In a conventional EP environment, ECG (and similar) equipment mitigates a large amount of 60 Hz noise that could be up to 100 times larger than the signal of interest. In addition, because of distortions in the power line signal, there is often a strong third harmonic at 180 Hz, which is generally the noisiest harmonic. Higher harmonics and other common mode signals are generally smaller and/or are above the frequency band of interest for the ECG and IC signals.
In some embodiments, a Wilson Central Terminal-Right Leg Drive (WCT-RLD) circuit is used to remove particularly the 60 Hz and 180 Hz noise by common mode rejection, that is, by enhancing the first and third harmonic frequencies of the power line signals and selectively feeding those signals back to the patient to cancel them out.
For example, a WCT circuit 2332 of
The addition of an active current via the right leg, the “right leg drive” (RLD) circuit 2330, to the WCT circuit 2332 allows the patient to be driven to the same voltage as the common amplifier, thus reducing the common mode voltage at the inputs of the ECG electrodes (LA, RA, LL, and V1 to V6). This can be done by generating the inverse of the common mode signal and applying that as an output to the right leg. Specifically, the right leg drive is represented by limb electrode RL. The patient 2302 receives, through the RL electrode, an RLD output 2310, a summed and inverted version of the other IC catheter signals or ECG electrode signals, canceling interference present in the patient's body. This, in combination with the common mode rejection properties of the signal amplification stage 532, can reduce common mode low-frequency interference to acceptable levels (specified by standard IEC 60601-2-25, for example).
However, because 60 Hz and 180 Hz noise is not equal in all parts of the body, common mode rejection alone cannot remove all of the noise. The WCT-RLD circuit 2300 of
In an exemplary embodiment using the WCT, the WCT input within the EP system can provide an optional unipolar input to replace the bipolar positive (+) or negative (—) catheter input to the Block 3 Buffer circuit (see
In some embodiments, a novel approach in the WCT-RLD circuit 2300 is to provide additional filter circuitry, called a “Twin-T” feedback network 2440 (see
For example, as illustrated in the plot 2500 of
Although Twin-T circuitry is used in electronic design, it has not been previously used in a WCT-RLD circuit as disclosed herein. The Twin-T feedback network 2440 removes power line signals conventionally passed by known circuits when generating a RLD signal, such that the power line signals do not affect phase response at higher frequencies. The Twin-T feedback network 2440 thus has an advantageous use for generating a RLD signal from electrode leads.
In the embodiment of
The following cases illustrate how the disclosed hardware circuitry conditions signals found in an EP environment, allowing improved cardiac monitoring in the midst of equipment and environment noise, and during procedures that introduce large, potentially interfering signals into the monitoring environment.
Signal Case #1—Common Mode 60 Hz and in-band 500 Hz Differential Signal
Signal case #1 presents a typical common mode 60 Hz noise signal with an in-band (less than 1000 Hz) differential signal as found from conventional IC leads. In this example, a series of signal plots representing the signal at exemplary nodes of the disclosed circuit is shown. The circuit amplifies the differential signal and rejects the common mode signal.
Signal case #2 presents a typical 500 kHz ablation signal applied to the EP system inputs during an ablation procedure as cardiac monitoring continues. The unwanted ablation signal is filtered and attenuated before reaching the A/D converter (see
As seen in
The plots of V(Shield1) and V(Shield2) shown in
As shown in
According to some embodiments, the Communication Module 510 of the MSU 504 transmits the independent digital signals from the A/D converter 416, 534 of the ECG board 506 and IC board 508 to the MPU 514 over a fiber optic link 512 for digital signal processing. The Communication Module 510 samples the output channels from the A/D converter 416, 534, converts them to serial format, and transmits the data over the fiber optic link 512. The signals are converted back to a parallel format at the receiving end of the fiber optic link 512 in the MPU 514.
In this specification, the ECG board 302, 506 and IC board 316, 508 are named thusly for sake of convenience. As would be understood by a person of ordinary skill in the art, the circuitry of the ECG board 302, 506 and IC board 316, 508 can accept other physiologic signals from various types of electrodes other than ECG and IC electrodes.
EP Recording System Software DescriptionProvided herein are system, apparatus, device, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for processing and displaying multiple signals in near real-time. For example, the embodiments may involve processing and display multiple biomedical signals (e.g., EP signals) in near real-time. Before describing further details of these embodiments, a brief overview of digital signal processing is provided.
At a high level, digital signal processing is the use of digital processing to identify particular features in a signal, or producing a signal that is of higher quality than the original signal (e.g., by removing noise from the signal). Digital signal processing may be performed on a digitized electrocardiography (ECG) or intracardiac (IC) signal representing the electrical activity of a heart over a period of time.
To perform digital signal processing on an analog signal, the analog signal needs to be converted to digital form. An analog-to-digital (AD) converter such as A/D converter 416 can convert the analog signal to digital form, as is well known to a person of ordinary skill in the art.
Digital signal processing may involve applying a digital signal processing function to one or more signal samples in a sequence of signal samples for a signal. A digital signal processing function can be a sequence of mathematical operations and computational algorithms. A digital signal processing function can measure, filter, compress, or optimize a signal sample, for example.
Digital signal processing can use different digital signal processing functions depending on the type of analysis and the type of signal being processed. For example, digital signal processing can use a different digital signal processing function to identify particular words in a speech signal or to remove motion blur from a video signal.
Digital signal processing systems have many applications such as audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications, digital synthesizers, radar, sonar, financial signal processing, and seismology. But conventional digital signal processing systems often cannot be used in certain applications such as biomedical signal processing. This is because conventional digital signal processing systems, including current EP solutions, are often unable to simultaneously display multiple signals in near real-time. Moreover, conventional solutions do not enable a user to dynamically apply a new digital signal processing function to a base signal. And, conventional solutions are often unable to synchronize the processing and display of multiple signals in near real-time. This is often problematic in clinical settings because the ability of a physician to make an effective clinical diagnosis may depend on comparing multiple signals at the same point in time. Finally, conventional EP systems that use analog filters are often unable to take full advantage of digital signal processing. This is because when functions are implemented in hardware, the options are greatly restricted. For example, the functions cannot be removed and therefore the full potential of digital signal processing cannot be obtained.
Signal path module 2602 includes input module 2604, timer 2605, packetizer 2606, queuing module 2608, packet dispatcher 2610, global signals table 2612, and output module 2616. Input module 2604, timer 2605, packetizer 2606, queuing module 2608, packet dispatcher 2610, global signals table 2612, and output module 2616 can be software modules capable of being executed by a processor (or processors) such as processor 5004. Signal path module 2602 solves at least the technological problem of how to synchronize the processing and display of multiple signals in near real-time. Signal path module 2602 solves this technological problem using a novel multistage process involving packetization, queueing, and processing delay equalization, as described below.
In a first stage, input module 2604 can receive signal samples for one or more base signals. A base signal can be a signal before any digital signal processing is applied. For example, a base signal can be a biomedical signal such as an ECG or IC signal. As would be appreciated by a person of ordinary skill in the art, a base signal can be various other types of signals. Input module 2604 can receive signal samples for multiple base signals. For example, input module 2604 can receive signal samples of an IC signal and signal samples of an ECG signal.
Input module 2604 can receive signal samples of a base signal from a hardware device associated with MSU (Hardware) 504 in
Input module 2604 can receive signal samples from a hardware device via A/D converter stage 534. For example, input module 2604 can receive signal samples of a base signal from EGG board 302.
Input module 2604 can receive signal samples of a base signal from an electrode attached to a hardware device. For example, input module 2604 can receive signal samples for each of eight (8) electrodes attached to ECG board 302. As would be appreciated by a person of ordinary skill in the art, input module 2604 can receive more or fewer signal samples depending on the number of hardware devices connected to input module 2604, and the number of electrodes attached to each hardware device.
Input module 2604 can store the one or more signal samples for each base signal in a computer storage device for later analysis by review module 2624. For example, input module 2604 can store the one or more signal samples in main memory 5008 or hard disk drive 5012 in
Input module 2604 can dispatch the one or more signal samples for each base signal to packetizer 2606. Packetizer 2606 can perform preprocessing on the received signal samples. Packetizer 2606 can perform preprocessing on the received signal samples to ensure that the resulting signal is compatible with later stages in signal path module 2602. As would be appreciated by a person of ordinary skill in the art, the type of preprocessing that packetizer 2606 performs can depend on the type of base signal. For example, packetizer 2606 can convert the binary values of the received signal samples to their corresponding physical values, e.g., for display of the base signal.
After preprocessing the received signal samples, packetizer 2606 can store the one or more signal samples of a base signal into a packet. A packet may be a consecutive sequence of N signal samples belonging to the same base signal. Packetizer 2606's storage of signal samples into packets can enable signal path module 2602 to synchronize the processing and displaying of multiple signals in near real-time, especially on a non-real-time operating system. In other words, a packet is the unit of processing in signal path module 2602.
Packetizer 2606 can store one or more signal samples in a packet based on timer 2605. Timer 2605 can be a high-resolution timer. For example, timer 2605 can be a Microsoft Windows® high-resolution timer having a 1-millisecond resolution. Timer 2605 can be set to an amount of time associated with receiving a fixed number of signal samples (e.g., N signal samples) from a hardware device or from a computer file. The fixed number of signal samples may correspond to the number of signal samples capable of being stored in a packet.
Packetizer 2606 can use timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, packetizer 2606 can set timer 2605 to an amount of time associated with receiving a given number of signal samples of a base signal. In other words, packetizer 2606 can expect to receive a certain number of signal samples when timer 2605 is triggered.
Packetizer 2606 can start timer 2605. Packetizer 2606 can then store signal samples received from input module 2604 into a packet until timer 2605 is triggered. Packetizer can then dispatch the packet to queuing module 2608. Packetizer 2606 can then restart timer 2605. Packetizer 2606 can then store a new set of signal samples received from input module 2604 into a new packet until timer 2605 is triggered again.
Packetizer 2606 can assign a tag to each packet. Packetizer 2606 can assign the same tag to each packet associated with a different base signal for the same period of time. This assignment can enable signal path module 2602 to synchronize the processing and displaying of packets for different base signals for the same period of time. The assigned tag may be used by a display module 2618 to synchronize the output of different signals. In other words, the display module 2618 can work on the same tag at any given time.
The assigned tag can correspond to the time period in which signal samples in the corresponding packet were received. Specifically, the tag can correspond to the sample number of the first signal sample in the corresponding packet. For example, packetizer 2606 can store sixteen (16) signal samples in each packet. In this case, packetizer 2606 can store the first set of signal samples in a packet with a tag of 0. Packetizer 2606 can store the second set of signal samples in a packet with a tag of 15. Packetizer 2606 can store the subsequent sets of signal samples in packets with tags of 31, 47, 64, etc. As would be appreciated by a person of ordinary skill in the art, other tag assignment conventions can be employed.
After packetization, packetizer 2606 can store each generated packet associated with a given base signal in queuing module 2608. Queueing module 2608 is shown in
Queuing module 2608 includes one or more queues 2702. For example, in
Packetizer 2606 can store each generated packet associated with a given base signal in a corresponding queue 2702. For example, packetizer 2606 can store generated packets associated with an IC signal into queue 2702-1, and generated packets associated with an ECG signal into queue 2702-2.
Packetizer 2606 can store each packet in a queue 2702 in the order generated. This can ensure that the signal samples in the generated packets are processed in the order they are received from the hardware device or from the computer file.
Returning to
Packet dispatcher 2610 can continuously scan the one or more queues 2702 in queuing module 2608. Each time packet dispatcher 2610 detects a new packet available in a queue 2702 in queuing module 2608, packet dispatcher 2610 can remove the new packet from the queue 2702. Packet dispatcher 2610 can then dispatch the new packet to one or more signal modules 2614 in global signal tables 2612 for digital signal processing. Packet dispatcher 2610 can dispatch the same packet to multiple signal modules 2614 so that the base signal can be simultaneously processed using different digital processing functions. Moreover, because packet dispatcher 2610 can dispatch packets from different queues 2702 to different signal modules 2614, different base signals can be simultaneously processed using different digital signal processing functions.
Packet dispatcher 2610 can dispatch a new packet from a queue 2702 to one or more signal modules 2614. Packet dispatcher 2610 can dispatch the new packet to one or more signal modules 2614 using global signals table 2612. Global signals table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal, and thus a given a queue 2702. For example, if there are 100 base signals, global signals table 2612 can be a fixed size array of 100 elements. Moreover, for each element of the array, there can be one or more signal modules 2614 designed to process the corresponding base signal. In some embodiments, each element of the array can be a fixed size array itself. Each element of this subarray can be associated with a given signal module 2614. For example, if there are 10 signal modules 2614, this subarray can contain 10 elements. Thus, by way of example and not limitation, global signals table 2612 can be a 100×10 array.
Packet dispatcher 2610 can dispatch the new packet to a signal module 2614 by checking the corresponding element in the subarray associated with the base signal of the new packet. Specifically, packet dispatcher 2610 can determine whether the corresponding element in the subarray indicates that the signal module 2614 is assigned to the base signal associated with the packet.
In some embodiments, global signals table 2612 can indicate whether a given signal module 2614 is assigned to a given base signal by storing a ‘0’ or ‘1’ at the corresponding element in the subarray associated with the given signal module 2614. For example, global signals table 2612 can indicate that the given signal module 2614 is not assigned to the given base signal by storing a ‘0’ at the corresponding element in the subarray. In some other embodiments, global signals table 2612 can indicate whether a given signal module 2614 is assigned to a given base signal by storing a reference to the given signal module 2614 at the corresponding element in the subarray. As would be appreciated by a person of ordinary skill in the art, the reference can be a memory pointer, flag, handle, or other type of identifier.
Packet dispatcher 2610 can also dispatch the new packet to one or more signal modules 2614 using a lookup table. The lookup table may map a given queue 2702 to one or more signal modules 2614. Packet dispatcher 2610 can dynamically determine which one or more signal modules 2614 are associated with a given queue 2702 using the lookup table. Packet dispatcher 2610 can then dispatch the packet to the one or more determined signal modules 2614 for digital signal processing.
Before packet dispatcher 2610 can begin dispatching packets to one or more signal modules 2614 for digital signal processing, configuration path module 2620 can configure signal path module 2602. Configuration path module 2620 can perform this configuration during initialization of system 2600, or when a user applies a new configuration to signal path module 2602. Configuration path module 2620 is shown in
Configuration path module 2620 includes a signal configuration module 2802, a signal factory module 2804, a digital signal processor (DSP) equalizer 2806, and a DSP factory module 2808. Configuration path module 2620 is a software module capable of being executed by a processor (or processors) such as processor 5004. Configuration path module 2620 controls the execution of signal factory module 2804, DSP equalizer 2806, and DSP factory module 2808. Signal factory module 2804, DSP equalizer 2806, and DSP factory module 2808 can be software modules capable of being executed by a processor (or processors) such as processor 5004.
During initialization of system 2600, or in response to a user applying a new configuration to system 2600, configuration path module 2620 can generate and configure one or more signal modules 2614 in global signals table 2612. In some embodiments, the execution of signal path module 2602 and monitoring module 2622 can be paused during the execution of configuration path module 2620.
Configuration path module 2620 includes signal configuration module 2802. Signal configuration module 2802 can receive one or more signal processing specifications. A signal processing specification can be used to generate and configure a signal module 2614. A signal processing specification may specify a base signal to process, the lengths of input and output packet queues for a signal module 2614, and a digital signal processing function to use to process the base signal. Signal configuration module 2802 can receive the one or more signal processing specifications from a computer file. The file may contain one or more signal processing specifications previously specified by a user. Signal configuration module 2802 can also receive a signal processing specification via a graphical user interface (GUI) in which a user manually enters the signal processing specification using a series of computer mouse, touch, keyboard, and/or voice recognition data entry techniques, as would be appreciated by a person of ordinary skill in the art.
In response to receiving one or more signal processing specifications, signal configuration module 2802 can forward the one or more signal processing specifications to signal factory module 2804. Signal factory module 2804 can generate a signal module 2614 based on a signal processing specification. For example, signal factory module 2804 can generate a signal module 2614 as shown in
Signal module 2614 includes input packet queue 2902, DSP 2904, and output packet queue 2906. Signal factory module 2804 can generate input packet queue 2902, DSP 2904, and output packet queue 2906 based on a signal processing specification from signal configuration module 2802. Input packet queue 2902 can store one or more packets from packet dispatcher 2610 for processing by DSP 2904. Input packet queue 2902 can be a queue data structure that stores items in the order that they are inserted. For example, the first item inserted into input packet queue 2902 is the first item removed from input packet queue 2902. In other words, input packet queue 2902 can be a first-in-first-out (FIFO) data structure. As would be appreciated by a person of ordinary skill in the art, input packet queue 2902 can be implemented using a linked list, an array, or various other data structure.
Output packet queue 2906 can store one or more packets processed by DSP 2904. Output packet queue 2906 can be a queue data structure that stores items in the order that they are inserted. For example, the first item inserted into output packet queue 2906 is the first item removed from output packet queue 2906. In other words, output packet queue 2906 can be a first-in-first-out (FIFO) data structure. As would be appreciated by a person of ordinary skill in the art, output packet queue 2906 can be implemented using a linked list, an array, or various other data structure.
Signal factory module 2804 can generate DSP 2904 based on a signal processing specification from signal configuration module 2802. Specifically, signal factory module 2804 can request DSP factory module 2808 to generate DSP 2904. DSP factory module 2808 can generate DSP 2904 based on a digital signal processing function specified in the signal processing specification. DSP factory module 2808 can further generate DSP 2904 based on one or more signal processing parameters associated with a digital processing function. For example, DSP factory module 2808 can generate DSP 2904 based on a low-pass filter function and a cutoff frequency specified in a signal processing specification.
A DSP 2904 is a software module capable of being executed by a processor (or processors) such as processor 5004 in
DSP 2904 can also apply a digital processing function that analyzes a signal for various characteristics. For example, DSP 2904 can apply a digital processing function that determines whether a noise anomaly or signal pattern is present in a signal. DSP 2904 can also analyze a signal by detecting repeated patterns in the signal. This may involve comparing the signal to a previously detected (or recorded or synthesized) signal pattern.
For example, DSP 2904 can determine a late potential in a signal. Specifically, DSP 2904 can determine a noise anomaly followed by subsequent noise anomalies occurring at the same time relative to a matched beat. Each subsequent noise anomaly at the same relative position can increase a confidence level that a late potential has been located. A display module 2618 can then display an indication of the late potential.
Similarly, DSP 2904 can determine an early activation in a signal. Specifically, DSP 2904 can determine an earliest sharp intracardiac signal above a selected threshold occurring within a predetermined segment before a reference point of a matched beat. A display module 2618 can then display an indication of the early activation.
DSP 2904 can detect a pattern in a signal using a correlation function. For example, DSP 2904 can detect a pattern using a mean absolute deviation algorithm. As would be appreciated by a person of ordinary skill in the art, DSP 2904 can use various other types of pattern matching algorithms.
DSP 2904 can detect a pattern based on various signal characteristics. For example, DSP 2904 can detect a pattern based on shape, amplitude, and time characteristics. As would be appreciated by a person of ordinary skill in the art, DSP 2904 can detect a pattern based on various other types of signal characteristics.
DSP 2904 can also include one or more signal processing parameters. The signal processing parameters may control how DSP 2904 applies its digital processing function. For example, DSP 2904 can include one or more signal processing parameters that specify a threshold frequency or an amplitude for filtering. DSP 2904 can also include one or more signal processing parameters that specify a signal pattern to detect, or a noise threshold value.
DSP 2904 can apply its digital processing function to a packet in input packet queue 2902. In some embodiments, DSP 2904 can scan input packet queue 2902 for a new packet to process. In some other embodiments, DSP 2904 can get a notification that a new packet is available in input packet queue 2902. DSP 2904 can then retrieve the packet from input packet queue 2902.
DSP 2904 can apply its digital processing function to the retrieved packet. In other words, DSP 2904 can apply its digital processing function to the one or more signal samples in the packet. DSP 2904 can control how it applies its digital processing function to the one or more signal samples in the packet based on its one or more signal processing parameters. After processing the packet, DSP 2904 can store the packet in output packet queue 2906 for display by output module 2616.
As discussed below, each DSP 2904 can have an associated processing delay. The processing delay can represent the amount of time to complete processing of a packet by the digital processing function of DSP 2904. The processing delay can vary between different DSPs 2904. This variance in processing delay between different DSPs 2904 can cause the DSPs 2904 to output packets for display at different times, as discussed below.
After signal factory module 2804 completes generating input packet queue 2902, DSP 2904, output packet queue 2906, signal factory module 2804 can connect the output of input packet queue 2902 to the input of DSP 2904, and the output of DSP 2904 to the input of output packet queue 2906. Once signal factory module 2804 completes the connection, DSP 2904 can receive packets from input packet queue 2902 representing an unprocessed base signal. DSP 2904 can then process the packets using its digital processing function. DSP 2904 can output the processed packets to output packet queue 2906. Signal factory module 2804 can further configure input packet queue 2902 to receive packets from the base signal specified in the signal processing specification.
Once the signal module 2614 is created, signal factory module 2804 can add it to global signals table 2612. As discussed above, global signals table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal. Moreover, each element of the array can be a fixed size array itself. Each element of this subarray can be associated with a given signal module 2614.
In some embodiments, signal factory module 2804 can add the created signal module 2614 to global signals table 2612 by adding a new array element to each subarray associated with a base signal. This new array element can correspond to the newly created signal module 2614. For example, if global signals table 2612 previously contained ten (10) signal modules 2614, the newly created signal module 2614 can be added at element number 11 in each subarray, for example.
Once the created signal module 2614 is added to global signals table 2612, a user (e.g., a physician) can assign the created signal module 2614 to a given base signal. In some embodiments, global signals table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a ‘0’ or ‘1’ at the corresponding element in the subarray associated with the created signal module 2614. In some other embodiments, global signals table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a reference to the created signal module 2614 at the corresponding element in the subarray.
Signal factory module 2804 can generate multiple signal modules 2614. Each signal module 2614 can have a DSP 2904 that applies a different digital signal processing function. As a result, each signal module 2614 can generate a different processed version of the same base signal. This can enable a user to analyze the same base signal in a variety of ways. A user may also want to analyze the time-aligned output of multiple versions of the same base signal. This can enable the user to compare different versions of the same signal at the same point in time or different points in time.
As noted above, conventional digital signal processing systems are often unable to synchronize the display of multiple processed signals in near real-time. This may be because different digital signal processing functions have different processing delays. For example, a current EP system may apply two different digital signal processing functions to the same base signal. But a medical team may want to synchronize the display of the two processed signals. For example, a medical team may want to compare an IC signal and an ECG signal at the same point in time in order to determine a clinical diagnosis. In other words, the medical team may want to time-align the display of the first processed signal with the display of the second processed signal in near real-time. But this may not be possible if the two different digital signal processing functions have different processing delays. This is because one of the digital signal processing functions may complete processing of the base signal more quickly than the other digital signal processing function. As a result, one processed signal may be displayed before the other processed signal.
The processing delay associated with a digital processing function may depend on the complexity of the function. For example, a digital processing function that performs low-pass filtering on a signal may be less computationally-intensive and use minimal memory. As a result, such a digital processing function may have a short processing delay. In contrast, another digital processing function may analyze a signal for particular signal characteristics. This type of digital processing function may be more computationally-intensive and use more memory, and therefore have a longer processing delay.
Because of the different processing delays, one processed signal may be displayed before another processed signal. This synchronization gap may become greater over time. For example, this synchronization gap may become greater where multiple signals are being processed and displayed in near real-time. This is because the difference in processing delay between two digital signal processing functions may be propagated to each new signal sample.
For example, a first digital signal processing function may have a processing delay of 10 milliseconds for a given base signal. A second digital signal processing function may have a processing delay of 20 milliseconds for the same base signal. The first digital signal processing function may complete processing of a first signal sample of the base signal at 10 milliseconds, and the second digital signal processing function may complete processing of the same first signal sample at 20 milliseconds. Thus, the first signal sample processed by the first digital signal processing function may be displayed at 10 milliseconds, and the first signal sample processed by the second digital signal processing function may be displayed at 20 milliseconds. In other words, the first signal sample processed by the first digital signal processing function may be displayed 10 milliseconds before the first signal sample processed by the second digital signal processing function.
This synchronization gap may increase when the second signal sample is processed. For example, the second signal sample may be received for processing by the first digital signal processing function at time 10 milliseconds, and the second signal sample may be received for processing by the second digital signal processing function at time 20 milliseconds. As a result, the second signal sample processed by the first digital signal processing function may be displayed at 20 milliseconds, and the second signal sample processed by the second digital signal processing function may be displayed at 40 milliseconds. In other words, the synchronization gap may increase by 10 milliseconds for the second signal sample; initially the synchronization gap is 10 milliseconds and subsequently the synchronization gap is 20 milliseconds.
This synchronization gap may increase where the digital signal processing is performed on a non-real-time operating system. Unlike a non-real-time operating system, a real-time operating system is a time bound system with well-defined fixed time constraints. A real-time operating system can guarantee that an application task is accepted and completed in a certain amount of time. In other words, a real-time operating system may provide a level of consistency concerning the amount of time it takes to complete a task.
In contrast, a non-real-time operating system cannot provide any guarantee that an application task is completed in a certain amount of time. For example, a non-real-time operating system may not provide a guarantee that the execution of a particular digital signal processing function is completed in a certain amount of time. As a result, there may be a high degree of variability concerning the amount of time it takes to complete a task. This may be problematic when attempting to synchronize the processing and display of multiple processed signals. This is because a processing delay associated with a digital processing function may vary with each execution. For example, a digital signal processing function may normally complete execution in 10 milliseconds. But on a non-real-time operating system, there may be no guarantee that the digital signal processing function completes execution after 10 milliseconds. For example, the digital signal processing function may complete execution in 30 milliseconds. This variability in processing delay may further increase the synchronization gap.
In some embodiments, this display synchronization problem is solved in a multipronged way using an input packet queue 2902 and an output packet queue 2906 of a signal module 2614, storing signal samples in a packet along with an associated tag, and equalizing the processing delays among one or more DSPs 2904.
An input packet queue 2902 and an output packet queue 2906 can solve the display synchronization problem in three ways. First, they ensure packets, and therefore signal samples, are processed and displayed sequentially. Second, an output packet queue 2906 can synchronize the display of packets at the same point in time by blocking the processing of more packets until existing packets are consumed by output module 2616. In other words, an output packet queue 2906 can provide a feedback mechanism to a DSP 2904 that indicates when the DSP 2904 can stop processing more packets. Finally, an input packet queue 2902 ensures a DSP 2904 has packets to process. For example, when an input packet queue 2902 is empty, a DSP 2904 can stop processing more packets. In other words, an input packet queue 2902 can provide a feedback mechanism to a DSP 2904 to indicate that there are no more packets to process.
DSP delay equalizer 2806 can also solve the display synchronization problem by equalizing processing delays across one or more DSPs 2904. As discussed above, different digital signal processing functions have different processing delays, which may cause the processed signals to be displayed out of sync. Therefore, if configuration path module 2620 generates multiple signal modules 2614, each with a DSP 2904 having a different digital signal processing function, each signal module 2614 can complete processing of a packet with a different processing delay. Because of these different processing delays, the processed signals may be displayed out of sync by output module 2616. DSP delay equalizer 2806 can solve this problem by equalizing the processing delays across the generated signal modules 2614.
In some embodiments, after configuration path module 2620 generates the one or more signal modules 2614, signal factory module 2804 can use DSP delay equalizer 2806 to equalize the processing delays of each generated signal module 2614 such that each signal module 2614 outputs a processed packet to its output packet queue 2906 at the same time. For example, DSP delay equalizer 2806 can determine the relative processing delay between two signal modules 2614. DSP delay equalizer 2806 can then use the determined relative delay to configure a DSP 2904 in the first signal module 2614 to complete processing of a packet at approximately the same time as a DSP 2904 in the second signal module 2614 is designed to complete processing of a packet.
In some embodiments, DSP delay equalizer 2806 can perform the equalization by scanning each generated signal module 2614. During the scan, DSP delay equalizer 2806 can request the processing delay associated with a DSP 2904 in each signal module 2614. DSP delay equalizer 2806 can request the processing delay using an application programming interface (API) of each signal module 2614. In response, each signal module 2614 can return its associated processing delay.
A signal module 2614 can store the processing delay associated with its DSP 2904. The processing delay may be a predefined value specified in the signal processing specification used to generate DSP 2904. In some other embodiments, DSP factory module 2808 can calculate the processing delay of a DSP 2904 based on various factors including the digital processing function used by the DSP 2904, the chosen signal processing parameters, and hardware characteristics such as the speed of the processor such as processor 5004, the size of the memory, and I/O latency.
After determining the processing delay associated with a DSP 2904 in each signal module 2614, DSP delay equalizer 2806 can determine the maximum processing delay among the signal modules 2614. For example, DSP delay equalizer 2806 can determine that signal module 2614-1 has a processing delay of 10 milliseconds, that signal module 2614-2 has a processing delay of 20 milliseconds, and that signal module 2614-N has a processing delay of 50 milliseconds. Based on this, DSP delay equalizer 2806 can determine that the maximum processing delay among the signal modules 2614 is 50 milliseconds.
After determining the maximum processing delay, DSP delay equalizer 2806 can configure the DSP 2904 of each signal module 2614 to have the maximum processing delay. For example, DSP delay equalizer 2806 can set the processing delay of the DSP 2904 of each signal module 2614 using an API. In response, each DSP 2904 can be designed to process a packet using its digital processing function and output the processed packet to its associated output packet queue 2906 at the end of the maximum processing delay. For example, in some embodiments, DSP 2904 can block its output to its output packet queue 2906 if it completes processing a packet prior to the end of the maximum processing delay. In some other embodiments, DSP 2904 can insert idle compute cycles during processing of a packet. As would be appreciated by a person of ordinary skill in the art, various other approaches may be used to cause DSP 2904 to output a processed packet to its output packet queue 2906 at the end of the maximum processing delay.
Packetization and the assignment of tags to packets can solve the display synchronization problem. As discussed above, each generated packet may include a fixed number of signal samples. Each packet may also include a tag indicating the packet's relative position among a sequence of packets. In order to synchronize the display of multiple signals, a display module 2618 can display packets having the same tag. In other words, the display module 2618 can synchronize its display using a tag.
As shown in
Each display module 2618 can display one or more signals. Each display module 2618 can receive a packet from an associated output packet queue 2906 in a signal module 2614 in global signals table 2612. Display module 2618 can display a signal based on the packet.
As discussed, a display module 2618 can receive a packet from an associated output packet queue 2906 in a signal module 2614. To receive the packet, display module 2618 can maintain a reference to the associated output packet queue 2906 in the signal module 2614. When a display module 2618 is designed to display multiple signals, the display module 2618 can maintain references to the output packet queues 2906 associated with each signal being displayed. The display module 2618 can store the references in its local signal table 3002. Local signal table 3002 can contain a list of one or more references to the output packet queues 2906 associated with each signal being displayed. The display module 2618 can remove a reference from its local signal table 3002 when the associated signal module 2614 is no longer active.
In some embodiments, a display module 2618 can continuously scan its one or more associated output packet queues 2906 for new packets. Where the display module 2618 is associated with a single output packet queue 2906, each time the display module 2618 detects a new packet, it may display the packet on a display device. However, where the display module 2618 is associated with multiple output packet queues 2906, the display module 2618 may not immediately display a new packet detected in a particular output packet queue 2906. This is because display module 2618 can be designed to synchronize the display of multiple signals.
In some embodiments, where a given display module 2618 is designed to synchronize the display of multiple signals, the display module 2618 can detect a new packet in a particular output packet queue 2906. The display module 2618 can then determine the tag associated with the new packet. The display module 2618 can use this determined tag to synchronize the display of new packets from the other output packet queues 2906. For example, display module 2618 can wait to display any packets to the display device until after detecting new packets at the other output packet queues 2906 that have the same determined tag. Once display module 2618 detects new packets having the same tag at its other associated output packet queues 2906, the display module 2618 can simultaneously display the packets from its associated output packet queues 2906. The display module 2618 can display the multiple signals in a non-overlapping stackable format. Because the display module 2618 can display packets having the same tag, the resulting displayed signals may be time-aligned.
A display module 2618 can maintain the current active tag to display in packet index 3004. Upon detecting a new packet in a particular output packet queue 2906, the display module 2618 can determine the tag of the new packet. Display module 2618 can then set packet index 3004 to the determined tag.
A display module 2618 can include display settings 3006. Display settings 3006 can include one or more parameters that control how display module 2618 displays its one or more associated signals. Display settings 3006 can specify colors to display the one or more associated signals. Display settings 3006 can specify a view format such as a waterfall view, dynamic view, or triggered view as discussed below. Display settings 3006 can specify a sweep speed for the one or more signals. Display settings 3006 can contain various other types of display settings as would be appreciated by a person of ordinary skill in the art. Display settings 3006 can be designed by a user as discussed below.
Review module 2624 can display one or more signals processed by one or more signal modules 2614 at a previous point in time. This can enable a user (e.g., a physician) to analyze the one or more signals long after they have been generated and displayed. In some embodiments, review module 2624 can capture a display of one or more signals in a display module 2618 in response to a command. For example, a user can click a button in a GUI to capture the current display of a display module 2618. The captured display can include the previously displayed visualization of the one or more signals at the time of capture. In some embodiments, the display module 2618 can pause its display of new packets in response to the capture of its current display.
In some embodiments, review module 2624 can capture the display of the one or more signals in the display module 2618 by determining a capture configuration of the display module 2618. The capture configuration can include the one or more active signals modules 2614 for the display module 2618, the capture time, the selected view for the display module 2618, the color scheme for the one or more displayed signals, and various other settings as would be appreciated by a person of ordinary skill in the art. After determining the capture configuration, review module 2624 can apply the capture configuration to previously stored signal samples.
As discussed above, input module 2604 can store one or more signal samples for each base signal in a storage for later analysis by review module 2624. Review module 2624 can capture a display of the one or more signals in the display module 2618 by applying the determined capture configuration to these stored signal samples. Specifically, review module 2624 can select the stored signal samples at the capture time in the capture configuration. Review module 2624 can then process the selected signal samples using the active signal modules 2614 in the capture configuration. Review module 2624 can also display the selected signal samples using the selected view, the color scheme, and various other settings in the capture configuration. Thus, review module 2624 can enable a user to review one or more processed signals for a display module 2618 at a particular point in time, and subject to a particular configuration.
In some embodiments, review module 2624 can enable a user to change the reviewed interval for a display module 2618. For example, the user can “rewind” to a different point in time in the past (e.g., 5 minutes ago). After the capture time is changed, review module 2624 can display the one or more processed signals for the display module 2618 at the new review time index.
Monitoring module 2622 can be continuously executed while signal path module 2602 is being executed. For example, monitoring module 2622 can be executed as a separate thread of execution by a processor. Monitoring module 2622 can determine whether there are issues in the execution of signal path module 2602.
In some embodiments, queue monitor 3102 can periodically scan queues in the signal path module 2602. For example, queue monitor 3102 can scan the queues 2702 in queuing module 2608. Queue monitor 3102 can also scan the input packet queues 2902 and the output packet queues 2906 in the one or more signal modules 2614. Queue monitor 3102 can determine the status of each queue during the scan. For example, queue monitor 3102 can determine the length of each queue during the scan. In some embodiments, if queue monitor 3102 determines a queue has an error status, queue monitor 3102 can request report module 3104 to display the error status on a display device. For example, queue monitor 3102 can determine that a queue's length is continuously increasing. In response, queue monitor 3102 can request report module 3104 to display an error that indicates that the particular queue has an incorrect length.
Live viewing area 3202 can contain the near real-time display of a display module 2618. In
Sweep speed 3204 can be a GUI widget that allows a user to select a sweep speed for live viewing area 3202. A sweep speed may represent a time scale of one or more signals displayed in live viewing area 3202. For example, the sweep speed may range from 10 mm per second to 1000 mm per second. In
Signal management window 3302 can include available signals 3304 and signal settings 3306. Available signals 3304 can contain one or more signals that can be selected for display by a display module 2618. For example, in
Signal settings 3306 can display various settings that can be set for each signal. For example, in
Live viewing area 3402 can contain the near real-time display of a display module 2618. In
Display settings window 3404 can include a zoom factor 3406 and a clip factor 3408. Zoom factor 3406 can be a GUI widget to select a zoom factor for a particular signal in live viewing area 3402. The selected zoom factor can increase or decrease the size of the particular signal. For example, zoom factor 3406 can increase the size of a particular signal from 0.02 to times 40.
Clip factor 3408 can be a GUI widget permitting a user to select a clip factor for a particular signal in live viewing area 3402. The selected clip factor can control how much a signal overshoots across the display screen. For example, a user can adjust the clip factor to reduce the actual area of where the particular signal is displayed so that if the particular signal is large, it does not extend beyond the whole display screen so as to be partially unviewable.
Live viewing area 3502 can contain the near real-time display of a display module 2618. Pattern search window 3504 can be a GUI window that enables a user to load or specify a signal pattern to search. For example, in
Live viewing area 3602 can contain the near real-time display of a display module 2618 subject to a late potential search. A user may create or load the search for the late potential as previously illustrated in
Live viewing area 3702 can contain the near real-time display of a display module 2618. Live viewing area 3702 can use a waterfall view to display the near real-time display of a display module 2618. In waterfall view, signals can be displayed side by side and vertically stacked on top of each other as a pattern is matched. Specifically, a user can select a pattern to match in a first signal (e.g., a specific beat pattern). When the pattern is detected in the first signal, display module 2618 can display a portion of the first signal that matches the pattern next to the corresponding portion of a second signal (e.g., an IC signal). The user can select the size of the portion of the first signal and the size of the portion of the second signal to be displayed. For example, the user can select the size of the portion of the first signal using a time interval (e.g., 150 milliseconds).
In waterfall view, each time the pattern is detected in the first signal, display module 2618 can vertically display each new portion of the first signal that matches the pattern along with the corresponding portion of the second signal. In other words, in waterfall view, display module 2618 can display signals along a vertical time axis.
In
A user (e.g., a physician) can find waterfall view advantageous. First, waterfall view enables a user to compare corresponding portions of two signals side by side. Second, waterfall view can display signals on a display screen longer because the signals are vertically stacked. In contrast, when signals are displayed left to right, it is often difficult for a user to analyze the signals because they are no longer displayed on the display screen after a short period of time.
In
For example, in
Live viewing area 3716 can contain the near real-time display of a display module 2618. Live viewing area 3716 can use a dynamic view to display the near real-time display of a display module 2618. In dynamic view, a user can select a trigger for a signal (e.g., a correlation with a stored beat). The user can select the trigger from a plurality of trigger types. A trigger type can be a signal characteristic of interest that is associated with a secondary event of interest. When the trigger occurs, display module 2618 can dynamically adjust the offset of the signal so that it is pinned to a baseline. This can prevent the signal from progressing off the display screen. This is often important in clinical settings where the height of a signal peak can indicate a particular type of injury, and a signal plateau can indicate the effectiveness of an ablation lesion, for example.
In
Live viewing area 3728 can contain the near real-time display of a display module 2618. In
In trigger view 3730, a user can also specify a time after the trigger occurs where data is pinned to the baseline. For example, in
Live viewing area 3802 can contain the near real-time display of a display module 2618. Review window 3804 can contain a previous display shown in live viewing area 3802. To capture the display of live viewing area 3802, a user may submit a capture request. For example, in
Live viewing area 3902 can contain the near real-time display of a display module 2618. Review window 3904 can contain a previously-captured display shown in live viewing area 3802. A user may analyze the previously-captured output in review window 3904 using vertical and horizontal calipers. Horizontal calipers can be a GUI selection widget. A user can use horizontal calipers to measure amplitude in millivolts (mV) for a particular signal. For example, as shown in
The following method descriptions for processing and displaying multiple signals in near-real time are provided for embodiments related to ECG and IC signal visualization. A person of ordinary skill in the art would understand that these methods can apply equally to visualization of other small physiologic signals.
Method 4000 shall be described with reference to
In 4002, configuration path module 2620 configures one or more signal modules 2614. 4002 can be performed by method 4100 in
In 4004, input module 2604 receives one or more signal samples for one or more signals. For example, input module 2604 can receive one or more signal samples for an IC signal, and one or more signal samples for an ECG signal. 4004 can be performed by method 4400 in
In 4006, input module 2604 dispatches the one or more signal samples to packetizer 2606.
In 4008, packetizer 2606 converts the one or more signal samples to one or more packets. 4008 can be performed by method 4500 in
In 4010, packetizer 2606 dispatches the one or more packets to queuing module 2608. 4010 can be performed by method 4600 in
In 4012, packet dispatcher 2610 dispatches a packet from queuing module 2608 to a signal module 2614 associated with the packet. 4012 can be performed by method 4700 in
In 4014, the signal module 2614 of 4012 processes the packet using a DSP 2904. 4014 can be performed by method 4800 in
In 4016, a display module 2618 associated with the signal module 2614 of 4012 displays the processed packet to a display screen. 4016 can be performed by method 4900 in
Method 4100 shall be described with reference to
In 4102, signal configuration module 2802 can receive one or more signal processing specifications. A signal processing specification may specify a base signal to process, the lengths of input and output packet queues for a signal module 2614, a digital signal processing function to process the base signal, and one or more associated parameters for the digital signal processing function. In some embodiments, signal configuration module 2802 can receive a signal processing specification from a file stored in memory. In some other embodiments, signal configuration module 2802 can receive a signal processing specification from a GUI that enables a user to manually enter the signal processing specification.
In 4104, signal configuration module 2802 dispatches the one or more signal processing specifications to signal factory module 2804.
In 4106, signal factory module 2804 generates a signal module 2614 for each signal processing specification. 4106 can be performed by method 4200 in
Method 4200 shall be described with reference to
In 4202, signal factory module 2804 generates an input packet queue 2902 of the signal module 2614 based on the signal processing specification in 4106 of
In 4204, signal factory module 2804 generates an output packet queue 2906 of the signal module 2614 based on the signal processing specification. For example, signal factory module 2804 generates an output packet queue 2806 by creating a queue data structure of the length specified in the signal processing specification.
In 4206, signal factory module 2804 generates a DSP 2904 of the signal module 2614 using DSP factory module 2808 based on the signal processing specification. Specifically, signal factory module 2804 can request DSP factory module 2808 to generate the DSP 2904 based on the digital processing function and one or more signal processing parameters specified in the signal processing specification. For example, DSP factory module 2808 can generate DSP 2904 based on a low-pass filter function and a specific cutoff frequency specified in the signal processing specification.
In 4207, signal factory module 2804 connects the generated input packet queue 2902, the generated DSP 2904, and the generated output packet queue 2906 of the signal module 2614. Specifically, signal factory module 2804 connects the output of the input packet queue 2902 to the input of DSP 2904. Signal factory module 2804 further connects the output of DSP 2904 to the input of output packet queue 2906.
In 4210, signal factory module 2804 configures input packet queue 2902 to receive packets dispatched from packet dispatcher 2610. In some embodiments, signal factory module 2804 can add a rule to a lookup table associated with packet dispatcher 2610. The rule may specify that packets associated with a given signal can be processed by a given signal module 2614.
In 4212, signal factory module 2804 uses DSP delay equalizer 2806 to equalize the associated processing delays of each generated signal module 2614 such that each signal module 2614 outputs a processed packet to its output packet queue 2906 at the same time. 4210 can be performed by method 4300 in
Method 4300 shall be described with reference to
In 4302, DSP delay equalizer 2806 requests the processing delay associated with each DSP 2904 of the one or more signal modules 2614. DSP delay equalizer 2806 can request the processing delay of a DSP 2904 using an API of its associated signal module 2614.
In 4304, DSP delay equalizer 2806 receives the processing delay of a DSP 2904 from each of the one or more signal modules 2614.
In 4306, DSP delay equalizer 2806 determines a maximum processing delay among the one or more received processing delays.
In 4308, DSP delay equalizer 2806 sets a DSP 2904 of each of the one or more signal modules 2614 to the maximum processing delay. For example, DSP delay equalizer 2806 can set the processing delay of a DSP 2904 of each signal module 2614 using an API. In response, each DSP 2904 can be designed to process a packet using its digital processing function and output the processed packet to output packet queue 2906 at the end of the maximum processing delay. In some embodiments, a DSP 2904 can block its output to output packet queue 2906 if it completes processing a packet using its digital processing function prior to the end of the maximum processing delay.
Method 4400 shall be described with reference to
In 4402, input module 2604 receives signal samples for a base signal from a hardware device (e.g., an electrode attached to a patient) or data stored in a computer file. For example, the computer file may contain a previously recorded session of signal samples received from a hardware device. As would be appreciated by a person of ordinary skill in the art, input module 2604 can simultaneously receive signal samples for multiple based signals.
In 4404, input module 2604 dispatches the received signal samples to packetizer 2606.
Method 4500 shall be described with reference to
In 4502, packetizer 2606 receives one or more signal samples from input module 2604.
In 4504, packetizer 2606 can optionally preprocess the one or more signal samples. For example, packetizer 2606 can convert the binary values of the one or more signal samples to their corresponding physical values. As would be appreciated by a person of ordinary skill in the art, packetizer 2606 can perform various other types of preprocessing.
In 4506, packetizer 2606 generates a packet containing the one or more signal samples for a given base signal. Packetizer 2606 can store a predefined number of signal samples in the packet. In some embodiments, packetizer 2606 can use timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, packetizer 2606 can store signal samples received from input module 2604 into the packet until timer 2605 is triggered.
In 4508, packetizer 2606 assigns a tag to the generated packet. The tag may correspond to a time period in which the one or more signal samples in the packet were received. Packetizer 2606 can assign a new tag to each subsequent packet. For example, packetizer 2606 can first generate a packet containing sixteen (16) signal samples for a given base signal. In this case, packetizer 2606 can store the first set of signal samples in a packet with a tag of 0. Packetizer 2606 can store the second set of signal samples in a packet with a tag of 15. Packetizer 2606 can store the subsequent sets of signal samples in packets with tags of 31, 47, 64, etc.
Method 4600 shall be described with reference to
In 4602, packetizer 2606 determines a base signal associated with a newly generated packet.
In 4604, packetizer 2606 determines a queue 2702 in queuing module 2608 associated with the determined base signal. Packetizer 2606 can determine that a queue 2702 is associated with the determined base signal using a lookup table.
In 4606, packetizer 2606 dispatches the packet containing the one or more signal samples to the determined queue 2702.
Method 4700 shall be described with reference to
In 4702, packet dispatcher 2610 continuously scans a queue 2702 in queueing module 2608.
In 4704, packet dispatcher 2610 detects a new packet in the queue 2702.
In 4706, packet dispatcher 2610 determines one or more signal modules 2614 in global signals table 2612 that are designed to process the new packet. Because the new packet can be dispatched to multiple signal modules 2614 (e.g., multiple copies or “instances” of the packet), the base signal associated with the packet can be simultaneously processed using different digital processing functions of the signal modules 2614.
In some embodiments, packet dispatcher 2610 can determine one or more signal modules 2614 that are designed to process an instance of the new packet using global signals table 2612. For example, global signals table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal, and thus a given a queue 2702. Moreover, each element of the array can be a fixed size array itself. Each element of this subarray can be associated with a given signal module 2614. Thus, packet dispatcher 2610 can determine one or more signal modules 2614 that are designed to process the new packet by checking the corresponding element in the subarray associated with the base signal of the new packet.
In some other embodiments, packet dispatcher 2610 can determine the one or more signal modules 2614 that are designed to process the new packet using a lookup table. Specifically, the lookup table may map the queue 2702 to one or more signal modules 2614.
In 4706, packet dispatcher 2610 dispatches the new packet to the determined one or more signal modules 2614 in global signals tables 2612 for processing. Specifically, packet dispatcher 2610 inserts the new packet into the input packet queues 2902 of the determined one or more signal modules 2614.
Method 4800 shall be described with reference to
In 4802, DSP 2904 detects whether a new packet is available in the input packet queue 2902 of the signal module 2614. In some embodiments, DSP 2904 can scan the input packet queue 2902 for a new packet to process. In some other embodiments, DSP 2904 can get a notification that a new packet is available in the input packet queue 2902.
In 4804, DSP 2904 retrieves the new packet from input packet queue 2902 of the signal module 2614.
In 4806, DSP 2904 processes the new packet using its associated digital signal processing function. Specifically, DSP 2904 can apply its digital processing function to the one or more signal samples in the packet. In some embodiments, DSP 2904 can control how it processes the packet using its digital processing function based on one or more signal processing parameters designed for DSP 2904.
In 4808, DSP 2904 outputs the processed packet to output packet queue 2906. In some embodiments, DSP 2904 can output the processed packet to output packet queue 2906 based on its designed maximum processing delay.
Method 4900 shall be described with reference to
In 4902, display module 2618 determines what one or more signal modules 2614 from which to display processed packets. In some embodiments, display modules 2618 can determine what one or more signal modules 2614 to display processed packets from by maintaining references to the output packet queues 2906 of the one or more signal modules 2614. Display module 2618 can store the references in local signal table 3002.
In 4904, display module 2618 detects that a new packet is available in an output packet queue 2906 of one of the determined signal modules 2614.
In 4906, display module 2618 receives the new packet from the output packet queues 2906 of the one of the determined signal modules 2614.
In 4908, display module 2618 determines a tag associated with new packet.
In 4910, display module 2618 receives new packets from the other output packet queues 2906 that match the determined tag.
In 4912, display module 2618 simultaneously displays the received new packets for one or more signal modules to a display screen. Because display module 2618 displays new packets having the same tag, display module 2618 synchronizes the display of the signals associated with the new packets.
Methods 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900 can be performed by processing logic that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executing on a processing device), or a combination thereof. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown in
Various embodiments can be implemented, for example, using one or more well-known computer systems, such as computer system 5000 shown in
Computer system 5000 can include one or more processors (also called central processing units, or CPUs), such as a processor 5004. Processor 5004 can be connected to a communication infrastructure or bus 5006.
Computer system 5000 can also include user input/output device(s) 5003, such as monitors, keyboards, pointing devices, etc., which can communicate with communication infrastructure 5006 through user input/output interface(s) 5002.
One or more of processors 5004 can be a graphics processing unit (GPU). In an embodiment, a GPU can be a processor that is a specialized electronic circuit designed to process mathematically intensive applications. The GPU can have a parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common to computer graphics applications, images, videos, etc.
Computer system 5000 can also include a main or primary memory 5008, such as random access memory (RAM). Main memory 5008 can include one or more levels of cache. Main memory 5008 can have stored therein control logic (e.g., computer software) and/or data.
Computer system 5000 can also include one or more secondary storage devices or memory 5010. Secondary memory 5010 can include, for example, a hard disk drive 5012 or a removable storage device or drive 5014. Removable storage drive 5014 can be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, tape backup device, or any other storage device/drive.
Removable storage drive 5014 can interact with a removable storage unit 5018. Removable storage unit 5018 can include a computer usable or readable storage device having stored thereon computer software (control logic) or data. Removable storage unit 5018 can be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, or any other computer data storage device. Removable storage drive 5014 can read from or write to removable storage unit 5018.
Secondary memory 5010 can include other means, devices, components, instrumentalities, or other approaches for allowing computer programs or other instructions or data to be accessed by computer system 5000. Such means, devices, components, instrumentalities, or other approaches can include, for example, a removable storage unit 5022 and an interface 5020. Examples of the removable storage unit 5022 and the interface 5020 can include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, or any other removable storage unit and associated interface.
Computer system 5000 can further include a communication or network interface 5024. Communication interface 5024 can enable computer system 5000 to communicate and interact with any combination of external devices, external networks, external entities, etc. (individually and collectively referenced by reference number 5028). For example, communication interface 5024 can allow computer system 5000 to communicate with external or remote devices 5028 over communications path 5026, which can be wired or wireless (or a combination thereof), and which can include any combination of LANs, WANs, the Internet, etc. Control logic or data can be transmitted to and from computer system 5000 via communications path 5026.
Computer system 5000 can also be any of a personal digital assistant (PDA), desktop workstation, laptop or notebook computer, netbook, tablet, smart phone, smart watch or other wearable, appliance, part of the Internet-of-Things, or embedded system, to name a few non-limiting examples, or any combination thereof.
Computer system 5000 can be a client or server, accessing or hosting any applications or data through any delivery paradigm, including but not limited to remote or distributed cloud computing solutions; local or on-premises software (“on-premise” cloud-based solutions); “as a service” models (e.g., content as a service (CaaS), digital content as a service (DCaaS), software as a service (SaaS), managed software as a service (MSaaS), platform as a service (PaaS), desktop as a service (DaaS), framework as a service (FaaS), backend as a service (BaaS), mobile backend as a service (MBaaS), infrastructure as a service (IaaS), etc.); or a hybrid model including any combination of the foregoing examples or other services or delivery paradigms.
Any applicable data structures, file formats, and schemas in computer system 5000 can be derived from standards including but not limited to JavaScript Object Notation (JSON), Extensible Markup Language (XML), Yet Another Markup Language (YAML), Extensible Hypertext Markup Language (XHTML), Wireless Markup Language (WML), MessagePack, XML User Interface Language (XUL), or any other functionally similar representations alone or in combination. Alternatively, proprietary data structures, formats or schemas can be used, either exclusively or in combination with known or open standards.
In some embodiments, a tangible, non-transitory apparatus or article of manufacture including a tangible, non-transitory computer useable or readable medium having control logic (software) stored thereon can also be referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 5000, main memory 5008, secondary memory 5010, and removable storage units 5018 and 5022, as well as tangible articles of manufacture embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system 5000), can cause such data processing devices to operate as described herein.
Based on the teachings contained in this disclosure, it will be apparent to persons skilled in the relevant art how to make and use embodiments of this disclosure using data processing devices, computer systems, or computer architectures other than that shown in
The EP recording system disclosed herein effectively removes noise and removes or isolates unwanted large signals while preserving relevant components of raw small signals, that is, while preserving integrity of original information in an EP environment. Conventional EP systems can successfully filter out noise but may also filter out signal components with the noise that a medical team desires to see. Conventional EP systems can also generate and introduce additional noise and unwanted artifacts not originally present in the raw signals with well-meaning software filtering algorithms. Even when conventional EP systems utilize state-of-the-art noise reduction practices, conventional EP systems cannot effectively collect clean small signals with high confidence in the presence of simultaneous large-signal procedures such as defibrillation and ablation. This is because conventional EP systems do not have a comprehensive signal acquisition and filtering solution across the relevant frequency ranges—low (e.g., 0 to 100 Hz), mid (e.g., above 100 Hz to below 300 kHz), and high (e.g., above and including 300 kHz)—and cannot effectively handle simultaneous signals that differ by 100s or 1000s of orders of magnitude. In comparison, the EP recording system disclosed herein integrates and applies novel hardware circuitry, software methods, and system topologies to remove unwanted signals but preserve original signal waveforms across the relevant frequencies for signals found in an EP environment.
The disclosed EP system does not have to make tradeoffs that conventional EP systems have to make. Rather, the disclosed EP system allows aspects of hardware and software to perform in tandem, in order to simultaneously: (1) run amplifiers at high gain to see small signals, (2) prevent both clipping and saturation by minimizing destructive large-signal filtering in hardware to see the large signals at the same time, (3) process the signals, separating them from each other in independent displays, removing any remaining noise, and synchronizing separated signals, and finally (4) enable a user to manipulate and analyze both large and small signals so that signal artifacts and events can be accurately time-and-event correlated.
The exemplary signals 2200 of
It is to be appreciated that the Detailed Description section, and not any other section, is intended to be used to interpret the claims. Other sections can set forth one or more but not all exemplary embodiments as contemplated by the inventor(s), and thus, are not intended to limit this disclosure or the appended claims in any way.
While this disclosure describes exemplary embodiments for exemplary fields and applications, it should be understood that the disclosure is not limited thereto. Other embodiments and modifications thereto are possible, and are within the scope and spirit of this disclosure. For example, and without limiting the generality of this paragraph, embodiments are not limited to the software, hardware, firmware, or entities illustrated in the figures or described herein. Further, embodiments (whether or not explicitly described herein) have significant utility to fields and applications beyond the examples described herein.
Embodiments have been described herein with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined as long as the specified functions and relationships (or equivalents thereof) are appropriately performed. Also, alternative embodiments can perform functional blocks, steps, operations, methods, etc. using orderings different than those described herein. This disclosure also extends to methods associated with using or otherwise implementing the features of the disclosed hardware and systems herein.
References herein to “one embodiment,” “an embodiment,” “an exemplary embodiment,” or similar phrases, indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment cannot necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of persons skilled in the relevant art to incorporate such feature, structure, or characteristic into other embodiments whether or not explicitly mentioned or described herein. Additionally, some embodiments can be described using the expression “coupled” and “connected,” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments can be described using the terms “connected” or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
The breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims
1. A circuit for processing an electrical signal having a large differential voltage offset, comprising:
- a first operational amplifier having a differential input and a differential output, and configured to receive the electrical signal at the differential input;
- a second operational amplifier having a common mode voltage input and configured to output a common mode reference voltage to a common mode node;
- a first pair of diode stages coupled between respective ones of the differential outputs of the first operational amplifier and respective ones of a first differential node and a second differential node;
- a plurality of timing banks coupled between the respective ones of the first differential node and the second differential node and the common mode node; and
- a second pair of diode stages coupled between the respective ones of the first differential node and the second differential node and the common mode node, and
- wherein the circuit is configured to attenuate the large differential voltage offset and output a compensating electrical signal at an output of each of the second pair of diode stages.
2. The circuit of claim 1, wherein the first pair of diode stages limits charging of the plurality of timing banks in response to respective voltage outputs of the differential output of the first operational amplifier being less than a breakdown voltage of a diode in the first pair of diode stages.
3. The circuit of claim 1, wherein:
- the first operational amplifier has a gain;
- each diode of the first pair of diode stages has a first breakdown voltage;
- the plurality of timing banks comprises a resistor-capacitor network, configured to set a plurality of time constants;
- the second pair of diode stages has a second breakdown voltage; and
- in response to the large differential voltage offset being above an activation threshold for a first duration of time at least as long as a time constant from the plurality of time constants, the circuit is configured to:
- amplify the large differential voltage offset with the gain to output respective voltages at respective outputs of the differential output, wherein the respective voltages are greater than the first breakdown voltage;
- charge the plurality of timing banks with respective attenuated voltages for a second duration of time equal to at least the time constant, wherein the respective attenuated voltages are the respective voltages attenuated by the first breakdown voltage;
- in response to charging the plurality of timing banks, generate a first voltage difference between the first differential node and the common mode node and a second voltage difference between the second differential node and the common mode node such that the first voltage difference and the second voltage difference are greater than the second breakdown voltage; and
- attenuate the large differential voltage offset by pulling an output voltage at the output of each of the second pair of diode stages towards the common mode reference voltage.
4. The circuit of claim 3, wherein each time constant of the plurality of time constants is 2 milliseconds to 10 milliseconds.
5. The circuit of claim 3, wherein the activation threshold is 100 mV.
6. The circuit of claim 3, wherein the activation threshold is determined by the gain of the first operational amplifier.
7. The circuit of claim 6, wherein the gain of the first operational amplifier is about 40.
8. The circuit of claim 1, wherein a breakdown voltage of one or more diodes in the second pair of diode stages sets an activation threshold and wherein the second pair of diode stages is configured to limit attenuation of the large differential voltage offset through the second pair of diode stages from the first differential node and the second differential node in response to respective voltages at the first and second differential nodes being less than the activation threshold.
9. The circuit of claim 1, wherein the first operational amplifier has a gain and the first pair of diode stages has a breakdown voltage, the gain and the breakdown voltage setting an activation threshold, and wherein, in response to the large differential voltage offset being less than the activation threshold, the first pair of diode stages limits charging of the plurality of timing banks.
10. The circuit of claim 1, wherein a breakdown voltage of the first pair of diode stages and a gain of the first operational amplifier set an activation threshold and wherein, in response to the large differential voltage offset being greater than the activation threshold, the circuit is configured to pull a respective voltage at the output of each of the second pair of diode stages toward the common mode reference voltage of the common mode node.
11. The circuit of claim 1, wherein the second pair of diode stages disconnects an output of the circuit to a system in response to the large differential voltage offset being below an activation threshold.
12. The circuit of claim 1, wherein a breakdown voltage of one or more diodes of the second pair of diode stages sets an activation threshold and wherein the circuit is configured to, in response to a voltage difference across the plurality of timing banks being greater than the activation threshold, limit a saturation duration of the large differential voltage offset to shorter than a saturation recovery time.
13. The circuit of claim 12, wherein the saturation recovery time is less than 100 milliseconds.
Type: Application
Filed: Feb 28, 2023
Publication Date: Aug 3, 2023
Applicant: BioSig Technologies, Inc. (Westport, CT)
Inventors: Budimir S. DRAKULIC (Los Angeles, CA), Sina Fakhar (Encino, CA), Thomas G. Foxall (Surrey), Branislav Vlajinic (Los Angeles, CA)
Application Number: 18/115,203
