SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of International Patent Application No. PCT/JP2023/014850, filed on Apr. 12, 2023, which claims the benefit of priority to Japanese Patent Application No. 2022-085858, filed on May 26, 2022, the entire contents of which are incorporated herein by reference.

FIELD

An embodiment of the present invention relates to a semiconductor device. In particular, an embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel.

BACKGROUND

In recent years, instead of a silicon semiconductor layer using amorphous silicon, low-temperature polysilicon, and single-crystal silicon, a semiconductor device in which an oxide semiconductor layer is used for a channel has been developed (for example, see Japanese laid-open patent publication Nos. 2021-141338, 2014-099601, 2021-153196, 2018-006730, 2016-184771, and 2021-108405). The semiconductor device including an oxide semiconductor layer can be manufactured with a simple structure and low-temperature process, similar to a semiconductor device including an amorphous silicon layer. Further, the semiconductor device including an oxide semiconductor layer is known to have higher mobility than the semiconductor device including an amorphous silicon layer.

It is essential to supply oxygen to an oxide semiconductor layer in the manufacturing process and to reduce the oxygen deficiencies formed in the oxide semiconductor layer in order for the semiconductor device in which the oxide semiconductor is used for the channel to perform a stable operation. For example, a technique for forming an insulating layer covering the oxide semiconductor layer under the condition that the insulating layer contains more oxygen is disclosed as one method of supplying oxygen to the oxide semiconductor layer.

SUMMARY

A semiconductor device according to an embodiment of the present invention includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view illustrating a crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view illustrating a crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 15 is a plan view showing an overview of a display device according to an embodiment of the present invention.

FIG. 16 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.

FIG. 17 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

FIG. 18 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention.

FIG. 19 is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention.

FIG. 20 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

FIG. 21 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention.

FIG. 22 is a graph showing electrical characteristics of a semiconductor device of an Example.

FIG. 23 is a graph showing a reliability test of the semiconductor device of an Example.

FIG. 24A is a cross-sectional TEM image of a semiconductor device of an Example.

FIG. 24B is a schematic diagram for explaining the cross-sectional TEM image of FIG. 24A.

FIG. 25 is an electron beam diffraction image of a semiconductor device of an Example.

FIG. 26 is an electron beam diffraction image of a semiconductor device of an Example.

FIG. 27 is a graph showing electrical characteristics of a semiconductor device of a Comparative Example.

FIG. 28 is a graph showing a reliability test of a semiconductor device of a Comparative Example.

FIG. 29 is a cross-sectional TEM image of a semiconductor device of a Comparative Example.

FIG. 30 is an electron beam diffraction image of a semiconductor device of a Comparative Example.

FIG. 31 is an electron beam diffraction image of a semiconductor device of a Comparative Example.

DESCRIPTION OF EMBODIMENTS

An insulating layer formed with more oxygen-containing conditions contains more defects. In this case, since electrons are trapped in the defects in the insulating layer, a variation in electrical characteristics or characteristics in reliability tests of the semiconductor device occurs. On the other hand, since an insulating layer with few defects does not contain much oxygen, oxygen cannot be sufficiently supplied from the insulating layer to the oxide semiconductor layer. Therefore, there is a demand for realizing a structure capable of repairing oxygen deficiencies formed in the oxide semiconductor layer while reducing defects in the insulating layer that cause the variation in characteristics of the semiconductor device.

Further, it is well-known that a semiconductor device with high mobility can be obtained by relatively increasing the ratio of indium contained in the oxide semiconductor layer. However, when the ratio of indium contained in the oxide semiconductor layer is high, oxygen deficiencies are likely to be formed in the oxide semiconductor layer. Therefore, in order to realize high mobility while maintaining high reliability, it is necessary to devise a configuration of the oxide semiconductor layer and the insulating layer around the oxide semiconductor layer.

An embodiment of the present invention can provide a semiconductor device with high mobility and high reliability.

Hereinafter, embodiments of the present invention are described with reference to the drawings. The following invention is merely an example. A configuration that can be easily conceived by a person skilled in the art by appropriately changing the configuration of the embodiment while keeping the gist of the invention is naturally included in the scope of the present invention.

In order to make the description clearer, the drawings may schematically show the widths, thicknesses, shapes, and the like of components in comparison with the actual embodiments. However, the illustrated shapes are merely examples, and do not limit the interpretation of the present invention. In the present specification and the drawings, the same reference signs are given to components similar to those described previously with respect to the above-described drawings, and detailed description thereof may be omitted as appropriate.

In the present specification and the like, a direction from a substrate toward an oxide semiconductor layer is referred to as “on” or “over” in each embodiment of the present invention. Conversely, a direction from the oxide semiconductor layer to the substrate is referred to as “under” or “below.” For convenience of explanation, the phrase “over” or “below” is used for description, but for example, the substrate and the oxide semiconductor layer may be arranged so that the vertical relationship is reversed from that shown in the drawings. Further, the expression “an oxide semiconductor layer on a substrate” merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and another member may be arranged between the substrate and the oxide semiconductor layer. The terms “over” or “below” mean a stacking order in which a plurality of layers is stacked, and may have a positional relationship in which a semiconductor device and a pixel electrode do not overlap in a plan view when expressed as “a pixel electrode over a semiconductor device.” On the other hand, the expression “a pixel electrode vertically over a semiconductor device” means a positional relationship in which the semiconductor device and the pixel electrode overlap in a plan view. In addition, a plan view refers to viewing from a direction perpendicular to a surface of the substrate.

In the present specification and the like, a “display device” refers to a structure that displays an image using an electro-optic layer. For example, the term “display device” may refer to a display panel that includes the electro-optic layer, or may refer to a structure with other optical members (for example, a polarized member, a backlight, a touch panel, and the like) attached to a display cell. The “electro-optic layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer, as long as there is no technical contradiction. Therefore, although a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified as a display device in the following embodiments, the structure according to the present embodiment can be applied to a display device including the other electro-optic layers described above.

In the present specification and the like, the expression “α includes A, B, or C,” “α includes any of A, B, or C,” “α includes one selected from a group consisting of A, B and C,” and the like does not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Further, these expressions do not exclude the case where a includes other components. In addition, the following embodiments can be combined with each other as long as there is no technical contradiction.

First Embodiment

A semiconductor device 10 according to an embodiment of the present invention is described with reference to FIGS. 1 to 14. For example, the semiconductor device 10 of the embodiment described below may be used in an integrated circuit (IC) such as a micro-processing unit (MPU) or a memory circuit in addition to a transistor used in a display device.

[Configuration of Semiconductor Device 10]

A configuration of the semiconductor device 10 according to an embodiment of the present invention is described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view showing a configuration of the semiconductor device 10 according to an embodiment of the present invention. Further, FIG. 2 is a plan view showing a configuration of the semiconductor device 10 according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor device 10 is arranged over a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. In addition, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be referred to as a source-drain electrode 200.

The gate electrode 105 is provided over the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided over the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided over the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided over the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. In main surfaces of the oxide semiconductor layer 140, a surface in contact with the metal oxide layer 130 is referred to as a lower surface 142. A side surface of the metal oxide layer 130 is substantially aligned with a side surface of the oxide semiconductor layer 140.

In the present embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100.

In FIG. 1, although the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are arranged in a straight line, the configuration is not limited thereto. An angle of the side surface of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from an angle of the side surface of the oxide semiconductor layer 140 with respect to the main surface. The side surface of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. In the main surfaces of the oxide semiconductor layer 140, a surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. A surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided over the gate insulating layer 150 and the gate electrode 160. Openings 171 and 173 that reach the oxide semiconductor layer 140 are provided in the insulating layers 170 and 180. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

The gate electrode 105 has a function as a bottom-gate of the semiconductor device 10 and a function as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities that diffuse from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom-gate. The metal oxide layer 130 is a layer that contains a metal oxide containing aluminum as the main component, and has a function as a gas barrier film for shielding a gas such as oxygen or hydrogen.

The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 vertically below the gate electrode 160. The source region S is a region of the oxide semiconductor layer 140 that does not overlap the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The channel region CH in the oxide semiconductor layer 140 has physical properties of a semiconductor. The source region S and the drain region D in the oxide semiconductor layer 140 have physical properties of a conductor.

The gate electrode 160 has a function as a top-gate of the semiconductor device 10 and a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has a function as a gate insulating layer for the top-gate, and has a function of releasing oxygen by a heat treatment in a manufacturing process. The insulating layers 170 and 180 insulate the gate electrode 160 and the source-drain electrode 200 and have a function of reducing parasitic capacitance therebetween. Operations of the semiconductor device 10 are controlled mainly by a voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case of using the gate electrode 105 simply as a light-shielding film, a specific voltage is not supplied to the gate electrode 105, and the gate electrode 105 may be in a floating state. That is, the gate electrode 105 may simply be referred to as a “light-shielding film.”

In the present embodiment, although a configuration using a dual-gate transistor in which the gate electrode is provided both over and below the oxide semiconductor layer as the semiconductor device 10 is exemplified, the configuration is not limited thereto. For example, a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer or a top-gate transistor in which the gate electrode is provided only over the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

As shown in FIG. 2, in a plan view, a planar pattern of the metal oxide layer 130 is substantially the same as a planar pattern of the oxide semiconductor layer 140. Referring to FIGS. 1 and 2, the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In particular, in the present embodiment, the whole of the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In a direction D1, a width of the gate electrode 105 is greater than a width of the gate electrode 160. The direction D1 is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating a channel length L of the semiconductor device 10. Specifically, a length in the direction D1 in the region (the channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap each other is the channel length L, and a width in a direction D2 in the channel region CH is a channel width W.

In the present embodiment, although a configuration in which all of the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130 is exemplified, the present invention is not limited thereto. For example, a part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the whole of the lower surface 142 of the channel region CH in the oxide semiconductor layer 140 may be covered with the metal oxide layer 130, and the whole or parts of the lower surface 142 of the source region S and the drain region D in the oxide semiconductor layer 140 may not be covered with the metal oxide layer 130. That is, the whole or parts of the lower surface 142 of the source region S and the drain region D in the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. However, in the above configuration, a part of the lower surface 142 of the channel region CH in the oxide semiconductor layer 140 may not be covered with the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.

In the present embodiment, although the configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150 is exemplified, the configuration is not limited thereto. The gate insulating layer 150 may be patterned. For example, the gate insulating layer 150 may be patterned to expose the whole or part of the source region S and the drain region D of the oxide semiconductor layer 140. That is, the gate insulating layer 150 on the source region S and the drain region D may be removed, and the source region S and the drain region D and the insulating layer 170 may be in contact with each other.

In FIG. 2, although the configuration in which the source-drain electrode 200 does not overlap the gate electrode 105 and the gate electrode 160 in a plan view is exemplified, the configuration is not limited thereto. For example, in a plan view, the source-drain electrode 200 may overlap at least one of the gate electrode 105 and the gate electrode 160. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[Material of Each Member of Semiconductor Device 10]

A rigid substrate having translucency, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like, is used as the substrate 100. In the case where the substrate 100 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acryl substrate, a siloxane substrate, or a fluororesin substrate is used as the substrate 100. In the case where the substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100. In particular, in the case where the semiconductor device 10 is a top-emission display, since the substrate 100 does not need to be transparent, impurities that reduce the translucency of the substrate 100 may be used. In the case where the semiconductor device 10 is used for an integrated circuit that is not a display device, a substrate without translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless substrate is used as the substrate 100.

Common metal materials are used for the gate electrode 105, the gate electrode 160, and the source-drain electrode 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof are used for the gate electrode 105, the gate electrode 160, and the source-drain electrode 200. The above-described materials may be used in a single layer or in a stacked layer for the gate electrode 105, the gate electrode 160, and the source-drain electrode 200.

In addition, the gate electrode 160 and the source/drain electrodes 200 may be made of the same metal material or different metal materials. For example, the gate electrode 160 may not contain aluminum, and the source-drain electrode 200 may contain aluminum.

Common insulating materials are used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180. For example, inorganic insulating materials such as silicon oxide (SiO_x), silicon oxynitride (SiO_xN_y), silicon nitride (SiN_x), silicon nitride oxide (SiN_xO_y), aluminum oxide (AlO_x), aluminum oxynitride (AlO_xN_y), aluminum nitride oxide (AlN_xO_y), and aluminum nitride (AlN_x) are used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180.

Silicon oxynitride (SiO_xN_y) and aluminum oxynitride (AlO_xN_y) are a silicon compound and an aluminum compound containing nitrogen (N) in a ratio (x>y) smaller than that of oxygen (O). Silicon nitride oxide (SiN_xO_y) and aluminum nitride oxide (AlN_xO_y) are a silicon compound and an aluminum compound containing oxygen (O) in a ratio (x>y) smaller than that of nitrogen (N).

Among the above-described inorganic insulating materials, the inorganic insulating material containing oxygen is used as the gate insulating layer 150. For example, an inorganic insulating material such as silicon oxide (SiO_x), silicon oxynitride (SiO_xN_y), or the like is used for the gate insulating layer 150.

An insulating layer having a function of releasing oxygen by a heat treatment is used as the gate insulating layer 120. For example, the temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is less than or equal to 600° C., less than or equal to 500° C., less than or equal to 450° C., or less than or equal to 400° C. That is, for example, in the case where the glass substrate is used as the substrate 100, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10.

An insulating layer with few defects is used as the gate insulating layer 150. For example, when a composition ratio of oxygen in the gate insulating layer 150 is compared with a composition ratio of oxygen in an insulating layer (hereinafter referred to as “other insulating layer”) having a composition similar to that of the gate insulating layer 150, the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in that other insulating layer. Specifically, in the case where silicon oxide (SiO_x) is used for each of the gate insulating layer 150 and the insulating layer 180, the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is close to the stoichiometric ratio of silicon oxide as compared with the composition ratio of oxygen in the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by electron-spin resonance (ESR) may be used as the gate insulating layer 150.

A metal oxide containing aluminum as the main component is used for the metal oxide layer 130 and a metal oxide layer 190 used in the manufacturing process as described later. For example, an inorganic insulating material such as aluminum oxide (AlO_x), aluminum oxynitride (AlO_xN_y), or the like is used for the metal oxide layer 130 (or the metal oxide layer 190). The “metal oxide layer containing aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer 130 (or the metal oxide layer 190) is greater than or equal to 1% of the total amount of the metal oxide layer 130 (or the metal oxide layer 190). The ratio of aluminum contained in the metal oxide layer 130 (or the metal oxide layer 190) may be greater than or equal to 5% and less than or equal to 70%, greater than or equal to 10% and less than or equal to 60%, or greater than or equal to 30% and less than or equal to 50% of the total amount of the metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

At least a part of the oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Thus, although described in detail later, aluminum contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140 when an OS annealing is performed. Therefore, the oxide semiconductor layer 140 includes a region with a high aluminum concentration in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. For example, the aluminum concentration can be detected by a secondary ion mass spectrometry (SIMS) analysis.

Further, although described in detail later, aluminum contained in the metal oxide layer 190 is diffused into the gate insulating layer 150 when the metal oxide layer 190 is deposited on the gate insulating layer 150 and an oxidation annealing is performed. Therefore, even after the metal oxide layer 190 is removed, the gate insulating layer 150 includes a region with a high aluminum concentration in the vicinity of a surface (in the vicinity of the surface on the opposite side to the oxide semiconductor layer 140).

A metal oxide having semiconductor properties is used for the oxide semiconductor layer 140. For example, an oxide semiconductor containing two or more metal elements including indium (In) is used for the oxide semiconductor layer 140. In the oxide semiconductor layer 140, the ratio of indium to two or more metal elements is greater than or equal to 50%. Gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids are used as a metal element of the oxide semiconductor layer 140 in addition to indium. Metal elements other than those described above may be used for the oxide semiconductor layer 140.

The oxide semiconductor layer 140 has crystallinity. The crystalline oxide semiconductor layer 140 has fewer oxygen deficiencies than an amorphous oxide semiconductor layer. Although the crystalline oxide semiconductor layer 140 may include an amorphous region, the proportion of the amorphous region in the oxide semiconductor layer 140 is smaller than the proportion of the crystalline region in the oxide semiconductor layer 140. For example, the proportion of the crystalline region in the oxide semiconductor layer 140 is greater than or equal to 70%, preferably greater than or equal to 80%, and more preferably greater than or equal to 90%.

Here, a crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to an embodiment of the present invention is described with reference to FIG. 3. FIG. 3 is a schematic cross-sectional view illustrating the crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to an embodiment of the present invention.

As shown in FIG. 3, the oxide semiconductor layer 140 includes a first crystal region 144 having a first crystal structure and a second crystal region 145 having a second crystal structure. The first crystal region 144 is formed only in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the first crystal region 144 is formed in contact with the metal oxide layer 130 and does not exist in a position away from the metal oxide layer 130. The oxide semiconductor layer 140 may have one first crystal region 144 formed therein, or may have a plurality of first crystal regions 144 formed therein. The second crystal region 145 is formed in contact with the metal oxide layer 130 and the first crystal region 144 so as to cover the first crystal region 144. In other words, in a cross-sectional view of the oxide semiconductor layer 140, the first crystal region 144 is surrounded by the metal oxide layer 130 and the second crystal region 145, and a crystal grain boundary is formed between the first crystal region 144 and the second crystal region 145.

As described above, the first crystal region 144 is formed only in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, and does not exist in a position away from the metal oxide layer 130. Therefore, the proportion of the first crystal region 144 in the oxide semiconductor layer 140 is significantly smaller than the proportion of the second crystal region 145 in the oxide semiconductor layer 140. In other words, in the cross-sectional view of the oxide semiconductor layer 140, the area of the first crystal region 144 is significantly smaller than the area of the second crystal region 145. That is, most of the oxide semiconductor layer 140 is formed by the second crystal region 145, and the crystal structure of the oxide semiconductor layer 140 is the same as the second crystal structure of the second crystal region 145.

The second crystal structure of the second crystal region 145 is, for example, a bixbyite structure, a corundum structure, a spinel structure, or a homologous structure. The bixbyite structure is one of the stable crystal structures of indium oxide. Each of the corundum structure and the spinel structure is one of the stable crystal structures of aluminum oxide or gallium oxide. The homologous structure is one of the stable crystal structures of indium gallium zinc oxide. The second crystal structure changes depending on the composition of the elements contained in the second crystal region 145. In addition, the homologous structure is expressed using an index m (m is a natural number) in the composition formula, and can have various periodic structures. Therefore, it is preferable that the second crystal structure is a bixbyite structure, a corundum structure, or a spinel structure rather than a homologous structure. The first crystal structure of the first crystal region 144 may be the same as or different from the second crystal structure of the second crystal region 145. However, when the first crystal structure is the same as the second crystal structure, the crystal orientation of the first crystal region 144 is different from the crystal orientation of the second crystal region 145 in the cross-sectional view of the oxide semiconductor layer 140. That is, the oxide semiconductor layer 140 includes at least two regions (the first crystal region 144 and the second crystal region 145) having different crystallinity, and the crystal grain boundary is formed between the first crystal region 144 and the second crystal region 145.

The reason why the first crystal region 144 is formed in the oxide semiconductor layer 140 is in the following description. As described above, aluminum contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140 when the OS annealing is performed on the oxide semiconductor layer 140 in contact with the metal oxide layer 130. In the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, the first crystal region 144 is formed with the diffused aluminum as a crystal nucleus. However, since the diffusion rate of the diffused aluminum in the oxide semiconductor layer 140 is not so high, the first crystal region 144 does not grow large. Thus, the second crystal region 145 is formed with the first crystal region 144, which has grown to a certain size, as a crystal nucleus. Therefore, since the first crystal region 144 contains aluminum diffused from the metal oxide layer 130, the aluminum concentration of the first crystal region 144 is higher than the aluminum concentration of the second crystal region 145. Further, since the diffused aluminum easily bonds with oxygen, the electrical conductivity of the first crystal region 144 may be smaller than the electrical conductivity of the second crystal region 145.

Although the crystalline oxide semiconductor layer has fewer oxygen deficiencies than the amorphous oxide semiconductor layer, the crystalline region of the oxide semiconductor layer also contains a considerable amount of oxygen deficiencies. Therefore, even in the crystalline oxide semiconductor layer, it is preferable that the oxygen deficiencies are further reduced. In the oxide semiconductor layer 140, the second crystal region 145 grows with the first crystal region 144 as a crystal nucleus, and the first crystal region 144 functions as a so-called buffer region. Therefore, compared with the crystal region directly grown from the metal oxide layer 130 or the gate insulating layer 120, the oxygen deficiencies are further reduced in the second crystal region 145 of the oxide semiconductor layer 140. Further, since the first crystal region 144 functions as the buffer region between the metal oxide layer 130 and the second crystal region 145, the interface state density of the oxide semiconductor layer 140 is reduced.

In addition, a configuration of the crystal structure of the oxide semiconductor layer 140 is not limited to the configuration shown in FIG. 3. Here, another crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to an embodiment of the present invention is described with reference to FIG. 4. FIG. 4 is a schematic cross-sectional view illustrating a crystal structure of the oxide semiconductor layer 140A of the semiconductor device 10 according to an embodiment of the present invention.

As shown in FIG. 4, the oxide semiconductor layer 140A includes a first crystal region 144A having a first crystal structure and a second crystal region 145A having a second crystal structure. The first crystal region 144A includes aluminum diffused from the metal oxide layer 130, and is formed as a layer at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the second crystal region 145A is not in contact with the metal oxide layer 130. Further, the thickness of the second crystal region 145A is larger than the thickness of the first crystal region 144A in the film thickness direction of the oxide semiconductor layer. Even in this case, since the first crystal region 144A functions as a buffer region (buffer layer), oxygen deficiencies in the second crystal region 145A are reduced and the interface state density of the oxide semiconductor layer 140A is reduced.

When the ratio of indium in the oxide semiconductor layer is greater than or equal to 50%, the oxide semiconductor layer has crystallinity. However, even in a crystalline oxide semiconductor layer, when oxygen deficiencies are formed in the crystal region of the oxide semiconductor layer, sufficient electrical characteristics and reliability cannot be obtained. In the present embodiment, the oxide semiconductor layer 140 includes the first crystal region 144 functioning as a buffer layer and the second crystal region 145 in which oxygen deficiencies are reduced. Therefore, the oxygen deficiencies and interface state density of the oxide semiconductor layer 140 are reduced, and the semiconductor device 10 has high mobility and high reliability.

In addition, not only the OS annealing but also the oxidation annealing is important in order to reduce oxygen deficiencies in the second crystal region 145 of the oxide semiconductor layer 140. In the following description, a method for manufacturing the semiconductor device 10 is described in detail.

[Manufacturing Method of Semiconductor Device 10]

A method for manufacturing the semiconductor device 10 according to an embodiment of the present invention is described with reference to FIGS. 5 to 12. FIG. 5 is a sequence diagram showing the method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. FIGS. 6 to 14 are cross-sectional views showing the method for manufacturing the semiconductor device 10 according to an embodiment of the present invention. In the following description, the method for manufacturing the semiconductor device 10 in which aluminum oxide is used for the metal oxide layers 130 and 190 is described.

As shown in FIGS. 5 and 6, the gate electrode 105 is formed on the substrate 100 as the bottom-gate, and the gate insulating layers 110 and 120 are formed on the gate electrode 105 (“Forming Bottom GI/GE” in step S2001 of FIG. 5). For example, silicon nitride is formed for the gate insulating layer 110. For example, silicon oxide is formed for the gate insulating layer 120. The gate insulating layers 110 and 120 are deposited by a CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 110 and 120 may be referred to as a “first insulating layer.”

When silicon nitride is used for the gate insulating layer 110, the gate insulating layer 110 can block impurities that diffuse, for example, from the substrate 100 toward the oxide semiconductor layer 140. The silicon oxide used for the gate insulating layer 120 is silicon oxide having a physical property of releasing oxygen by a heat treatment.

As shown in FIGS. 5 and 7, the metal oxide layer 130 and the oxide semiconductor layer 140 are deposited on the gate insulating layer 120 (“Depositing OS/AlO_x” in step S2002 of FIG. 5). For this process, it can be said that the gate insulating layers 110 and 120 are formed over the substrate 100, and the metal oxide layer 130 is deposited over the gate insulating layers 110 and 120. Alternatively, it can be said that the metal oxide layer 130 is deposited over the substrate 100, and the oxide semiconductor layer 140 is deposited on the metal oxide layer 130. Specifically, the oxide semiconductor layer 140 is deposited to be in contact with the metal oxide layer 130. The metal oxide layer 130 and the oxide semiconductor layer 140 are deposited by a sputtering method or an atomic layer deposition (ALD) method.

For example, a thickness of the metal oxide layer 130 is greater than or equal to 1 nm and less than or equal to 100 nm, greater than or equal to 1 nm and less than or equal to 50 nm, greater than or equal to 1 nm and less than or equal to 30 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. In the present embodiment, aluminum oxide is used for the metal oxide layer 130. Aluminum oxide has a high barrier property against gas. In the present embodiment, aluminum oxide used for the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

For example, a thickness of the oxide semiconductor layer 140 is greater than or equal to 10 nm and less than or equal to 100 nm, greater than or equal to 15 nm and less than or equal to 70 nm, or greater than or equal to 20 nm and less than or equal to 40 nm. In the present embodiment, an oxide containing indium (In) and gallium (Ga) is used for the oxide semiconductor layer 140. The oxide semiconductor layer 140 before the heat treatment (OS annealing) described later is amorphous.

When the oxide semiconductor layer 140 is crystallized by the OS annealing described later, it is preferable that the oxide semiconductor layer 140 after the deposition and before the OS annealing is in an amorphous state (a state in which there are less low crystalline components of the oxide semiconductor). That is, the deposition conditions of the oxide semiconductor layer 140 are preferred to be such that the oxide semiconductor layer 140 immediately after the deposition does not crystallize as much as possible. For example, in the case where the oxide semiconductor layer 140 is deposited by the sputtering method, the oxide semiconductor layer 140 is deposited in a state where the temperature of the object to be deposited (the substrate 100 and structures formed thereon) is controlled.

In the case where the deposition is performed on the object to be deposited by a sputtering method, ions generated in the plasma and atoms recoiled by a sputtering target collide with the object to be deposited. Thus, the temperature of the object to be deposited rises with the deposition process. When the temperature of the object to be deposited rises during the deposition process, microcrystals are included in the oxide semiconductor layer 140 immediately after the deposition process. The microcrystals inhibit crystallization by a subsequent OS annealing. For example, in order to control the temperature of the object to be deposited as described above, deposition may be performed while cooling the object to be deposited. For example, the object to be deposited may be cooled from a surface opposite to a deposited surface so that the temperature of the deposited surface of the object to be deposited (hereinafter, referred to as “deposition temperature”) is less than or equal to 100° C., less than or equal to 70° C., less than or equal to 50° C., or less than or equal to 30° C. As described above, when the oxide semiconductor layer 140 is deposited while cooling the object to be deposited, it is possible to deposit the oxide semiconductor layer 140 with few crystalline components in a state immediately after the deposition.

As shown in FIGS. 5 and 8, a pattern of the oxide semiconductor layer 140 is formed (“Forming OS Pattern” in step S2003 of FIG. 5). Although not shown in the figures, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. Wet etching or dry etching may be used for the etching method of the oxide semiconductor layer 140. The wet etching may be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid may be used as the etchant.

A heat treatment (“OS Annealing” in step S2004 of FIG. 5) is performed on the oxide semiconductor layer 140 after the pattern of the oxide semiconductor layer 140 is formed. In the present embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing. When the OS anneal is performed, aluminum contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140, and the first crystal region 144 is formed in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. Further, the second crystal region 145 is formed with the first crystal region 144 as a crystal nucleus.

As shown in FIGS. 5 and 9, a pattern of the metal oxide layer 130 is formed (“Forming AlO_x Pattern” in step S2005 of FIG. 5). The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. Wet etching or dry etching may be used for the etching method of the metal oxide layer 130. For example, dilute hydrofluoric acid (DHF) is used for the wet etching. As described above, a photolithography process can be omitted by etching the metal oxide layer 130 using the oxide semiconductor layer 140 as the mask.

As shown in FIGS. 5 and 10, the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 (“Forming GI” in step S2006 of FIG. 5). For example, silicon oxide is formed for the gate insulating layer 150. The gate insulating layer 150 is deposited by a CVD method. For example, the gate insulating layer 150 may be deposited at a deposition temperature higher than or equal to 350° C. in order to form an insulating layer having few defects as described above. For example, a thickness of the gate insulating layer 150 is greater than or equal to 50 nm and less than or equal to 300 nm, greater than or equal to 60 nm and less than or equal to 200 nm, or greater than or equal to 70 nm and less than or equal to 150 nm. A process of implanting oxygen may be performed on a part of the gate insulating layer 150 after the gate insulating layer 150 is deposited. The gate insulating layer 150 may be referred to as a “second insulating layer.” The metal oxide layer 190 is deposited on the gate insulating layer 150 (“Depositing AlO_x” in step S2007 of FIG. 3). The metal oxide layer 190 is deposited by a sputtering method. Oxygen is implanted into the gate insulating layer 150 by the deposition of the metal oxide layer 190.

For example, a thickness of the metal oxide layer 190 is greater than or equal to 5 nm and less than or equal to 100 nm, greater than or equal to 5 nm and less than or equal to 50 nm, greater than or equal to 5 nm and less than or equal to 30 nm, or greater than or equal to 7 nm and less than or equal to 15 nm. In the present embodiment, aluminum oxide is used for the metal oxide layer 190. Aluminum oxide has a high barrier property against gas. In the present embodiment, aluminum oxide used for the metal oxide layer 190 suppresses the oxygen implanted into the gate insulating layer 150 at the time of the deposition of the metal oxide layer 190 from diffusing outward.

For example, in the case where the metal oxide layer 190 is deposited by a sputtering method, a process gas used in the sputtering method remains in the metal oxide layer 190. For example, in the case where Ar is used as the process gas for the sputtering method, Ar may remain in the metal oxide layer 190. The remaining Ar can be detected by a SIMS analysis on the metal oxide layer 190.

A heat treatment for supplying oxygen to the oxide semiconductor layer 140 is performed in a state where the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 and the metal oxide layer 190 is deposited on the gate insulating layer 150 (“Oxidation Annealing” in step S2008 of FIG. 5). In other words, the oxidation annealing is performed on the metal oxide layer 130 and the oxide semiconductor layer 140 patterned as described above. In the process from the deposition of the oxide semiconductor layer 140 to the deposition of the gate insulating layer 150 on the oxide semiconductor layer 140, a large amount of oxygen deficiencies is formed in the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140 by the above-described oxidation annealing, and the oxygen deficiencies are repaired.

Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130. Therefore, oxygen is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from a region where the metal oxide layer 130 is not formed to the gate insulating layer 150 arranged on the gate insulating layer 120 and reaches the oxide semiconductor layer 140 through the gate insulating layer 150. As a result, the oxygen released from the gate insulating layer 120 is less likely to be supplied to the lower surface 142 of the oxide semiconductor layer 140, and is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. Further, the oxidation annealing makes it possible to supply oxygen released from the gate insulating layer 150 to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Although the oxidation annealing may release hydrogen from the gate insulating layers 110 and 120, the released hydrogen is blocked by the metal oxide layer 130.

As described above, in the oxidation annealing, it is possible to supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen deficiencies while suppressing the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen deficiencies.

Similarly, in the oxidation annealing described above, the oxygen implanted in the gate insulating layer 150 is blocked by the metal oxide layer 190. Therefore, the oxygen is suppressed from being released to the atmosphere. As a result, oxygen is efficiently supplied to the oxide semiconductor layer 140 by the oxidation annealing, and the oxygen deficiencies are repaired.

As shown in FIGS. 5 and 11, the metal oxide layer 190 is etched (removed) after the oxidation annealing (“Removing AlO_x” in step S2009 of FIG. 5). Wet etching or dry etching may be used for the etching method of the metal oxide layer 190. For example, dilute hydrofluoric acid (DHF) is used for the wet etching. The metal oxide layer 190 formed on the entire surface is removed by the etching. In other words, the removal of the metal oxide layer 190 is performed without using a mask. In other words, all of the oxide layer 190 including a region that overlaps the oxide semiconductor layer 140 formed in one pattern in at least a plan view is removed by the etching.

When the oxidation annealing is performed, aluminum contained in the metal oxide layer 190 is diffused into the gate insulating layer 150. Therefore, even when the metal oxide layer 190 is removed, aluminum diffused from the metal oxide layer 190 remains in the gate insulating layer 150.

As shown in FIGS. 5 and 12, the gate electrode 160 is formed on the gate insulating layer 150 (“Forming GE” in step S2010 of FIG. 5). The gate electrode 160 is deposited by a sputtering method or an atomic layer deposition method and patterned by a photolithography process. As described above, the gate electrode 160 is formed to be in contact with the gate insulating layer 150 exposed by removing the metal oxide layer 190.

When the gate electrode 160 is etched, a part of the gate insulating layer 150 may also be etched. That is, the gate insulating layer 150 includes regions having different thicknesses. Specifically, the gate insulating layer 150 includes a first region overlapping the gate electrode 160 and a second region not overlapping the gate electrode 160. The first region overlaps the channel region CH of the oxide semiconductor layer 140. The second region overlaps the source region S or the drain region D of the oxide semiconductor layer 140. The thickness of the second region is smaller than the thickness of the first region.

Resistances of the source region S and the drain region D of the oxide semiconductor layer 140 are reduced (“Reducing Resistance of SD” in step S2011 of FIG. 5) in a state where the gate electrode 160 is patterned. Specifically, impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140 by the ion implantation. When oxygen deficiencies are formed in the oxide semiconductor layer 140 by the ion implantation, the resistance of the oxide semiconductor layer 140 is reduced. Since the channel region CH in the semiconductor device 140 is provided so as to overlap the gate electrode 160 in the semiconductor device 10, impurities are not implanted into the channel region CH in the oxide semiconductor layer 140.

As shown in FIGS. 5 and 13, the insulating layers 170 and 180 are deposited on the gate insulating layer 150 and the gate electrode 160 as interlayer films (“Depositing Interlayer Film” in step S2012 of FIG. 5). The insulating layers 170 and 180 are deposited by a CVD method. For example, silicon nitride is deposited for the insulating layer 170, and silicon oxide is deposited for the insulating layer 180. The materials used for the insulating layers 170 and 180 are not limited thereto. A thickness of the insulating layer 170 is greater than or equal to 50 nm and less than or equal to 500 nm. A thickness of the insulating layer 180 is greater than or equal to 50 nm and less than or equal to 500 nm.

As shown in FIGS. 5 and 14, the openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 (“Opening Contact Hole” in step S2013 of FIG. 5). The oxide semiconductor layer 140 in the source region S is exposed by the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed by the opening 173. The semiconductor device 10 shown in FIG. 1 is completed by forming the source-drain electrode 200 on the insulating layer 180 so as to be in contact with the oxide semiconductor layer 140 exposed by the openings 171 and 173 (“Forming SD” in step S2014 of FIG. 5).

With respect to the semiconductor device 10 manufactured by the above-described manufacturing method, it is possible to obtain electrical characteristics having a mobility greater than or equal to 50 cm²/Vs, greater than or equal to 55 cm²/Vs, or greater than or equal to 60 cm²/Vs in a range where the channel length L of the channel region CH is greater than or equal to 2 μm and less than or equal to 4 μm and the channel width of the channel region CH is greater than or equal to 2 μm and less than or equal to 25 μm. The mobility in the present embodiment is the field-effect mobility in a saturation region in the electrical characteristics of the semiconductor device 10. Specifically, the mobility means the maximum value of the field-effect mobility in a region where a potential difference (Vd) between the source electrode and the drain electrode is greater than a value (Vg−Vth) obtained by subtracting a threshold-voltage (Vth) of the semiconductor device 10 from a voltage (Vg) supplied to the gate electrode.

Second Embodiment

A display device 20 using a semiconductor device 10 according to an embodiment of the present invention is described with reference to FIGS. 15 to 19. In the embodiment shown below, a configuration in which the semiconductor device 10 described in the First Embodiment described above is applied to a circuit of a liquid crystal display device is described.

[Overview of Display Device 20]

FIG. 15 is a plan view showing an overview of the display device 20 according to an embodiment of the present invention. As is shown in FIG. 15, the display device 20 includes an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit substrate 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded to each other by the sealing portion 310. A plurality of pixel circuits 301 is arranged in a matrix in a liquid crystal region 22 surrounded by the sealing portion 310. The liquid crystal region 22 is a region overlapping a liquid crystal element 311, which is described later, in a plan view.

A sealing region 24 where the sealing portion 310 is provided is a region surrounding the liquid crystal region 22. The FPC 330 is provided in a terminal region 26. The terminal region 26 is a region where the array substrate 300 is exposed from the counter substrate 320 and is provided outside the sealing region 24. The outside of the sealing region 24 means the outside of the region where the sealing portion 310 is provided and the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.

[Circuit Configuration of Display Device 20]

FIG. 16 is a block diagram showing a circuit configuration of the display device 20 according to an embodiment of the present invention. As is shown in FIG. 14, a source driver circuit 302 is arranged at a position adjacent to the liquid crystal region 22 where the pixel circuit 301 is arranged in the direction D1 (column direction), and a gate driver circuit 303 is arranged at a position adjacent to the liquid crystal region 22 in the direction D2 (row direction). The source driver circuit 302 and the gate driver circuit 303 are arranged in the sealing region 24 described above. However, the region where the source driver circuit 302 and the gate driver circuit 303 are arranged is not limited to the sealing region 24. The source driver circuit 302 and the gate driver circuit 303 may be arranged in any region outside the region where the pixel circuit 301 is arranged.

A source wiring 304 extends from the source driver circuit 302 in the direction D1 and is connected to the plurality of pixel circuits 301 arranged in the direction D1. A gate wiring 305 extends from the gate driver circuit 303 in the direction D2 and is connected to the plurality of pixel circuits 301 arranged in the direction D2.

A terminal portion 306 is provided in the terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected to each other by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected to each other by the connection wiring 307. By connecting the FPC 330 to the terminal portion 306, an external device which is connected to the FPC 330 and the display device 20 are connected to each other, and a signal from the external device drives each pixel circuit 301 arranged in the display device 20.

The semiconductor device 10 shown in the First Embodiment is used as a transistor included in the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303.

[Pixel Circuit 301 of Display Device 20]

FIG. 17 is a circuit diagram showing a pixel circuit of the display device 20 according to an embodiment of the present invention. As is shown in FIG. 17, the pixel circuit 301 includes elements such as the semiconductor device 10, a storage capacitor 350, and the liquid crystal element 311. The semiconductor device 10 has the gate electrode 160, the source electrode 201, and the drain electrode 203. The gate electrode 160 is connected to the gate wiring 305. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to the storage capacitor 350 and the liquid crystal element 311. In the present embodiment, although an electrode indicated by “201” is referred to as a source electrode and an electrode indicated by “203” is referred to as a drain electrode for the convenience of explanation, the electrode indicated by “201” may function as a drain electrode and the electrode indicated by “203” may function as a source electrode.

[Cross-Sectional Structure of Display device 20]

FIG. 18 is a cross-sectional view of the display device 20 according to an embodiment of the present invention. As shown in FIG. 18, the display device 20 is a display device in which the semiconductor device 10 is used. In the present embodiment, although a configuration in which the semiconductor device 10 is used for the pixel circuit 301 is exemplified, the semiconductor device 10 may be used for a peripheral circuit including the source driver circuit 302 and the gate driver circuit 303. In the following description, since the configuration of the semiconductor device 10 is the same as that of the semiconductor device 10 shown in FIG. 1, the description thereof is omitted.

An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 provided in common for the plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

In the display device 20, a wiring layer 162 is provided in the same layer as the gate electrode 160. The wiring layer 162 contains the same material as the gate electrode 160. The wiring layer 162 is provided on an insulating layer corresponding to the gate insulating layer 150. The metal oxide layer 190 is also deposited on the insulating layer, and the oxidation annealing is performed. An aluminum concentration of a region of the insulating layer not overlapping the wiring layer 162 is smaller than an aluminum concentration of a region of the insulating layer overlapping the wiring layer 162.

FIG. 19 is a plan view of the pixel electrode 390 and the common electrode 370 of the display device 20 according to an embodiment of the present invention. As shown in FIG. 19, the common electrode 370 has an overlapping region overlapping the pixel electrode 390 in a plan view, and a non-overlapping region not overlapping the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. The gradation of the pixel is determined by the operation of liquid crystal molecules included in the liquid crystal element 311 by the transverse electric field.

Third Embodiment

A display device 20 using the semiconductor device 10 according to an embodiment of the present invention is described with reference to FIGS. 20 and 21. In the present embodiment, a configuration in which the semiconductor device 10 described in the First Embodiment is applied to a circuit of an organic EL display device is described. Since the overview and the circuit configuration of the display device 20 are the same as those shown in FIG. 15 and FIG. 16, the description thereof is omitted.

[Pixel Circuit 301 of Display Device 20]

FIG. 20 is a circuit diagram showing a pixel circuit 301 of the display device 20 according to an embodiment of the present invention. As shown in FIG. 20, the pixel circuit 301 includes elements such as a drive transistor 11, a selection transistor 12, a storage capacitor 210, and a light emitting element DO. The drive transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to a signal line 211, and the gate electrode of the selection transistor 12 is connected to a gate line 212. The source electrode of the drive transistor 11 is connected to an anode power line 213, and the drain electrode of the drive transistor 11 is connected to one end of the light emitting element DO. The other end of the light emitting element DO is connected to a cathode power line 214. The gate electrode of the drive transistor 11 is connected to the drain electrode of the selection transistor 12. The storage capacitor 210 is connected to the gate electrode and the drain electrode of the drive transistor 11. A gradation signal for determining the light emitting intensity of the light emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row in which the gradation signal described above is written is supplied to the gate line 212.

[Cross-Sectional Structure of Display Device 20]

FIG. 21 is a cross-sectional diagram of the display device 20 according to an embodiment of the present invention. Although the configuration of the display device 20 shown in FIG. 21 is similar to that of the display device 20 shown in FIG. 18, the structure over the insulating layer 360 of the display device 20 in FIG. 21 is different from the structure over the insulating layer 360 of the display device 20 in FIG. 18. Hereinafter, in the configuration of the display device 20 in FIG. 21, descriptions of the same configuration as the display device 20 in FIG. 18 are omitted, and differences between the two are described.

As shown in FIG. 21, the display device 20 has the pixel electrode 390, a light emitting layer 392, and a common electrode 394 (the light emitting element DO) above the insulating layer 360. The pixel electrode 390 is provided over the insulating layer 360 and inside the opening 381. An insulating layer 362 is provided over the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to a light emitting region. That is, the insulating layer 362 defines a pixel. The light emitting layer 392 and the common electrode 394 are provided over the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light emitting layer 392 are individually arranged for each pixel. On the other hand, the common electrode 394 is arranged in common for the plurality of pixels. Different materials are used for the light emitting layer 392 depending on the display color of the pixel.

In the Second Embodiment and the Third Embodiment, although the configuration in which the semiconductor device 10 described in the First Embodiment is applied to a liquid crystal display device and an organic EL display device is described, the semiconductor device 10 may be applied to display devices (for example, a self-luminous display device or an electronic paper display device other than an organic EL display device) other than these display devices. Further, the semiconductor device 10 described above can be applied without any particular limitation from a small sized display device to a large sized display device.

EXAMPLES

As an Example, the semiconductor device 10 described in the First Embodiment was fabricated, and an evaluation was performed on the semiconductor device 10. Further, as a Comparative Example, a semiconductor device in which the metal oxide layer 130 in contact with the oxide semiconductor layer 140 was not provided was fabricated.

In both the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example, before forming the gate electrode 160, an aluminum oxide layer was formed as the metal oxide layer 190 by a sputtering method, and the aluminum oxide layer was removed after performing oxidation annealing.

[1. Electrical Characteristics]

FIG. 22 is a graph showing electrical characteristics of the semiconductor device 10 of the Example. Further, FIG. 27 is a graph showing electrical characteristics of the semiconductor device of the Comparative Example. Table 1 shows the conditions for measuring the electrical characteristics shown in FIGS. 22 and 27.

TABLE 1
Size of Channel Region W/L = 3.0 μm/3.0 μm
Source-Drain Voltage   0.1 V (thin solid line),
                       10 V (thick solid line)
Gate Voltage           −15 V to +15 V
Measurement            Room Temperature,
Environment            Dark Room

FIGS. 22 and 27 show not only the electrical characteristics (Id-Vg characteristics) but also mobility. In FIGS. 22 and 27, the vertical axis for the drain current (Id) is shown on the left side of the graph, and the vertical axis for the mobility calculated from the drain current is shown on the right side of the graph.

As shown in FIG. 22, the electrical characteristics of the semiconductor device 10 of the Example show so-called normally-off (enhancement type) characteristics in which the drain current Id starts to flow when the gate voltage Vg is higher than 0 V. The mobility calculated from the electrical characteristics is about 59 cm²/Vs.

As shown in FIG. 27, the electrical characteristics of the semiconductor device of the Comparative Example also show so-called normally-off (enhancement type) characteristics. The mobility calculated from the electrical characteristics is about 34 cm²/Vs.

As can be seen from the above, the mobility of the semiconductor device 10 of the Example is approximately twice as high as that of the semiconductor device of the Comparative Example, and it confirms that the semiconductor device 10 of the Example has high mobility.

[2. Reliability Test]

FIG. 23 is a graph showing a reliability test of the semiconductor device 10 of the Example. Further, FIG. 28 is a graph showing a reliability test of the semiconductor device of the Comparative Example. Table 2 shows that the measurement conditions of the reliability test shown in FIGS. 23 and 28. That is, reliability was evaluated by Negative Bias Temperature Illumination Stress (NBTIS) for the reliability test.

	TABLE 2
	NBTIS
	Size of Channel Region	W/L = 3.0 μm/3.0 μm
	Light Irradiation	With irradiation
	Conditions	(8000 cd/m2)
	Source and Drain Voltages	0	V
	Gate Voltage	−30	V
	Stage Temperature	60°	C.
	when stress is applied

In FIGS. 23 and 28, electrical characteristics measured at stress times of 0 sec, 100 sec, 500 sec, 1000 sec, 1500 sec, 2000 sec, and 3600 sec are displayed in an overlapping manner. Here, the time before stress application is set to 0 sec, and the time after stress application is set to 3600 sec. In FIGS. 23 and 28, the electrical characteristics before stress application (0 sec) are shown by a thick dotted line, and the electrical characteristics after stress application (3600 sec) are shown by a thick solid line.

In addition, Table 3 shows that the conditions for measuring the electrical characteristics before and after the application of stress.

TABLE 3
Size of Channel Region W/L = 3.0 μm/3.0 μm
Source-Drain Voltage   0.1 V, 10 V
Gate Voltage           −15 V to +15 V
Measurement            60° C.,
Environment            Dark Room

As shown in FIG. 23, the electrical characteristics before and after the stress application in the NBTIS test are almost unchanged in the semiconductor device 10 of the Example. The change in threshold voltage before and after the stress application is −0.05 V. That is, after the stress application, the threshold voltage shifts by only 0.05 V in the negative direction. Further, the electrical characteristics show normally-off characteristics even after the stress application.

As shown in FIG. 28, the electrical characteristics before and after the stress application in the NBTIS test are changed in the semiconductor device of the Comparative Example. The change in threshold voltage before and after the application of stress is −1.14 V. That is, after the stress application, the threshold voltage shifts by 1.14 V in the negative direction. As can be seen from the above, the reliability of the semiconductor device 10 of the Example is stable, and it confirms that the semiconductor device 10 of the Embodiment has high reliability.

[3. Cross-Sectional TEM Observation]

FIG. 24A is a cross-sectional TEM image of the semiconductor device 10 of the Example. FIG. 24B is a schematic diagram for explaining the cross-sectional TEM image of FIG. 24A. FIG. 29 is a cross-sectional TEM image of the semiconductor device of the Comparative Example. FIG. 24A shows a cross-sectional TEM image of the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 in the semiconductor device 10 of the Example. On the other hand, FIG. 29 shows a cross-sectional TEM image of the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 in the semiconductor device of the Comparative Example.

As shown in FIG. 24A, two different crystal regions can be confirmed in the semiconductor device 10 of the Example. Specifically, as shown in FIG. 24B, the first crystal region 144 in contact with the metal oxide layer 130 and the second crystal region 145 covering the first crystal region 144 can be confirmed in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140.

As shown in FIG. 29, the oxide semiconductor layer 140 has crystallinity in the semiconductor device of the Comparative Example. However, no crystal region different from the crystal region occupying most of the oxide semiconductor layer 140 is observed in the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140.

[4. Electron Beam Diffraction Measurement]

FIGS. 25 and 26 are electron beam diffraction images of the semiconductor device 10 of the Example. FIG. 25 shows an electron beam diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, and FIG. 26 shows an electron beam diffraction image in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. FIGS. 30 and 31 are electron beam diffraction images of the semiconductor device of the Comparative Example. FIG. 30 shows an electron beam diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the gate insulating layer 120 and the oxide semiconductor layer 140, and FIG. 31 shows an electron beam diffraction image in the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140.

Clear spots due to the crystal structure can be confirmed in FIG. 25. Therefore, it confirms that the oxide semiconductor layer 140 (the second crystal region 145) in the semiconductor device 10 of the Example has a crystal structure. On the other hand, spots different from the spots confirmed in FIG. 25 can be confirmed in FIG. 26. It is assumed that the spots confirmed in FIG. 26 are obtained by the crystal structure of the first crystal region 144. Therefore, it confirms that in the semiconductor device 10 of the Example, the first crystal region 144 in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 has a different crystal structure or crystal orientation from the second crystal region 145.

Clear spots due to the crystal structure can be confirmed in FIG. 30. Therefore, it confirms that the oxide semiconductor layer 140 in the semiconductor device of the Comparative Example also has a crystal structure. The same spots as those confirmed in FIG. 30 can also be confirmed in FIG. 31. Therefore, in the semiconductor device of the Comparative Example, no crystal region different from the crystal region occupying most of the oxide semiconductor layer 140 is confirmed in the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140.

As can be seen from the results of the cross-sectional TEM observation and the electron beam diffraction, in the semiconductor device 10 of the Example, the first crystal region 144 having crystallinity different from that of the second crystal region 145 occupying most of the oxide semiconductor layer 140 is formed in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. As described above, the semiconductor device 10 in which the first crystal region 144 is formed has high mobility and high reliability.

Each of the embodiments described above as the embodiments of the present invention can be appropriately combined and implemented as long as no contradiction is caused. Further, the addition, deletion, or design change of components, or the addition, deletion, or condition change of processes as appropriate by those skilled in the art based on each of embodiments are also included in the scope of the present invention as long as they are provided with the gist of the present invention.

Further, it is understood that, even if the effect is different from those provided by each of the above-described embodiments, the effect obvious from the description in the specification or easily predicted by persons ordinarily skilled in the art is apparently derived from the present invention.

Claims

1. A semiconductor device comprising:

a metal oxide layer containing aluminum over an insulating surface; and

an oxide semiconductor layer over the metal oxide layer,

wherein the oxide semiconductor layer comprises: a first crystal region in contact with the metal oxide layer, and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer,

wherein the first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.

2. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer contains two or more metal elements including indium, and

wherein a ratio of the indium to the two or more metal elements is greater than or equal to 50% in the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein an aluminum concentration of the first crystal region is larger than an aluminum concentration of the second crystal region.

4. The semiconductor device according to claim 1, wherein a thickness of the second crystal region is larger than a thickness of the first crystal region in a thickness of the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein a grain boundary is between the first crystal region and the second crystal region in the cross-sectional view of the oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein the first crystal region has a lower electrical conductivity than the second crystal region.

7. The semiconductor device according to claim 1, wherein the first crystal region is surrounded by the metal oxide layer and the second crystal region in the cross-sectional view of the oxide semiconductor layer.