Normally-off gallium nitride-based semiconductor devices

A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.

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Description
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. Nonprovisional patent application Ser. No. 12/657,757, filed Jan. 27, 2010, the contents of which are herein incorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure relates generally to semiconductor devices. More specifically, this disclosure relates to normally-off gallium nitride-based semiconductor devices.

BACKGROUND

Various III-V compounds are being investigated for use in high-power electronics applications. These compounds include III-V nitrides such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlinGaN). These compounds can be used to form High Electron Mobility Transistors (HEMTs) for use in high-power high-voltage applications.

Many conventional GaN-based transistor devices operate in a normally-on state or in a depletion mode. This typically requires the use of a negative bias voltage in order to turn off the transistor devices. The use of negative bias voltages is often undesirable. While some normally-off GaN-based transistor devices have been proposed, those devices also suffer from various disadvantages.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a first example normally-off gallium nitride-based semiconductor device according to this disclosure;

FIG. 2 illustrates example polarizations in the semiconductor device of FIG. 1 according to this disclosure;

FIG. 3 illustrates an example band diagram associated with the semiconductor device of FIG. 1 according to this disclosure;

FIGS. 4A and 4B illustrate example relationships between electrical characteristics and composition of the semiconductor device of FIG. 1 according to this disclosure;

FIG. 5 illustrates a second example normally-off gallium nitride-based semiconductor device according to this disclosure; and

FIG. 6 illustrates an example method for forming a normally-off gallium nitride-based semiconductor device according to this disclosure.

 DETAILED DESCRIPTION

FIGS. 1 through 6, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the invention may be implemented in any type of suitably arranged device or system.

FIG. 1 illustrates a first example normally-off gallium nitride-based semiconductor device 100 according to this disclosure. As shown in FIG. 1, the semiconductor device 100 is formed over a substrate 102. The substrate 102 represents any suitable semiconductor substrate that supports or carries other structures of the semiconductor device 100. The substrate 102 could, for example, represent a silicon, sapphire, or silicon carbide substrate.

A buffer layer 104 is formed over the substrate 102. The buffer layer 104 typically represents a thin layer used to help isolate other structures in the semiconductor device 100 from the substrate 102 (such as from defects in the substrate 102). The buffer layer 104 could be formed from any suitable material(s) and in any suitable manner. For example, the buffer layer 104 could represent an epitaxial layer, such as a gallium nitride (GaN) or aluminum gallium nitride (AlGaN) epitaxial layer.

A relaxed layer 106 is formed over the buffer layer 104. The relaxed layer 106 represents an active layer formed from material(s) generally not under tensile or compressive stress or under only a small amount of tensile or compressive stress. The relaxed layer 106 could be formed from any suitable material(s) and in any suitable manner. For example, the relaxed layer 106 could represent a GaN epitaxial layer.

A tensile layer 108 is formed over the relaxed layer 106. The tensile layer 108 represents a barrier layer formed from material(s) under tensile stress. The tensile layer 108 could be formed from any suitable material(s) and in any suitable manner. For example, the tensile layer 108 could represent an AlGaN epitaxial layer. Note that the aluminum concentration (if any) in the buffer layer 104 could be much less than the aluminum concentration in the tensile layer 108.

A compressive layer 110 is formed over the tensile layer 108. The compressive layer 110 represents a barrier layer formed from material(s) under compressive stress. The compressive layer 110 could be formed from any suitable material(s) and in any suitable manner. For example, the compressive layer 110 could be formed by depositing an epitaxial layer of AlinGaN and etching the AlinGaN to leave a portion of the AlinGaN over the tensile layer 110. The compressive layer 110 could also be formed by depositing AlinGaN in a specified area defined by a mask. Note that the aluminum concentration (if any) in the buffer layer 104 could be much less than the aluminum concentration in the compressive layer 110.

A source region 112 and a drain region 114 are formed in the tensile layer 108 and possibly in the relaxed layer 106. The source region 112 and the drain region 114 could be formed in any suitable manner, such as by masking the structure and performing a doping process (like an implantation or diffusion process). Also, any suitable dopant(s) could be used to form each of the source and drain regions 112-114.

A gate 116 is formed over the compressive layer 110. The gate 116 could be formed from any suitable conductive material(s) and in any suitable manner. For example, the gate 116 could be formed by depositing conductive material(s) over the structure and etching the conductive material(s) to form the gate 116. The gate 116 could also be formed by depositing conductive material(s) in a specified area defined by a mask.

As noted above, many conventional GaN-based transistor devices operate in a normally-on state or in a depletion mode. This is caused by spontaneous polarization, which results from asymmetry in the atomic structure of a GaN wurtzite crystal structure and from partial ionic bonding between aluminum, indium, or gallium and nitrogen. This spontaneous polarization induces a charge separation along the crystal growth axis for gallium face structures. Also, when a wide bandgap barrier layer 108 (such as AlGaN with an aluminum mole fraction between 10-30%) is used, a tensile strain is created due to lattice mismatch and thermal coefficient mismatch. This strain induces a piezoelectric polarization that further enhances charge separation in the AlGaN/GaN system. Bandgap discontinuities between low bandgap (GaN) and wide bandgap (AlGaN) layers and charge separation result in the formation of a two-dimensional electron gas at the AlGaN/GaN interface. The presence of this two-dimensional electron gas leads to a normally-on or depletion mode transistor.

In accordance with this disclosure, strain engineering is used in the semiconductor device 100 to compensate for the spontaneous polarization. The strain engineering is also used to invert the charge generated at the relaxed layer/tensile layer interface. An illustration of this is shown in FIG. 2, which illustrates example polarizations in the semiconductor device 100 of FIG. 1. As shown in FIG. 2, spontaneous polarization Psp in the layers 106 and 110 are in the same direction, but piezoelectric polarization Ppe in the layer 110 is in the opposite direction. This can generate a depleted electron region under the gate 116. At the same time, the source and drain regions 112-114 may have electrons accumulate at their interfaces with the layers 106-108. When a positive voltage is applied to the gate 116, the positive charge at the depleted electron region is depleted, and electron accumulation at the relaxed layer/tensile layer interface leads to an on state. As a result, high current and very low specific-on resistance (RDSoN) can be achieved in a normally-off GaN-based transistor device.

In the semiconductor device 100, the compressive layer 110 is used to compensate for the spontaneous polarization. When the compressive layer 110 is formed from AlinGaN, the aluminum composition could be about 20%, and the indium composition could be about 20%. With this composition, a compressive strain is generated on top of the tensile layer 108, which can result in a total strain that is slightly compressive. In particular embodiments, the AlinGaN compressive layer 110 could generate as much as 0.04 C/m2 of polarization, which can be slightly higher and opposite to the total spontaneous polarization in the device 100.

FIG. 3 illustrates an example band diagram 300 associated with the semiconductor device 100 of FIG. 1. The threshold voltage VT of the device 100 can be adjusted using the strain in the compressive layer 110 to compensate for the spontaneous polarization. With a piezoelectric polarization that is greater than or equal to the spontaneous polarization, at a zero gate voltage bias there may be little or no two-dimensional electron gas formed at the relaxed layer/tensile layer interface or at the relaxed layer/buffer layer interface.

FIGS. 4A and 4B illustrate example relationships between electrical characteristics and composition of the semiconductor device 100 of FIG. 1. In particular, FIG. 4A shows a graph 400 illustrating how the spontaneous polarization Psp in the device 100 varies based on the indium component of the compressive layer 110 (assuming an AlinGaN compressive layer with 20% aluminum). As shown here, the spontaneous polarization Psp varies but only slightly, increasing only about 0.0008 C/m2 for an indium component that varies from a zero mole fraction to a 0.25 mole fraction.

FIG. 4B shows a graph 450 illustrating how the piezoelectric polarization Ppe in the device 100 varies based on the indium component of the compressive layer 110 (assuming an AlinGaN compressive layer with 20% aluminum). As shown here, the piezoelectric polarization Ppe varies to a much greater extent, increasing more than 0.05 C/m2 for an indium component that varies from a zero mole fraction to a 0.25 mole fraction.

These graphs 400 and 450 illustrate that the indium component of an AlinGaN compressive layer 110 can be adjusted to arrive at a suitable piezoelectric polarization Ppe. This piezoelectric polarization Ppe can be selected so that it is slightly larger than the spontaneous polarization Psp.

FIG. 5 illustrates a second example normally-off gallium nitride-based semiconductor device 500 according to this disclosure. As shown in FIG. 5, the semiconductor device 500 includes a substrate 502, a buffer layer 504, and a relaxed layer 506. These components 502-506 may be the same as or similar to the corresponding components 102-106 in FIG. 1.

A compressive layer 508 is formed over the relaxed layer 506. The compressive layer 508 could be formed from any suitable material(s) and in any suitable manner. For example, the compressive layer 508 could be formed by depositing an epitaxial layer of AlinGaN and etching the AlinGaN to leave a portion of the AlinGaN over the relaxed layer 506. The compressive layer 508 could also be formed by depositing AlinGaN in a specified area defined by a mask. Again, the compressive layer 508 has enough compressive strain to compensate for the total spontaneous polarization generated in the semiconductor device 500.

A tensile layer 510 is formed over the relaxed layer 506 and beside or around the compressive layer 508. The tensile layer 510 could be formed from any suitable material(s) and in any suitable manner. For example, the tensile layer 510 could be formed from AlGaN. As a particular example, the tensile layer 510 could be formed by a selective epitaxial growth of AlGaN with a 20% aluminum content. Source and drain regions 512-514 are formed in the tensile layer 510 and possibly in the relaxed layer 506, and a gate 516 is formed over the compressive layer 508.

In the semiconductor device 100 of FIG. 1, two-dimensional electron gas can still form at the interface between the source region 112 and the layers 106-108 and at the interface between the drain region 114 and the layers 106-108. In the semiconductor device 500 of FIG. 5, two-dimensional electron gas can form at the interface between the source region 512 and the layers 506 and 510 and at the interface between the drain region 514 and the layers 506 and 510. This two-dimensional electron gas helps to provide high current and low specific-on resistance. However, the two-dimensional electron gas is located away from the gates 116 and 516 in areas where it does not cause the semiconductor devices 100 and 500 to be normally on. The two-dimensional electron gas can form in the semiconductor devices 100 and 500 because the compressive layers 110 and 508 are etched away from or not formed where the source and drain regions are located.

Although FIGS. 1 through 5 illustrate two example normally-off gallium nitride-based semiconductor devices and related details, various changes may be made to FIGS. 1 through 5. For example, while specific materials and manufacturing processes are described above, any other materials and manufacturing processes could be used to form various layers or other structures of the semiconductor devices 100 and 500. Also, while specific electrical or other characteristics are described above, these details are examples only.

FIG. 6 illustrates an example method 600 for forming a normally-off gallium nitride-based semiconductor device according to this disclosure. As shown in FIG. 6, a buffer layer is formed over a substrate at step 602. This could include, for example, forming the buffer layer 104, 504 over the substrate 102, 502. A relaxed layer is formed over the buffer layer at step 604. This could include, for example, forming the relaxed layer 106, 506 over the buffer layer 104, 504. Both layers could represent epitaxial layers.

Tensile and compressive layers are formed over the relaxed layer at step 606. This could include, for example, forming the tensile layer 108 over the relaxed layer 106 and forming the compressive layer 110 over the tensile layer 108. This could also include forming the compressive layer 508 over the relaxed layer 506 and forming the tensile layer 510 over the relaxed layer 506 and next to the compressive layer 508. The compressive layer has a piezoelectric polarization Ppe that is greater than or equal to the spontaneous polarization Psp in the structure.

Source, drain, and gate structures are formed at step 608. This could include, for example, forming source and drain regions 112-114, 512-514 in the tensile layer 108, 510 and optionally in the relaxed layer 106, 506. Formation of the semiconductor device is completed at step 610. This could include, for example, forming electrical connections to the source, drain, and gate structures. This could also include encapsulating the semiconductor device 100, 500 in a protective package or forming other structures to complete the formation of an HEMT transistor device.

Although FIG. 6 illustrates one example of a method 600 for forming a normally-off gallium nitride-based semiconductor device, various changes may be made to FIG. 6. For example, while shown as a series of steps, various steps in FIG. 6 could overlap, occur in parallel, or occur in a different order. Also, piezoelectric polarization management through strain can be obtained in many different ways, and the method 600 illustrates one example of this.

It may be advantageous to set forth definitions of certain words and phrases that have been used within this patent document. The terms “include” and “comprise, as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or.

While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.

Claims

1. An apparatus comprising:

a relaxed layer over a semiconductor substrate;
a tensile layer over the relaxed layer, the tensile layer having tensile stress;
a compressive layer over the relaxed layer, the compressive layer having compressive stress;
source and drain regions in at least the tensile layer; and
a gate over the compressive layer;
wherein the compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers and wherein the tensile layer is next to the compressive layer.

2. The apparatus of claim 1, wherein:

the relaxed layer comprises gallium nitride;
the tensile layer comprises aluminum gallium nitride; and
the compressive layer comprises aluminum indium gallium nitride.

3. The apparatus of claim 1, wherein the piezoelectric polarization in the compressive layer is in an opposite direction than the spontaneous polarization in the compressive layer.

4. The apparatus of claim 1, wherein the compressive layer is over the tensile layer.

5. The apparatus of claim 1, further comprising:

a buffer layer over the substrate;
wherein the relaxed layer is over the buffer layer.

6. An apparatus comprising:

a relaxed layer over a semiconductor substrate;
a tensile layer over the relaxed layer, the tensile layer having tensile stress; and
a compressive layer over the relaxed layer, the compressive layer having compressive stress;
wherein the compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers; and
wherein the tensile layer is next to the compressive layer.

7. The apparatus of claim 6, wherein:

the relaxed layer comprises gallium nitride;
the tensile layer comprises aluminum gallium nitride; and
the compressive layer comprises aluminum indium gallium nitride.

8. The apparatus of claim 7, wherein the piezoelectric polarization in the compressive layer is in an opposite direction than the spontaneous polarization in the compressive layer.

9. The apparatus of claim 7, wherein the aluminum indium gallium nitride has an indium mole fraction between 0.20 and 0.25.

10. The apparatus of claim 7, further comprising:

a buffer layer over the substrate;
wherein the relaxed layer is over the buffer layer.

11. A normally-off gallium nitride-based semiconductor device, comprising:

a buffer layer over a substrate;
a relaxed layer comprising gallium nitride over the buffer layer;
a tensile layer comprising aluminum gallium nitride over the relaxed layer, the tensile layer having tensile stress;
a compressive layer comprising aluminum indium gallium nitride over the relaxed layer, the compressive layer having compressive stress and the aluminum indium gallium nitride having an indium mole fraction between 0.20 and 0.25, wherein the tensile layer is next to the compressive layer;
source and drain regions in at least the tensile layer; and
a gate over the compressive layer.

12. The device of claim 11, wherein the compressive layer is over the tensile layer.

13. The device of claim 11, further comprising:

a buffer layer over the substrate;
wherein the relaxed layer is over the buffer layer.
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Patent History
Patent number: 9385199
Type: Grant
Filed: Jun 30, 2014
Date of Patent: Jul 5, 2016
Patent Publication Number: 20140312358
Assignee: NATIONAL SEMICONDUCTOR CORPORATION (Santa Clara, CA)
Inventor: Jamal Ramdani (Scarborough, ME)
Primary Examiner: Pamela E Perkins
Application Number: 14/319,490
Classifications
Current U.S. Class: With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) (257/190)
International Classification: H01L 31/0336 (20060101); H01L 29/225 (20060101); H01L 29/66 (20060101); H01L 29/778 (20060101); H01L 29/20 (20060101);