Abstract: A valve assembly includes mechanical hard stops that are integral with the actuator assembly. The valve assembly includes a valve body, a valve element, and an actuator assembly. The valve element is disposed within the valve body and is moveable between an open position and a closed position. The actuator assembly is coupled to the valve element and is adapted to receive one or more position control signals, and is operable to selectively move the valve element between the open and closed positions. An engagement structure is coupled to the valve element and is moveable therewith. A stop structure is fixedly coupled to the actuator assembly and is configured to engage the engagement structure when the valve is at least in one of the open and closed positions.

Abstract: An apparatus capable of moving a shiftable valve member into a closed position, the shiftable valve member mounted in a valve housing having a bore and being moveable between at least one open and at least one closed position relative to the bore, includes at least one elastically deformable member that extends at least partially around the circumference of the bore and is disposed at least partially in a cavity in the valve housing. Each elastically deformable member is elongated, has first and second ends and is connected to the shiftable valve member at one location and to the valve housing at at least one other location. Each elastically deformable member is torsionally loaded to provide biasing, closing force to the shiftable valve member to assist in moving the shiftable valve member into a closed position and retaining it in the closed position.

Abstract: A plastic outlet valve for containers for liquids has a valve housing having an inlet socket and a union nut for securing the inlet socket on an outlet socket of a container. An anti-twist device in the form of an outer annular cam arrangement with locking cams is arranged on the inlet socket of the valve housing. The locking cams interlock with locking cams of an inner annular cam arrangement of the outlet socket of the container. As an alternative, an adapter ring with inner and outer locking cams is provided. The adapter ring is slipped onto the insertion end of the inlet socket of the valve housing. The inner locking cams engage matching external longitudinal grooves of the inlet socket of the valve housing, and the outer locking cams engage matching inner longitudinal grooves provided on the outlet socket of the container.

Abstract: A valve assembly including a housing having a flow channel and an annular surface surrounding the flow channel, a slide plate movable to a closed position, and a seal ring positioned between the annular surface and the slide plate. The seal ring includes a first and second sides, a first surface extending between the first and the second sides and facing towards the annular surface of the housing, and a second surface axially spaced from the first surface and extending between the first and the second sides and facing towards the slide plate. The second surface includes a continuous annular sealing portion for contacting the slide plate when the seal ring is biased against the slide plate so that a fluid-tight seal can be formed between the continuous annular sealing portion and the slide plate, and at least one passageway positioned between the annular sealing portion and the second side.

Abstract: The invention relates to a crystallized solid, referred to by the name IM-12, which exhibits an x-ray diffraction diagram as provided below. Said solid exhibits a chemical composition that is expressed on an anhydrous base, in terms of oxide moles, by the formula XO2:mYO2:pZ2O3:qR2/nO, where R represents one or more cation(s) of valence n, X represents one or more different tetravalent element(s) of germanium, Y represents germanium, and Z represents at least one trivalent element.

Abstract: The present invention relates to switchable components for high-frequency technology, in particular microwave technology, which use liquid-crystalline dielectrics, to the liquid-crystal materials, to the use thereof, and to a process for the production of the components, for their operation and for improving their characteristics.

Abstract: The present invention relates a chiral compound, comprising a general formula as formula (L): wherein A, B independently are X, Y independently are fluorine (F), hydrogen (H) or chlorine (Cl); m represents an integral from 6 to 16; n represents 0 or 1; p represents 1,2,3 or 4; and q represents 1,2,3 or 4.

Abstract: Composite materials formed of a matrix of fused ceramic grains with single-wall carbon nanotubes dispersed throughout the matrix and a high relative density, notably that achieved by electric field-assisted sintering, demonstrate unusually high electrical conductivity in combination with high-performance mechanical properties including high fracture toughness. This combination of electrical and mechanical properties makes these composites useful as electrical conductors in applications where high-performance materials are needed due to exposure to extreme conditions such as high temperatures and mechanical stresses.

Abstract: A cable is installed in a protective duct or guide tube by means of blowing (and, optionally, synergetic pushing) and lubricating the cable during installation. Lubricating the cable is done after the cable exits from the cable blowing equipment and hence takes place in a pressurized airflow passage. A hollow chamber filled with foam-plugs saturated with lubricant forms the cable lubricator. Lubricant is wiped onto the cable as it moves through the pressurized lubrication compartment. A portion of the airflow used for propelling the cable during blowing installation is bypassed around the lubricator and injected into the duct trajectory downstream of the lubricator.

Abstract: This invention relates to vertical fencing, and in particular to bow-top vertical fencing. According to the invention there is provided vertical fencing comprising a pair of rails and a plurality of tubular bow-top fence members attached thereto, each fence member comprising a pair of interconnected legs, the rails being pivotable relative to the fence members, each leg of a fence member having a connector by which it may be connected to at least one of the rails, and at least one of connectors being movable relative to the longitudinal axis of the fence member. The connector may be a resiliently-biassed projection, or a rivet, for example.

Abstract: A handrail and bracket assembly includes a pair of brackets having two off-set channels that permit the hand rail to be positioned in an expanded or in-use position or a collapsed or stowed position. At least one mounting opening is provided in each bracket for securing it to a wall or other surface. The channels and openings are positioned such that the brackets can be attached to the handrail prior to attaching the brackets to a wall or other surface.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, wherein the method comprises depositing a first diode layer of material on a substrate, and depositing a second diode layer of phase-change material on the first diode layer, the phase-change material containing copper, indium and selenium.

Abstract: A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the second conductor. At least one mobile charge is positionable within the tunneling barrier. The device also includes a gate, wherein a voltage applied to the gate with respect to the substrate (or with respect to a second gate formed on or in the substrate) modulates or moves the mobile charge to a position between the first conductor and the second conductor within the tunneling barrier, thus deforming the shape of the energy barrier between the first conductor and the second conductor. The deformation can cause a current to flow between the conductors when a voltage is present between them due to quantum mechanical tunneling.

Abstract: Disclosed is a nitride-based semiconductor device including a first nitride semiconductor layer doped with an n type impurity, an active layer formed on the first nitride semiconductor layer, the active layer including a plurality of quantum well layers and a plurality of quantum barrier layers alternately laminated over one another, at least one of the quantum layers being doped with the n type impurity, and a nitride semiconductor layer formed over the active layer, and doped with a p type impurity. The quantum barrier layer doped with the n type impurity includes an internal layer portion doped with the n type impurity, and an anti-diffusion film arranged at an interface of the quantum barrier layer with an adjacent one of the quantum well layers, the anti-diffusion film having an n type impurity concentration lower than that of the internal layer portion.

Abstract: The present invention relates to a preferred semiconductor substrate for the production of devices. The semiconductor substrate is comprised of GaAs. Then, a plurality of quantum rings, which are composed of GaSb and have a substantially elliptical shape with an aspect ratio of 2 or more but 5 or less, are formed on a surface of the semiconductor substrate. These quantum rings extend along in the substantially same direction. In a case where a light beam is irradiated onto the surface of the semiconductor substrate, among the polarized components of the irradiated light, one polarized component parallel to the long-axis direction of the ellipse that is an extending direction of each quantum ring is reflected, while another polarized component parallel to the short-axis direction thereof is transmitted. That is, the semiconductor substrate reflects one polarized component, and transmits the other polarized component.

Abstract: The present invention relates to a semiconductor device comprising a substrate (101); a semiconductor multi-layered structure formed on the substrate (101); the semiconductor multi-layered structure comprising an emitter layer (102), a base layer (105), and a collector layer (107), each composed of a group III-V n-type compound semiconductor and layered in this order; a quantum dot barrier layer (103) disposed between the emitter layer (102) and the base layer (105); a collector electrode (110), a base electrode (111) and an emitter electrode (112) connected to the collector layer (107), the base layer (105) and the emitter layer (102), respectively; the quantum dot barrier layer (103) comprising a plurality of quantum dots (103c); the quantum dots (103) being sandwiched between first and second barrier layers (103a, 103d) from the emitter layer side and the base layer side, respectively; each of the quantum dots (103c) having a convex portion that is convex to the base layer (105); a base layer (105) side in

Abstract: A tester for a semiconductor device is provided, which includes a bottom ground pad structure, an intermediate ground pad structure, and a top layer. The bottom ground pad structure is electrically connected to a substrate. The bottom ground pad structure includes a bottom signal shield plate. The intermediate ground pad structure is electrically connected to the bottom ground pad structure. The intermediate ground pad structure is located over the bottom ground pad structure. The top layer is located over the intermediate ground pad structure. The top layer includes a device under test (DUT), a ground probe pad, a signal probe pad, and leads. The DUT is electrically connected to the ground probe pad and the signal probe pad via the leads. The ground probe pad is electrically connected to the intermediate ground pad structure. The signal probe pad is located over the bottom signal shield plate.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an interlayer insulating film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

Abstract: A relaying pad is formed in a predetermined portion in an insulation layer of the single-crystal thin film device, in a region where the single-crystal thin film device is formed. The relaying pad is for providing connection wiring through the insulator substrate. With this configuration it is possible to prevent an increase in an aspect ratio of a contact hole formed in an insulation layer in a region in which a transferred device is formed, the semiconductor device including a substrate on which the transferred device and a deposited device coexist.

Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.

Abstract: Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.

Abstract: The present invention presents a semiconductor device (10) which is adapted to a solar cell, and in which a semiconductor element (1) is produced by forming one flat surface (2) on a spherical or substantially spherical silicon single crystal (1a, 1b). A diffusion layer (3) and a substantially spherical pn junction (4) are formed on this semiconductor element (1), and a diffusion-mask thin film (5) and a positive electrode (6a) are formed on the flat surface (2). A negative electrode 6b is formed at the apex on the opposite side to the positive electrode (6a), and an antireflection film (7) is formed on the surface side of the diffusion layer (3).

Abstract: A semiconductor light emitting device and a fabrication method thereof includes: providing a substrate; forming an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer on the substrate; forming a first transparent electrode having holes per a certain region on the p-type semiconductor layer; and forming a first pad on the first transparent electrode.

Abstract: A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.

Abstract: A semiconductor light-emitting device capable of attaining a surface plasmon effect while attaining excellent ohmic contact is provided. This semiconductor light-emitting device comprises a semiconductor layer formed on an emission layer, a first electrode layer formed on the semiconductor layer and a second electrode layer, formed on the first electrode layer, having a periodic structure. The first electrode layer is superior to the second electrode layer in ohmic contact with respect to the semiconductor layer, and the second electrode layer contains a metal exhibiting a higher plasma frequency than the first electrode layer.

Abstract: An LCD having semiconductor components. In one embodiment of the invention, the structure with multiple silicon layers comprises a substrate, a first silicon layer on the substrate, a gate dielectric layer on the first silicon layer, a gate on the gate dielectric layer, an interlayer dielectric layer on the gate, and a second silicon layer on the interlayer dielectric layer.

Abstract: A high efficiency and high brightness multi-active layer tunneling regenerated white color semiconductor light emitting diode having a p type electrode 1, a monolithic red light cell 14, a tunnel junction 9, a monolithic green light 15 and blue light cell 16 (or a monolithic cyan light cell 19), wherein each of said cells are electrically connected by tunnel junctions 9, and the red cell physically connected with blue and green cell (or cyan cell) by wafer bonding layer 8. The lights from each cell synthesize white color light. The white light emitting diode only has one time optical-electrical conversion, so the quantum efficiency is high. Moreover, the white LED totally made from semiconductor materials, the lifetime of the white LED lamp is not limited by the relatively short lifetime of fluorescent material.

Abstract: A light emitting diode comprising: a base substrate having a pair of electrodes; a reflection cup installed on the base substrate; a light emitting element arranged at a bottom of the reflection cup; and a resin sealant enclosing the light emitting element; wherein the light emitting element is electrically connected to the electrodes through an opening formed in the bottom of the reflection cup; wherein the reflection cup comprises a film body held in a cup shape and a metal film formed on a surface of the film body. This construction makes the control of light directivity easy and can produce light with a narrow directivity.

Abstract: Certain compound semiconductor materials can be formed with nearly metal-like conductivity, while retaining the crystalline structure, high mobilities, and high carrier velocities of conventional semiconductors. Such bulk and thin-film states of matter, method of creating them, devices formed therefrom, and applications benefiting from said devices and states of matter are disclosed herein.

Abstract: A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A semiconductor device that permits an increase in static destruction resistance while preventing an increase in the chip size includes a protective element formed by a polysilicon layer in which JFETs are serially connected in three stages and which is inserted between a gate electrode and source electrode of a power-MOSFET or IGBT semiconductor device. The gate insulation film of a semiconductor active element portion of the semiconductor device is protected regardless of whether the polarity of static electricity or another high voltage is positive or negative.

Abstract: A microelectromechanical system includes a substrate, a transducer supported on the substrate and a conductor layer, which is also supported on the substrate and electrically connected to the transducer. The transducer includes a portion made of silicon or a silicon compound. The conductor layer is made of a refractory conductor, which includes, as its main ingredient, at least one element selected from the group consisting of copper, gold and silver. At least a portion of the conductor layer is located at an intermediate level between the silicon or silicon compound portion of the transducer and the substrate.

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

Abstract: A method of manufacturing an electronic component, including: forming a thermoplastic resin layer on a surface of a semiconductor substrate including a plurality of integrated circuits and a bump electrode provided on each of the integrated circuits, to bury the bump electrode; forming a conductive pattern on a surface of the thermoplastic resin layer opposite to the semiconductor substrate, and electrically connecting the conductive pattern to the bump electrode; and dividing the semiconductor substrate in units of the integrated circuits.

Abstract: A submount that enables the reliable mounting of a semiconductor light-emitting device on it, and a semiconductor unit incorporating the submount. A submount 3 comprises (a) a substrate 4; and (b) a solder layer 8 formed on the top surface 4f of the substrate 4. The solder layer 8 before melting has a surface roughness, Ra, of at most 0.18 ?m. It is more desirable that the solder layer 8 before melting have a surface roughness, Ra, of at most 0.15 ?m, yet more desirably at most 0.10 ?m. A semiconductor unit 1 comprises the submount 3 and a laser diode 2 mounted on the solder layer 8 of the submount 3.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: In an embodiment of the invention, an electronic device includes an interfacial layer with traps. This interfacial layer is between an electrode and an organic layer, and if the electrode was adjacent to the organic layer, the energy barrier between these two layers is such that the current through the organic layer is limited by charge injection into this layer rather than the transport properties of the organic layer. The traps are used to accumulate charges of one charge type (e.g., either electrons or holes) within the interfacial layer. By accumulating charges, the bands of the interfacial layer are bent so that charges can tunnel from the electrode to the organic layer thus increasing the efficiency of the electronic device and allowing organic layers to be used within an electronic device that otherwise would be too inefficient for use in that device.

Abstract: A CMOS image sensor and a method for manufacturing the same, capable of preventing an interface between an active region and a field region in the CMOS image sensor from being damaged by ion implantation. The method comprises implanting dopant ions into a source region between a gate electrode of the reset transistor and the photodiode, using an ion implantation mask that covers predetermined locations of the field region and the source region.

Abstract: Disclosed is an imaging device including a photodiode and floating diffusion region formed to be spaced from each other on a surface layer of a pixel region of a silicon (semiconductor) substrate, and a transfer gate having one of a concave and convex portions toward the floating diffusion region, the transfer gate being formed above the silicon substrate between the photodiode and the floating diffusion region by interposing a gate insulating film therebetween.

Abstract: To eliminate the influence of radiation noise, which drops the image quality of a photoelectric converter, at a low cost without sacrificing an opening portion of a light receiving element. A photoelectric converter includes: a first semiconductor region of a first conductive type which is formed within a pixel region; a second semiconductor region of a second conductive type which is formed within the first semiconductor region and in which optically generated carriers can be accumulated; and a conductor which is formed through an insulator on the second semiconductor region and held at a predetermined potential.

Abstract: A process for fabricating a ferrocapacitor comprises etching a layer of amorphous PZT formed over a layer having a low concentration of nucleation centres for PZT crystallisatlon. The etching step forms individual PZT elements. The side surfaces of the PZT elements are then coated with a layer of a material which promotes crystallisation of the PZT, such as one having a high concentration of PZT crystallisation centres (e.g. TiO2), and a PZT annealing step is carried out. The result is that the PZT has a high degree of crystallisation, with grain boundaries extending substantially horizontally through the PZT elements.

Abstract: A ferroelectric capacitor device, such as an FeRAM device is formed by forming a substrate extending in a first plane and comprising a number of layers of material, forming a hard mask layer on the substrate and forming a first layer of a first material on the hard mask layer. The hard mask shape is then defined by etching the hard mask layer. A second layer of the first material is deposited on the etched hard mask layer. The deposited second layer has one or more side surfaces extending substantially perpendicular to the plane of the substrate. The second layer and the number of layers forming the substrate are then etched to shape the ferroelectric capacitor device.

Abstract: A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

Abstract: First and second ferroelectric capacitors are selectively connected with a first bit line. Data is read to the first bit line from a first ferroelectric capacitor by applying a first voltage in a coordinate increasing direction of an axis or from the second ferroelectric capacitor by applying a second voltage having a sign opposite to the first voltage in the coordinate increasing direction. Third and fourth ferroelectric capacitors are selectively connected with a second bit line. Data is read to the second bit line from the third ferroelectric capacitor by applying a third voltage having the same sign as the first voltage in the coordinate increasing direction or from the fourth ferroelectric capacitor by applying a fourth voltage having the same sign as the second voltage in the coordinate increasing direction. A sense amplifier amplifies the potential difference between the first and second bit lines.

Abstract: A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.

Abstract: A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.