Abstract: A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.

Abstract: A liquid crystal display has, a plurality of pixel including a switching element, a plurality of gate lines extending transversally, a plurality of data lines extending longitudinally, a first storage electrode line extending transversally, a second storage electrode line extending longitudinally, a third storage electrode line connecting two of the adjacent second storage electrode line, a repair assistant formed in an area that the data line crosses over the third storage electrode line. The liquid crystal display can be repaired with good quality by shortening the repair path.

Abstract: The present invention relates generally to a method and means for growing strained or relaxed or graded silicon germanium (SiGe) layers on a semiconductor substrate using a selective epitaxial growth process. In particular, the present invention provides a method for epitaxially growing SiGe layers at temperatures lower than 600° C. by using halogermane and silane precursor materials.

Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.

Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.

Abstract: A mask containing apertures therein which is used for fabricating a channel of a thin film transistor (TFT), wherein the pixel charging time for a TFT in a high-resolution liquid crystal display (LCD) device is reduced by minimizing the length of the channel in the TFT when the active region is made of amorphous silicon. The length of the channel can be minimized by exposing light through the apertures in an exposure mask when forming the channel.

Abstract: A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

Abstract: A semiconductor multi-layered structure (1) having non-uniform quantum dots formed without requiring lattice strain is of a double hetero junction structure in which an active layer (3) has clad layers (5, 6, 16) laid on its opposite sides, wherein the clad layers are larger in forbidden band than the active layer (3), and the active layer (3) includes at least one layer of non-uniform quantum dots (2) formed without requiring lattice strain and wherein the non-uniform quantum dots in the layer (2) are composed of compound semiconductor material and different from one another in either size or material composition or both. A light emitting diode (15, 15?), a semiconductor laser diode (20) and a semiconductor light amplifier (30) are also provided, each having a semiconductor multi-layered structure (1, 1?) with non-uniform quantum dots. They can emit or amplify light wide in range of wavelengths.

Abstract: The present invention is directed towards a source of ultraviolet energy, wherein the source is a UV-emitting LED's. In an embodiment of the invention, the UV-LED's are characterized by a base layer material including a substrate, a p-doped semiconductor material, a multiple quantum well, a n-doped semiconductor material, upon which base material a p-type metal resides and wherein the base structure has a mesa configuration, which mesa configuration may be rounded on a boundary surface, or which may be non-rounded, such as a mesa having an upper boundary surface that is flat. In other words, the p-type metal resides upon a mesa formed out of the base structure materials. In a more specific embodiment, the UV-LED structure includes n-type metallization layer, passivation layers, and bond pads positioned at appropriate locations of the device. In a more specific embodiment, the p-type metal layer is encapsulated in the encapsulating layer.

Abstract: The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.

Abstract: An organic light emitting display and a driving method thereof, with an improved aperture ratio is disclosed. In one embodiment, the organic light emitting display comprises: a plurality of scan lines and a plurality of emission control lines, which are arranged in a horizontal direction; a plurality of data lines arranged in a vertical direction; and a pixel portion comprising a plurality of pixel circuits electrically connected to the scan line, the emission control line and the data line, wherein each pixel circuit is connected to two organic light emitting diodes placed on different two horizontal lines, and two emission control lines are connected to the organic light emitting diodes placed on two horizontal lines in a zigzag pattern.

Abstract: Whereas incandescent light bulbs and other similar light sources known in the related art emit light in all directions, LED lamps can emit light in a single direction, and this is manifested in the problem of being unable to achieve light distribution characteristics satisfied by conventional headlamp designs. In accordance with an embodiment of the invention, an LED lamp for a light source of a headlamp can include an LED chip 2 in the vicinity of the focus of a projection means and a shielding member 7 covering a portion of the LED chip 2 in a formation allowing a light distribution characteristic suitable for a vehicle front-illumination light to be obtained when light from the LED chip 2 is magnified and projected in an illumination direction by a projection lens 10 or the like constituting the projection means. Accordingly, accurate light distribution characteristics can be obtained in a simple manner by projecting in the illumination direction using the projection lens 10.

Abstract: Disclosed is a light-emitting diode chip comprising a semiconductor layer sequence suitable for emitting primary electromagnetic radiation and further comprising a converter layer that is applied to at least one main face of the semiconductor layer sequence and comprises at least one phosphor suitable for converting a portion of the primary radiation into secondary radiation, at least a portion of the secondary radiation and at least a portion of the unconverted primary radiation overlapping to form a mixed radiation with a resulting color space. The converter layer is purposefully structured to adjust a dependence of the resulting color space on viewing angle. Also disclosed is a method of making a light-emitting diode chip in which a converter layer is purposefully structured.

Abstract: A radiation-emitting semiconductor component with a layer structure (12) which includes a photon-emitting active layer (16), an n-doped cladding layer (14) and a p-doped cladding layer (18), a contact connected to the n-doped cladding layer (14) and a mirror layer (20) connected to the p-doped cladding layer (18). The mirror layer (20) is formed by an alloy of silver comprising one or more metals selected from the group consisting of Ru, Rh, Pd, Au, Os, Ir, Pt, Cu, Ti, Ta and Cr.

Abstract: The invention is a light emitting diode that exhibits high reflectivity to incident light and high extraction efficiency for internally generated light. The light emitting diode includes a reflecting layer that reflects both the incident light and the internally generated light. A multi-layer semiconductor structure is deposited on the reflecting layer. The multi-layer semiconductor structure has an active layer that emits the internally generated light. An array of light extracting elements extends at least part way through the multi-layer semiconductor structure and improves the extraction efficiency for internally generated light. The light extracting elements can be an array of trenches, an array of holes, an array of ridges or an array of etched strips. The light emitting diode improves the efficiency of light recycling illumination systems.

Abstract: A flip-chip type of Group III nitride based compound semiconductor light-emitting device comprises a transparent conductive film 10 made of ITO on a p-type contact layer. On the transparent conductive film, an insulation protection film 20, a reflection film 30 which is made of silver (Ag) and aluminum (Al) and reflects light to a sapphire substrate side, and a metal layer 40 made of gold (Au) are deposited in sequence. Because the insulation protection film 20 exists between the transparent conductive film 10 and the reflection film 30, metal atoms comprised in the reflection film 30 can be prevented from diffusing in the transparent conductive film 10. That enables the transparent conductive film 10 to maintain high transmissivity. As a result, a light-emitting device having high external quantum efficienty can be provided.

Abstract: A system and method for active array temperature sensing and cooling. The system includes an active temperature sensing layer, a thermoelectric cooling layer and a heatsink layer. The temperature sensing layer is formed of temperature sensing elements that sense the temperature gradient across an unevenly heated region of the active array substrate. The thermoelectric cooling layer controls the temperature gradient sensed by the temperature sensing layer. The heatsink layer includes a plurality of cooling channels for absorbing thermal energy from the unevenly heated region. The system is under the control of a process control computer.

Abstract: A light emitting device includes a substrate, a doped substrate layer, a layer of first conductivity type overlying the doped substrate layer, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A conductive transparent layer, e.g., of indium tin oxide, and a reflective metal layer overlie the layer of second conductivity type and provide electrical contact with the layer of second conductivity type. A plurality of vias may be formed in the reflective metal and conductive transparent layer as well as the layer of second conductivity type, down to the doped substrate layer. A plurality of contacts are formed in the vias and are in electrical contact with the doped substrate layer. An insulating layer formed over the reflective metal layer insulates the plurality of contacts from the conductive transparent layer and reflective metal layer.

Abstract: An optical component with integrated back monitor photodiode. The optical component includes a substrate doped with a first type dopant, such as an n-type dopant. The substrate has a trench with sloped walls. An optical source is disposed in the trench. An implant of a second type dopant, such as a p-type dopant, is in the substrate around at a least a portion of the optical source. The implant in the substrate in combination with the first type dopant in the substrate forms a diode.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Abstract: An optical film includes a base layer, a resin layer and a plurality of hollow particles. The resin layer is disposed on a surface of the base layer. The hollow particles are disposed in the resin layer. The hollow particles each have an epidermis that defines an inner space of a hollow particle. The hollow particles reflect or transmit light due to a refractive index difference between the epidermis and the inner space.

Abstract: Radiation occurs when current is injected into an active layer from electrodes. A pair of clad layers is disposed sandwiching the active layer, the clad layer having a band gap wider than a band gap of the active layer. An optical absorption layer is disposed outside at least one clad layer of the pair of clad layers. The optical absorption layer has a band gap wider than the band gap of the active layer and narrower than the band gap of the clad layer. A spread of a spectrum of radiated light can be narrowed.

Abstract: An organic light emitting device (OLED) and a method for manufacturing the same are disclosed. In one embodiment, the OLED includes i) a pixel layer having a first electrode, a second electrode, and a light emitting portion interposed between the first electrode and the second electrode and having at least an emission layer, ii) a transparent member disposed in a direction in which light generated from the pixel layer is transmitted, iii) a diffraction grating disposed between the pixel layer and the transparent member, and iv) a low-refractive layer made of a material having a refractive index less than that of a material forming the transparent member, the low-refractive layer disposed between the diffraction grating and the transparent member. The OLED can prevent image spreading and deterioration in color purity while having enhanced light coupling efficiency.

Abstract: A nitride semiconductor substrate having a rugged surface being lapped by whetting granules to roughness between Rms5 nm and Rms200 nm, which has a function of reducing dislocations of a GaN, InGaN or AlGaN layer epitaxially grown on the lapped substrate by gathering dislocations in the epi-layer to boundaries of holes, pulling the dislocations to bottoms of the holes. Higher roughness of the nitride substrate degrades morphology of an epitaxially-grown layer thereon but reduces dislocation density to a lower level. Morphology of the epi-layer contradicts the dislocation density of the epi-layer. The nitride semiconductor substrate can reduce dislocation density and can be low cost and useful substrates.

Abstract: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided.

Abstract: The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

Abstract: A circuit arrangement comprises at least one power component and a drive circuit for the power component, which are integrated in a first and a second semiconductor chip. Only CMOS components of the drive circuit or CMOS components, capacitive components and resistance components of the drive circuit are integrated in the first semiconductor chip, and the at least one power component and further components of the drive circuit are integrated in the second semiconductor chip.

Abstract: A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires.

Abstract: A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).

Abstract: There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of second metal lines are formed on the first metal layer and connected with a ground voltage. The second metal lines are arranged neighboring to the first metal lines. The second metal lines are connected with a second metal layer disposed below the first metal lines on the metal layer, and the first metal lines are connected with the second metal layer disposed below the second metal lines on the first metal layer. An insulating layer is disposed between the first metal layer and the second metal layer, thereby forming a decoupling capacitance between the first metal lines and the second metal lines.

Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.

Abstract: A thin film transistor array substrate and manufacturing method thereof are provided. A shielding layer is formed between lead lines in a peripheral region of the substrate. The shielding layer and a gate layer may be formed simultaneously so that the light leakage between lead lines connected to a source/drain layer is reduced. Alternatively, the shielding layer and the source/drain layer may be formed simultaneously so that the light leakage between lead lines connected to a gate layer is reduced. Furthermore, a common voltage may be applied to the shielding layer so that signal interference between lead lines is reduced. Moreover, in an electrical inspection of the thin film transistor array, any short circuit between the lead lines and the shielding layer can be determined.

Abstract: The invention relates to a method for operating a switching or amplifier device (11, 111), and to a switching or amplifier device (11, 111) comprising: an active material (13, 113) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts (12a, 12b, 12c).

Abstract: A light source arrangement for substantially enhaning the lighting intensity of the light beams emitted from the light source therefore includes a lens body and an illumination unit. The lens body has an illumination portion defining a light projecting surface and at least a diffraction portion defining a light diffraction surface inclinedly extended at a diffraction angle, wherein a diffraction density of the illumination portion is different from that of the diffraction portion. The illumination unit is covered by the lens body for radially generating light towards the illumination portion. When the light reaches the light diffraction surface of a diffraction portion at an angle larger than the diffraction angle, the light is substantially reflected at the light diffraction surface back towards the light projecting surface, such that the light from the illumination unit is converged to project at the light projecting surface of the lens body.

Abstract: At least two switching devices each including a substrate formed of a wide bandgap semiconductor, source and gate electrodes formed in a principal surface side of the substrate, and a drain electrode formed on the back surface of the substrate are stacked so that respective upper surface sides of the switching face each other.

Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).

Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.

Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: In a solid state image pickup apparatus with a photodetecting device and one or more thin film transistors connected to the photodetecting device formed in one pixel, a part of the photodetecting device is formed over at least a part of the thin film transistor, and the thin film transistor is constructed by a source electrode, a drain electrode, a first gate electrode, and a second gate electrode arranged on the side opposite to the first gate electrode with respect to the source electrode and the drain electrode, and the first gate electrode is connected to the second gate electrode every pixel, thereby, suppressing an adverse effect of the photodetecting device on the TFT, a leakage at turn-off TFT, variation in a threshold voltage of the TFT due to an external electric field, and accurately transferring photo carrier to a signal processing circuit.

Abstract: Disclosed herein is a solid-state imaging apparatus including: a pixel section having a plurality of pixels disposed two-dimensionally in rows and columns, each pixel containing a photoelectric conversion section and an amplifying section for amplifying output of the photoelectric conversion section to output pixel signals; a first scanning section for selecting a row to be read out of the pixel section; a noise suppressing section for effecting pixel-by-pixel noise suppression of the pixel signals; a second scanning section for selecting a column to be read out of the pixel section to cause the pixel signals processed through the noise suppressing section be outputted from a horizontal signal line; a first reference potential line for supplying a reference potential; and a second reference potential line separate from the first reference potential line.

Abstract: A photoelectric conversion device comprises: at least two electrodes; and an organic photoelectric conversion film intervening between said at least two electrodes, the organic photoelectric conversion film comprising a positive hole transporting material containing an arylidene compound having a specific structure.

Abstract: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may be a separate and individual transistor having the gate profile of a transfer gate or a reset gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor, adjusting the channel length of the transistor, or thinning the gate oxide on the transistor. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.

Abstract: A ferroelectric memory cell has a semiconductor substrate of a first conductivity type having a first region and a second region with each being of a second conductivity type, with a channel region therebetween. The first region and the second region are aligned in a first direction. A gate dielectric is over at least a portion of the channel region. A gate is over the gate dielectric, with the gate extending in a direction transverse to the first direction termination at a termination point not overlapping the first region, the second region and the channel region. A ferroelectric capacitor is at the termination point. The ferroelectric capacitor has a first end and a second end with the first end connected to the gate. The ferroelectric memory cell has three terminals: the first region, the second region, and the second end. In another embodiment, an insulator is over at least a portion of the first region.

Abstract: A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first conductive polymer layer disposed on the first electrode layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer. The module further includes a second set of layers including: an ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the ILD layer of the second set of layers; and a second electrode layer disposed on the second conductive polymer layer. The first conductive polymer layer and the second conductive polymer layer cover the electrode layers to provide a reaction and/or diffusion barrier between the electrode layers and the ferroelectric polymer layer.

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a mask when a pattern of the capacitor is formed, wherein an inclination of a side surface of the mask film is gentler than an inclination of a side surface of the top electrode and an inclination of a side surface of the dielectric film.

Abstract: The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, the insulating film including an opening portion, a surface strap embedded in the opening portion, the surface strap comprising a semiconductor layer, a reaction preventing film provided on the surface strap, the reaction preventing film comprising a material different from that of the insulating film, a storage electrode of a trench capacitor provided in the semiconductor substrate, the storage electrode connecting electrically with the surface strap, and a source/drain region provided on a surface of the semiconductor substrate, the source/drain region connecting electrically with the storage electrode via the surface strap.