Abstract: The invention relates to a microwave package delimiting an interior volume, comprising: a Faraday cage formed by a conducting surface surrounding the interior volume, a connection point placed outside the Faraday cage, the connection point being intended to be linked electrically to an exterior circuit, an input-output passing through the Faraday cage and linked electrically to the connection point, a base forming a face of the package, the exterior surface of the base forming a mounting surface intended to be applied to the exterior circuit, the connection point being placed on the mounting surface, so that the connection point is placed between the Faraday cage and the exterior circuit when the package is mounted on the exterior circuit. The invention applies to microwave packages used in the realms of avionics, telecommunications, space.

Abstract: Some embodiments relate to a semiconducting device that includes a substrate, a die and an interconnect device. The die and interconnect device are attached to an upper surface of the substrate. The semiconducting device further includes a first wire that is bonded to the substrate and to the interconnect device and a second wire that is bonded to the interconnect device and to the die. Other example embodiments include a stack of dice that has a bottom die attached to the upper surface of the substrate and a top die stacked onto the other dice in the stack of dice. The interconnect device is attached to an upper surface of any die in the stack of dice such that a first wire is bonded to the substrate and to the interconnect device and a second wire is bonded to the interconnect device and to the top die.

Abstract: A memory card. The memory card comprises a substrate, a plurality of electronic package devices, a molding compound and a plastic forming material. The substrate has at least a plurality of outer contacts and a plurality of inner contacts and the outer contacts are electively connected to the inner contacts. The electronic package devices are located on the substrate and the electronic package devices electively connect to the inner contacts, respectively. The molding compound is covering the electronic package devices and the corresponding inner contacts. The plastic forming material is covering the molding compound and the substrate, and the plastic forming material exposes the outer contacts.

Abstract: A cavity-down stacked multi-chip package with a plurality of packages stacked together is provided. The uppermost package has a circuit board with an opening, a heat spreader, and a chip. The heat spreader is positioned on the circuit board and covers the opening. The chip is positioned in the opening and adhered to a lower surface of the heat spreader. In addition, the chip is electrically connected to a lower surface of the circuit board through at least a conductive wire.

Abstract: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Abstract: An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls are reflowed on ball-grid-array pads at the top of the stack to provide external electrical connections.

Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.

Abstract: A method for manufacturing a semiconductor device including: fixing each of a plurality of semiconductor substrates onto a surface of a wiring substrate in which a perforation is formed in advance; covering the surface of the wiring substrate with a metal mold having a protrusion on an inner surface along the perforation; wholly sealing the plurality of semiconductor substrates with a sealing resin by introducing the sealing resin into the metal mold while forming a thin region in the sealing resin along the perforation; and dividing the wiring substrate into a plurality of chips by splitting the wiring substrate and the sealing resin along the perforation in the wiring substrate and the thin region in the sealing resin.

Abstract: In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

Abstract: Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and an I/O circuit is connected to the second bonding pad. First and second bonding wires connect the first and second bonding pads to the same package pin, respectively. The second bonding wire is configured to be sufficiently longer than the first bonding wire, regardless of the pitch of the first bonding pads.

Abstract: To provide an excellent image by reducing buckling of a CCD device having one-dimensional CCD elements mounted thereon due to changes in temperature. Blackening treated iron or iron-based alloy is used as a material of a heat sink 11 having a one-dimensional CCD element 14 mounted thereon. The thermal coefficient of expansion of the heat sink 21 is matched with that of a hollow molded case 12 for integrally molding the heat sink 11 and a lead frame 20. A plurality of projections 21 formed on the side of the hollow molded case 12 are disposed at a bonding interface between the glass cap 13 which closes an upper opening of the hollow molded case 12 and side walls of hollow molded case 12.

Abstract: An automatic trace determination apparatus for automatically determining optimal positions of traces from pads to corresponding vias on a substrate using computation comprises: tentative determination means for tentatively determining a tentative target line with which tentative positions of bending points of traces are aligned; and final determination means for determining a final target line by correcting the tentative target line so that at least clearances between the adjacent traces and between the traces and vias adjacent to the corresponding traces can be secured, wherein the positions of intersection of the determined final target line and the traces from the pads are determined as bending points of the traces.

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1) having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties.

Abstract: Microelectronic packages having chambers and sealing materials, and methods of making the packages, and sealing the chambers, are disclosed. An exemplary package may include a first surface, a second surface, a solid sealing material including an intermetallic compound, such as, for example, of gallium or another relatively low melting material, between the first surface and the second surface, and a chamber defined by the first surface, the second surface, and the sealing material. An exemplary method may include disposing a ring of a sealing material including a liquid metal between a first surface and a second surface to define a chamber between the first surface, the second surface, and the ring of the sealing material, and sealing the chamber by heating the sealing material to react the liquid metal with a metal that is capable of forming an intermetallic compound with the liquid metal.

Abstract: A semiconductor device is provided with a heat dissipation metal plate which improves heat dissipation performance in heat generating members of a semiconductor element and the like. In particular, the heat dissipation metal plate is placed on a surface of an insulating film, the surface being located on an opposite side to the semiconductor element. This plate makes it possible to provide the semiconductor device and an electronic apparatus with the same demonstrating the superiority in heat dissipation performance when heat is discharged from the semiconductor element and the like.

Abstract: A method and apparatus for cooling an electronics chip with a cooling plate having integrated micro channels and manifold/plenum made in separate single-crystal silicon or low-cost polycrystalline silicon. Forming the microchannels in the cooling plate is more economical than forming the microchannels directly into the back of the chip being cooled. In some embodiments, the microchannels are high-aspect-ratio grooves formed (e.g., by etching) into a polycrystalline silicon cooling base, which is then attached to a cover (to contain the cooling fluid in the grooves) and to the back of the chip.

Abstract: A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.

Abstract: A semiconductor substrate structure with a highly heat-conductive advantage increases packaging good rate and quality. Using semiconductor chip packaging, an electronic chip is easily made highly heat-conductive, and compared with the prior art, the present invention has superior good rate for substrate structure. The improved heat-conductive structure avoids the semiconductor chip overheating and affects the life of electronic device by directly connecting the chip to the heat-conductive base plate.

Abstract: In a chip package (10, 10?, 110, 210), first and second electrical power buses (14, 14?, 16, 16?, 114, 116, 214, 216) are each formed of an electrical conductor having a chip bonding portion (20, 22, 120, 122, 220, 222) and a lead portion (26, 26?, 28, 28?, 126, 128, 226, 228) extending away from the chip bonding portion. The chip bonding portions of the first and second electrical power buses have edges (32, 34, 132, 134, 232, 234) spaced apart from one another to define an extended electrical isolation gap (40, 140, 240). A plurality of chips (42, 44, 46, 142, 143, 144, 145, 146, 147, 148, 242) straddle the extended electrical isolation gap and are electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.

Abstract: A semiconductor package which is multifunctional, thin, and high in mounting reliability includes an insulating film; a first electronic component formed on one of the main surfaces of the insulating film; a second electronic component formed outwardly on the other of the main surfaces opposite to the one of the main surfaces; an external output terminal formed outwardly on the other of the main surfaces; and internal wiring formed in the insulating film so as to provide electrical continuity between the external output terminal and each of the first electronic component and the second electronic component. The insulating film is composed of a first insulating film and a second insulating film opposite to each other; the internal wiring is interposed between the first insulating film and the second insulating film, and the protruding end of the external output terminal is outside beyond the protruding end of the second electronic component.

Abstract: In a pressing cap forming part of a semiconductor device carrier unit, a pressing portion of a pressure body has recesses, to each of which a bump is inserted.

Abstract: An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to-face bonding pads of each member of the other set.

Abstract: A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.

Abstract: A semiconductor device uses a carbon nanotube structure, which reduces an electric resistance and a thermal resistance by increasing a density of the carbon nanotubes. An insulation film covers a first electrically conductive material. A second electrically conductive material is provided on the insulation film. A plurality of carbon nanotubes extend through the insulation film by being filled in an opening part that exposes the first electrically conductive material. The carbon nanotubes electrically connect the first electrically conductive material and the second electrically conductive material to each other. Ends of the carbon nanotubes are fixed to a recessed part provided on a surface of the first electrically conductive material.

Abstract: A semiconductor device comprises a semiconductor integrated circuit, an external connection terminal connecting the semiconductor integrated circuit to an external device, and a plurality of tin or tin-alloy plating layers formed on the external connection terminal as multiple unleaded metal plating layers. The multiple unleaded metal plating layers comprise a first layer made of a tin alloy and provided as an inner layer of the multiple unleaded metal plating layers, the tin alloy of the first layer containing as a second element one of bismuth, silver, copper, indium, and zinc, and a second layer made of either 100% tin or a tin alloy and provided as an outer surface layer of the multiple unleaded metal plating layers, the 100% tin or the tin alloy of the second layer having a percentage of tin content greater than that of the first layer.

Abstract: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: An electronic structure includes an electronic device coupled to a substrate by conductive bumps and ball limiting metallurgy (BLM). Underfill material having filler particles is disposed in a space between the electronic device and the substrate. A weight percentage of the filler particles is at least about 60%. A particle size of at least 90 wt % of the filler particles is less than about 2 ?m and/or the filler particles are coated by an organic coupling agent. Once the underfill material is fully cured, its coefficient of thermal expansion is no more than 30 PPM/° C., and its glass transition temperature is at least 100° C., and its adhesion to a passivation layer of the electronic device, to the substrate and to the electronic device at its edges is such that the electronic structure passes standardized reliability tests without delamination of the ball limiting metallurgy.

Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.

Abstract: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.

Abstract: Metal alloy barrier layers formed of a group VII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as a barrier layer over copper bumps that are soldered to a tin-based solder in a die package. Such barrier layers may also be used as barrier layer liners within trenches in which copper interconnects or vias are formed and as capping layers over copper interconnects or vias to prevent the electromigration of copper.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

Abstract: A semiconductor device is configured of a semiconductor chip which is sandwiched by first and second resin films having a wiring pattern. Plural semiconductor chips can be fabricated collectively by sandwiching the semiconductor chips by the first and second resin films, and productivity can be improved.

Abstract: Disclosed is a wiring connection structure comprising a wiring on which a preferable carbon nanotube can be formed, and a method for forming the same. On a lower layer Cu wiring, Mo is deposited to form a connection layer. On this connection layer, a carbon nanotube is grown using a CVD method. When the connection layer composed of Mo is formed, the following advantages can be obtained. Even when heat is applied during the CVD for growing the carbon nanotube, thermal diffusion of Cu in the lower layer Cu wiring is suppressed so that activity of the catalyst metal can be kept. Further, since the contact resistance between Mo and the carbon nanotube is low, a low resistance connection between the lower layer Cu wiring and the carbon nanotube can be secured and at the same time, a preferable carbon nanotube can be formed.

Abstract: A stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer. The copper interposer significantly reduces the warping of the stacked die IC assembly caused by the warping of the substrate due to thermal changes in the substrate. The copper interposer has a significantly higher coefficient of thermal expansion than a conventional silicon (Si) interposer. The higher CTE enables the copper interposer to counteract the substrate warping.

Abstract: A semiconductor device, includes: a circuit board having an inner terminal on one surface, an outer terminal on the other surface, and wiring between the inner terminal and the outer terminal; a semiconductor chip flip-chip bonded to the inner terminal against the circuit board; and a sealing resin covering the semiconductor chip and having a side portion of a diced surface that is the same as a side portion of the circuit board.

Abstract: In a semiconductor device and a fabrication method thereof according to the present invention, a second insulating film is formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a portion of the second insulating film directly below the electrode pad. By using the second insulating film as a mask, a through hole is formed in the semiconductor substrate in such a manner that the through hole recedes from an opening edge of the first insulating film. A third insulating film is formed only on the inner wall of the through hole. The opening edge of the second insulating film and the inner periphery surface of the third insulating film coincide as viewed from the second surface side of the semiconductor substrate.

Abstract: A housing having a non-detachable bond to a micromechanical component using a flexible bonding material in particular. The combination including the housing and the micromechanical component as well as the manufacturing method of this combination. At least part of the component and/or of the housing has depressions for receiving the bonding material. These depressions may be designed as grooves, for example.

Abstract: A semiconductor device, comprising: a flexible substrate; at least one semiconductor element; at least one electrode for external connection, the element and the electrode being formed on a front surface of the flexible substrate; and at least one wire formed on the front surface to electrically connect the element to the electrode, wherein at least a part of the flexible substrate has a curved form.

Abstract: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer.

Abstract: A semiconductor package comprising a chip, a die pad adjacent the chip, said die pad having a side facing away from the chip, a portion of said side separated from an adjacent package surface by a distance greater than zero. The package further comprises mold compound abutting the chip and the die pad, wherein the distance between said portion and said adjacent package surface varies.

Abstract: A polycrystalline silicon GOLDD TFT with a gate (10) overlying its channel (11) is fabricated by using the gate (10) as a mask during a first dopant implantation step. Spacers (13, 14) are then formed adjacent to the gate (10), which comprise portions of a thin metallic layer (19) which are defined by fillets (17) in an etching process. The spacers and gate are then used as a mask for doping source and drain regions, thereby providing a self-aligned fabrication technique.

Abstract: An automatic plate feeding system for loading plates of various sizes into a printing plate imaging device, which includes a plurality of trays staggered one on top of the other is provided. At least two of the trays contain plates of different sizes stacked with their sensitive side downward. Separation papers are interposed between the plates. The automatic plate feeding system includes suction cups, which touch the non-sensitive surface of the plate, and a loading mechanism for loading plates from the trays and feeding the loaded plates to the imaging device.

Abstract: An optic is produced by the steps of placing a polymer inside a rotateable cylindrical chamber, the rotateable cylindrical chamber having an outside wall, rotating the cylindrical chamber, heating the rotating chamber forcing the polymer to the outside wall of the cylindrical chamber, allowing the rotateable cylindrical chamber to cool while rotating producing an optic substrate with a substrate surface, sizing the optic substrate, and coating the substrate surface of the optic substrate to produce the optic with an optic surface.

Abstract: Invisible bifocal sunglasses. The sunglasses include a hard mirror coating to disguise the different focal powers of the sunglasses. The bifocal sunglasses also include a bifocal region that is molded within the main lens blank of the sunglasses.

Abstract: A method and apparatus for separating excess cured lens material, or lens flash, from the mold section in which it was cast. This invention is particularly suited for cast contact lenses or intraocular lenses.

Abstract: An apparatus and method for encapsulating a liquid or suspension within a polymeric shell to form a microcapsule of a selected size ranging from approximately 0.1 ?m to 1000 ?m in diameter. The apparatus preferably has a laminar flow of air through a channel and ultrasonic atomizer with the head oriented at approximately ninety degrees from the laminar flow. Emulsions, liquids or thin films of core and shell materials are atomized and the formed microcapsules are exposed to ultraviolet light or additionally infrared light to cure the polymer shell and then are collected. A variety of capsule morphologies can be created by the choice of materials and process conditions to achieve desired controlled or programmed release kinetics. Surface functionalization of the outer shell of the microcapsules capsules can also be achieved to facilitate targeted delivery.

Abstract: An apparatus for supplying differently colored polyurethane forming materials includes a source of isocyanate, a source of polyol, multiple colorant sources for supplying multiple colorants, and multiple premix chambers that are each connected to a respective colorant source and one of the source of isocyanate and the source of polyol. Each premix chamber has a mixing element for mixing a respective colorant and one of isocyanate and polyol to form a selectively colored material. The apparatus further includes a spray head in communication with the premix chambers and the other of the source of isocyanate and the source of poloyl, and a valve assembly disposed between the spray head and the premix chambers for selectively introducing selectively colored material from one of the premix chambers and the other of isocyanate and polyol to the spray head.

Abstract: A powder which is capable of being used in a layer-by-layer process in which regions of the respective pulverulent layer are selectively melted and, after cooling, are fixed, contains a mixture of diacid-regulated polyamide and diamine-regulated polyamide and/or diacid-regulated copolyamide and diamine-regulated copolyamide.

Abstract: An apparatus for scarfing a fibrous web includes a rotatable scarfing roll with vacuum ports and an air moving source in fluid communication with the vacuum ports. The rotatable scarfing roll has a core member which includes a plurality of scarfing elements connected thereto and vacuum ports located therein. A method for scarfing a fibrous web includes providing a rotatable scarfing roll with vacuum ports and reducing scarfing wind by applying vacuum to the vacuum ports. A method for producing absorbent articles includes providing a fibrous web, contacting the fibrous web with a rotatable scarfing roll with vacuum ports to remove a portion of the fibrous web, applying vacuum to the vacuum ports to reduce scarfing wind, and producing an absorbent article with the fibrous web.