Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor and a method for fabricating the same are provided. The CMOS image sensor includes: a pixel region provided with a plurality of unit pixels, each including a buried photodiode and a floating diffusion region; and a logic region provided with CMOS devices for processing data outputted from the unit pixels, wherein a self-aligned silicide layer is formed on gate electrodes and source/drain regions of the CMOS devices in the logic region while a self-aligned silicide blocking layer is formed over the pixel region.

Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.

Abstract: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: A semiconductor device, such as a metal-oxide semiconductor field-effect transistor, includes a semiconductor substrate, a drift layer formed on the substrate, a first and a second source region, and a JFET region defined between the first and the second source regions. The JFET region may have a short width and/or a higher concentration of impurities than the drift layer. The semiconductor device may also include a current spreading layer formed on the drift layer. The current spreading layer may also have a higher concentration of impurities than the drift layer.

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

Abstract: A bonded assembly is provided. The bonded assembly comprises: (a) a first substrate having a plurality of etched trenches defined in a first bonding surface; and (b) a second substrate having a second bonding surface. The second bonding surface is bonded to the first bonding surface with an adhesive and the adhesive is received, at least partially, in the plurality of etched trenches. Semiconductors chips bonded to a second substrate exemplify the advantages of the invention. The etched trenches allow the adhesive bond to be strengthened whilst avoiding increased surface roughening.

Abstract: A process for packaging a number of micro-components on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a covering plate comprising a re-useable matrix, a polymer layer, and a metal layer; covering the wafer with the covering plate; applying a contact pressure equal to at least one bar on the covering plate and on the wafer; heating the metal layer during pressing until sealing is obtained, each cavity thus being provided with a sealing area and closed by metal layer; and dissolving the polymer to recover and recycle the matrix.

Abstract: An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation region damages can be avoided.

Abstract: Unit cells 2n1 and 2n2 arranged two-dimensionally in a row direction and a column direction includes a cell with four pixels as a set arranging pixels having an oblong shape and lengthwise shape alternatively with floating junctions FJ1 and FJ2 taken as centers; a plurality of reading transistors (Tr1 to Tr4) connected to the floating junction; reset transistors Tr15 and Tr25 arranged at one row end portion between the cells in the adjacent row directions, and address transistors Tr17 and Tr27 arranged at the other row end portion; amplifier transistors Tr16 and Tr26 connected in series to this address transistor, and moreover, arranges a reset wire ADD/RST-2 between the rows of the unit cell arranged in the row direction.

Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.

Abstract: In a contact assembly, a first set of contacts (30-1 through 30-5) is arranged on a first surface and a second set of contacts (40-5 through 4-1) is arranged on a second surface with respective contacts of each set used as pairs. A plurality of first and second sets are stacked one on top of another separated by insulators, the first terminal portions (12) of respective first and the second sets of contacts are aligned in the direction of stacking and the second terminal portions (20) of the first and second sets of contacts are arranged in such a fashion as to be symmetrical relative to a median line. The pitch (P2) of the second terminal portions (20) of the first and the second sets of contacts is expanded to a greater degree than the pitch (P1) of the first terminal portions (12) in two preferred embodiments.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: An inductor fabricated with a dry film resist and a cavity and a method of fabricating the inductor. The cavity can be formed in a substrate to minimize a parasitic capacitance generated by structures of upper electrodes, an insulating layer, and a lower electrode and minimize energy loss caused by an eddy current generated through the substrate. Also, a process of forming and planarizing the cavity can be simplified so as to form the cavity to a sufficient depth. As a result, an inductor having a high quality factor and a high self resonant frequency can be fabricated. Also, a scheme for simply forming and planarizing a cavity is contemplated.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layers (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.

Abstract: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

Abstract: A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.

Abstract: A hermetically sealed microelectromechanical system (MEMS) package includes a MEMS switch having a movable portion and a stationary portion with an electrical contact thereon. A glass lid is anodically bonded to the MEMS switch to form a sealed cavity over the movable portion of the MEMS switch. The glass lid includes a contact aperture to allow access to the electrical contact on the stationary portion of the MEMS switch. A family of body-implantable hermetically-sealed MEMS packages are provided according to certain aspects and embodiments of the present invention.

Abstract: An integrated circuit (IC) package 100 comprises an IC 102 and leads 104 coupled to the IC. Each lead has a first end 106 configured to be coupled to the integrated circuit and a second end 108 configured to pass through one of a plurality of mounting holes 110 extending through a mounting board 112. The leads comprise at least one positioning lead 114 comprising a stop 118 being a continuous part of the positioning lead and having a lateral dimension 120 greater than a diameter 122 of a first hole 124 of the plurality of mounting holes. The leads further comprise at least one non-positioning lead 116 having a continuous uniformly shaped body 130 with a lateral dimension 132 less than a diameter 134 of a second hole 136 of the plurality of mounting holes. The stop limits an extension of the non-positioning lead through the second hole.

Abstract: A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along an edge of the package, and in some embodiments in a row along each of the four edges of the package. The leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other; in a plan view, the leads of the first leadframe appear to be interdigitated with the leads of the second leadframe. The input/output contact portions of the first leadframe are exposed in a row of first contacts near or, usually, at the edge of the package, and the input/output contact portions of the second leadframe are exposed in a row of second contacts inboard from the row of first contacts.

Abstract: Apparatus and center pad die and substrate assemblies configured to provide for molding, in a single molding step, both an attached center pad die and other features on a die attach side of the substrate, and wire bonds an associated bond pads and other features on the opposite side of the substrate. Also, methods for sealing a center pad die and substrate assembly, including such a molding step.

Abstract: In a wireless IC tag, on which an integrated circuit and a small antenna are integrally mounted, a radiation-shielding material covers only the integrated circuit (IC chip) portion. Thus, the area of the small antenna covered by the radiation-shielding material is minute, and it is possible to minimally suppress a reduction in antenna gain of the small antenna. Such a wireless IC tag has radiation-shielding properties.

Abstract: A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern on a top surface, the other set contacts a pattern on a bottom surface of the flex substrate within a same end portion. The other end portion has a conductive pattern, and is connected to a third set of electrical contacts. The flex substrate is wrapped around an edge of the chip package to connect the third set with the other two sets. Thereby, four chip packages are provided with this design, the layout of conductive traces formed within at least one of the flex substrates is meandered to compensate for length differences with respect to the other flex substrate.

Abstract: An interface module for connecting LSI packages includes a connecting member which is to be mounted on an LSI package including an LSI chip and which includes lines to be electrically connected to the LSI package, an optoelectronic transducer which is mounted on the connecting member, which is connected to the lines of the connecting member, and which converts optical signal to electric signal or converts electric signal to optical signal, an optical waveguide which includes an optical input end and an optical output end, one of which is optically connected to the optoelectronic transducer, and a reinforcing film which is adhered to the optical waveguide, covering at least one side of the optical waveguide, and which is secured at one end to the connecting member.

Abstract: A stacked image sensor package contains an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is enhanced by exposing surfaces including a back surface of the peripheral chip.

Abstract: A method of forming polymer reinforced solder-bumped containing device or substrate is described. The method comprises the following steps: providing a device or substrate having at least one solder bump formed thereon; coating a predetermined portion of the device or substrate with a curable polymer reinforcement material forming a layer on the device or substrate, partially curing the curable polymer reinforcement material to provide a solder-bumped structure comprising a partially cured polymer reinforcement material, and, making a connection between the solder-bumped structure formed and a printed circuit board or array of attachment pads and fully curing the partially cured polymer reinforcement material to provide a reinforced interconnection. Full curing of the polymer reinforcement material may take place either during the “reflow step” or subsequent to it (post-curing).

Abstract: Microelectronic packages having chambers and sealing materials, and methods of making the packages, and sealing the chambers, are disclosed. An exemplary package may include a first surface, a second surface, a solid sealing material including an intermetallic compound, such as, for example, of gallium or another relatively low melting material, between the first surface and the second surface, and a chamber defined by the first surface, the second surface, and the sealing material. An exemplary method may include disposing a ring of a sealing material including a liquid metal between a first surface and a second surface to define a chamber between the first surface, the second surface, and the ring of the sealing material, and sealing the chamber by heating the sealing material to react the liquid metal with a metal that is capable of forming an intermetallic compound with the liquid metal.

Abstract: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.

Abstract: An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a wafer edge ring is formed with a spin coating apparatus provided with a wafer edge exposure (WEE) system. In further embodiments, a wafer edge ring is used to contain a liquid over a wafer active surface during a processing operation. In one embodiment, the wafer edge ring contains a liquid having a higher refractive index than air while exposing a photoresist on the wafer by immersion lithography. In another embodiment, the wafer edge ring contains a curable liquid material while forming a chip scale package (CSP) sealing layer on the wafer.

Abstract: A manufacturing method of forming an encapsulation layer on a back surface of a wafer, the method comprising the steps of: providing the wafer having the back surface and an active surface opposing to the back surface; providing an encapsulation disposed only on the back surface of the wafer, and not disposing the encapsulation over the active surface of the wafer; providing a mold having a mold surface disposed over the encapsulation; heating the mold and moving the mold surface to press the encapsulation simultaneously so as to have the encapsulation distributed over the back surface of the wafer to form the encapsulation layer on the back surface of the wafer; and singulating the wafer into a plurality of chips, wherein the encapsulation layer is formed on a back surface of each chip, and is not formed on a side surface of each chip.

Abstract: An electronic device has external contact elements projecting from at least one external contact side of a plastic housing. The external contact elements have an internal section and an external section. The external section has an external contact region tapering away from the external contact side. An external contact element of this type improves the possibilities of a soldering connection to circuit carriers of superordinate circuits.

Abstract: Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed on the face side of a layer insulation film and a contact hole provided at a bottom portion of the wiring trench. The layer insulation films constituting the plurality of wiring layers are so configured that the layer insulation films are changed in the magnitude of mechanical strength alternately on a wiring layer basis in the lamination direction of the wiring layers.

Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate comprises a first interconnection pattern formed of the first interconnection which comprises at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

Abstract: A method of providing shield interconnection, the method shielding an interconnection pattern to be shielded with shield interconnection patterns for shielding on the substrate of a semiconductor integrated device, is disclosed. The method includes the steps of disposing multiple interconnection layers having the corresponding shield interconnection patterns formed therein so that the interconnection layers surround the interconnection pattern to be shielded; setting different potentials for at least a first one of the shield interconnection patterns formed in a first one of the interconnection layers and a second one of the shield interconnection patterns formed in a second one of the interconnection layers; and shielding the interconnection pattern to be shielded with the first one and the second one of the shield interconnection patterns.

Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: An electronic device according to an embodiment of the invention includes a pair of members which are connected to each other by a connecting portion layer interposed between connecting portions respectively formed thereon and have thermal expansion coefficients different from each other, wherein the connection layer is formed by diffusion reaction between the metal layers by which the metal layers are melted only in the vicinity of a contact interface between the layers, the metal layers being formed on the connecting portions with materials different from each other. At least one of the metal layers is formed by plating, thereby the connection layer is formed in a thickness sufficient to absorb difference in thermal expansion coefficient between the pair of members.

Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

Abstract: An electronic device comprises a semiconductor device having a package substrate with bumps. The semiconductor device is bonded to a mounting substrate by flip-chip bonding. A standoff member supports the package substrate on the mounting substrate with a predetermined standoff between the package substrate and the mounting substrate. The standoff member comprises a hole provided in the mounting substrate, an insertion portion provided to be contained in the hole, and a standoff portion provided to contact and support the package substrate such that the standoff portion has a height, equivalent to the predetermined standoff, on the mounting substrate and enables relative displacement of the package substrate to the mounting substrate.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: A chip carrier includes a first surface and a second surface that opposes the first surface. The chip carrier acts as a heat sink for semiconductor chips arranged on it. A first recess is provided in the first surface, and a second recess is provided in the second surface. First and second semiconductor chips are respectively received in the first and second recesses.

Abstract: In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.

Abstract: A semiconductor device with surface-mountable outer contacts and to a process for producing it is disclosed. In one embodiment, surface-mountable outer contacts are arranged on outer contact connection surfaces on the underside of the semiconductor device. In their respective center region, the outer contact connection surfaces have at least one recess which has a dovetail-like profile, the areal extent of the recess being smaller than the maximum cross section of an outer contact. In a one process, the recess in the center region is achieved by selective deposition of correspondingly patterned metal layers.

Abstract: A manufacturing method for electronic device, includes: forming a first interconnection on a substrate; disposing a pedestal having a predetermined shape on the substrate; and forming a second interconnection connecting to the first interconnection, extending onto the pedestal.