Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

Abstract: Systems and methods for at or near room temperature of infrared detection are disclosed. Embodiments of the disclosure include high temperature split-off band infrared detectors. One embodiment, among others, comprises a first barrier and a second barrier with an emitter disposed between the first and second barrier, each barrier being a layer of a first semiconductor material and the emitter being a layer of a second semiconductor material.

Abstract: The semiconductor layer structure includes an active layer (6) and a superlattice (9) composed of stacked layers (9a, 9b) of III-V compound semiconductors of a first (a) and at least one second type (b). Adjacent layers of different types in the superlattice (9) differ in composition with respect to at least one element. The layers (9a, 9b) have predefined layer thicknesses, such that the layer thicknesses of layers (9a) of the first type (a) and of the layers (9b) of the second type (b) increase from layer to layer with increasing distance from an active layer (6). An increasing layer thickness within the layers of the first and the second type (a, b) is suitable for adapting the electrical, optical and epitaxial properties of the superlattice (9) to given requirements in the best possible manner.

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Abstract: An apparatus includes a first solid electrode on a substrate, a polyelectrolyte layer over a part of the first solid electrode, a second solid electrode on a portion of the polyelectrolyte layer, and an anchoring layer on the part of the first solid electrode. The polyelectrolyte layer is either chemically bonded to the anchoring layer or has a thickness of less than about 20 nanometers.

Abstract: Substrate structures and fabrication methods thereof. A substrate structure includes a bendable substrate and an inorganic electrode structure on the bendable structure, wherein the inorganic electrode structure includes a conductive layer or a semiconductor layer. The inorganic electrode structure includes carbon nanotubes, carbon nanofibers, a nanolinear material, or a micro-linear material. The bendable substrate includes polyethylene (PE), polyimide (PI), polyvinyl alcohol (PVA), or polymethyl methacrylate (PMMA).

Abstract: Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an electrode formed on the molecular active layer. The organic dielectric thin film may be immobilized on the electrode or a Si layer by a self-assembled method. The organic dielectric thin film may include first and second molecular layers bound together through hydrogen bonds. An organic compound may be self-assembled over the substrate to form the organic dielectric thin film. The organic compound may include an M?-R-T structure, where M?, R and T represent a thiol or silane derivative, a saturated or unsaturated C1 to C20 hydrocarbon group which is substituted or unsubstituted with fluorine (F), and an amino(—NH2) or carboxyl (—COOH) group, respectively.

Abstract: A thin-film transistor and fabrication method thereof are provided. A controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. At least two organic thin-film transistors are formed on two ring ridges of the coffee rings. For example, N-type and P-type soluble semiconductor materials may be formed on two adjacent ring ridges to form a complementary metal-oxide semiconductor (CMOS) device. Thus, the invention can simplify the process for fabricating thin-film transistors and increase their applications.

Abstract: The present invention relates to the use of perylene diimide derivatives as air-stable n-type organic semiconductors.

Abstract: A semiconductor component includes at least one surface, at least one trench formed in the at least one surface and at least one edge structured and arranged on the at least one surface and formed by the at least one trench. Additionally, the semiconductor component includes an electric contact arranged on the at least one edge, wherein the at least one surface provides for at least one of electric and optical power input and output to the semiconductor component.

Abstract: A wafer test is performed to a wafer, and then a protective film is applied to part of a chip surface of each good chip other than terminals. For defective chips, a protective film is applied to an entire chip surface as well as terminals and, while keeping that state, a burn-in test is performed, thereby cutting off power supply and signal application to defective chips before burn-in test. Moreover, when a chip includes a self-test circuit to judge whether the chip is good or not and the chip is judged to be defective, the function of stopping an internal operation of the chip may be provided or a judgment signal may be transmitted to a burn-in test apparatus, thereby stopping power supply and signal application from the burn-in test apparatus. Thus, power supply and signal application to a chip judged to be defective after burn-in can be cut off.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window.

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are disposed on the substrate and define a plurality of pixel regions. A plurality of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A plurality of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract: The invention provides a display device and an electronic device, each of which has one of a structure in which a substrate provided with a light emitting element which performs bottom light emission and a substrate provided with a light emitting element which performs top light emission are attached, and a structure in which two substrates, each of which is provided with a light emitting element which performs bottom light emission are attached. By attaching two substrates, each of which is provided with a light emitting element, displays are provided on the front and back of the display device, thus a high added value can be realized. One of the two substrates, each of which is provided with a light emitting element also functions as a sealing substrate for another substrate, thus a compact, thin, and lightweight display device can be obtained.

Abstract: A thin film semiconductor device is provided. The semiconductor device includes a semiconductor thin film configured to have an active region turned into a polycrystalline region through irradiation with an energy beam, and a gate electrode configured to be provided to traverse the active region. Successive crystal grain boundaries extend along the gate electrode in a channel part that is the active region overlapping with the gate electrode, and the crystal grain boundaries traverse the channel part and are provided cyclically in a channel length direction.

Abstract: A display apparatus includes a silicon oxide film and a silicon nitride film as a base layer placed on an insulating substrate, a polycrystalline silicon electrode placed on the base layer, a gate insulating film placed on the polycrystalline silicon electrode, and a gate metal electrode placed on the gate insulating film at a position opposite to the polycrystalline silicon electrode. The gate metal electrode partly or entirely covers the edge of the polycrystalline silicon electrode when viewed from the top.

Abstract: A display device according to an embodiment of the present invention includes: an interlayer insulating film; a signal line formed above the interlayer insulating film in the display region and supplying a signal or power from a peripheral region to a TFT; a passivation film formed above the signal line; an organic planarization film formed in the display region above the passivation film; and an upper conductive film 15 formed above the organic planarization film, two or more inorganic insulating films being formed between the signal line and the upper conductive film in a non-planarized region not including the planarization film in the peripheral region.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: A semiconductor memory device that is configured with a Si substrate layer, a SiC layer and a Si oxide layer, including a structure in which the SiC layer is layered onto the Si substrate layer and the Si oxide layer is layered onto the SiC. Wherein, the Si oxide layer includes two or more layers whose compositional ratios of SiO2 are different in a direction of layers, and a compositional ratio of SiO2 in the. Si oxide layer that is distanced most from the SiC layer is more than other layers.

Abstract: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer.

Abstract: A semiconductor light-emitting device capable of preventing fusion bonding between electrodes or damage to an electrode, and a method of manufacturing the same are provided. A semiconductor light-emitting device includes a semiconductor layer and a first electrode on a first surface of a semiconductor substrate in order from the semiconductor substrate side and a second electrode on a second surface of the semiconductor substrate, the semiconductor layer including a light-emitting region, the first electrode being arranged corresponding to at least the light-emitting region, wherein a recessed section with a depth larger than the thickness of the second electrode in arranged on the second surface, thereby a step section projected from the recessed section is formed in a region other than the recessed section in the second surface, and the second electrode is formed on a least the recessed section of the second surface.

Abstract: A semiconductor device includes a plurality of light emitting elements formed of a thin layer of a compound semiconductor and arranged in a row in one direction with an equal interval therebetween. Each of the light emitting elements includes a light emitting area formed on a surface thereof; a first conductive type side electrode formed on the surface and electrically connected to one side of the light emitting element; and a second conductive type side electrode formed on the surface and electrically connected to the other side of the light emitting element. Further, the first conductive type side electrode is disposed at a position continuously surrounding at lease two sides of the light emitting area of the light emitting area with an insulating film inbetween. The second conductive type side electrode is disposed on the light emitting area.

Abstract: An edge-emitting light-emitting diode comprises a base, a frame, and at least two chips. The base has a recessed cup on the front side. The frame is fixed on the inside of the recessed cup. The chips are electrically connected to the frame inside the recessed cup. The frame has a plurality of bended pins extending therefrom. The bended pins are arranged interlacedly, symmetrically on the lateral surface of the base toward opposite directions. As a result, the edge-emitting light-emitting diode can be placed steadily.

Abstract: An optocoupler has an organic light emitter and an inorganic photodetector with a detector area, the detector area being optically coupled to the organic light emitter. The organic light emitter converts an electrical input signal into a light signal and the inorganic photodetector converts the light signal into an electrical output signal, the organic light emitter and the inorganic photodetector being integrated in a component and galvanically separated.

Abstract: A reflex coupler has an organic light emitter for generating a light signal and an inorganic photodetector with a detector area. The organic light emitter and the detector area are optically coupled as a result of radiation returned from an object onto which the light signal impinges, and the organic light emitter and the inorganic photodetector are integrated in one device.

Abstract: The semiconductor laser device includes an active layer, a p-type cladding layer, and a p-type cap layer. The layers are sequentially stacked so that the semiconductor laser device is provided. The p-type cap layer includes both a p-type dopant and an n-type dopant. In another aspect, the p-type cap layer includes a first layer including a first p-type dopant and a second layer including a second p-type dopant having a diffusion coefficient smaller than that of the first p-type dopant. The first layer is far from the active layer, and the second layer is close to the active layer. In further aspect, the p-type cap layer includes carbon (C) as a p-type dopant. According to these configuration, the p-type dopant can be prevented from being diffused in the active layer and the p-type cladding layer.

Abstract: A light-emitting device includes a substrate, a first nitride semiconductor stack formed on the substrate, a nitride light-emitting layer formed on the first nitride semiconductor stack, a second nitride semiconductor stack formed on the nitride light-emitting layer, and a first transparent conductive oxide layer formed on the second nitride semiconductor stack. The second nitride semiconductor stack includes a plurality of hexagonal-pyramid cavities formed in an upper surface of the second nitride semiconductor stack. The plurality of hexagonal-pyramid cavities of the second nitride semiconductor stack are filled with the first transparent conductive oxide layer, and a low-resistance ohmic contact is generated at the inner surfaces of the plurality of hexagonal-pyramid cavities so as to decrease the operation voltage and improve light-emitting efficiency of the light-emitting device.

Abstract: A method of forming an LED lamp with a desired distribution of phosphor is disclosed. The method includes the steps of mixing a plurality of phosphor particles in an uncured polymer resin for which the viscosity can be controlled in response to temperature to form a substantially uniform suspension of the phosphor particles in the resin. The uncured resin is then placed into a defined position adjacent an LED chip and the temperature of the resin is increased to correspondingly decrease its viscosity but to less than the temperature at which the resin would cure unreasonably quickly. The phosphor particles are encouraged to settle in the lowered-viscosity resin to a desired position with respect to the LED chip, and the temperature of the resin is thereafter increased to the point at which it will cured and solidify.

Abstract: In a light emitting package (8), at least one light emitting chip (12, 14, 16, 18) is supported by a board (10). A light transmissive encapsulant (30) is disposed over the at least one light emitting chip and over a footprint area (32) of the board. A light transmissive generally conformal shell (40) is disposed over the encapsulant and has an inner surface (44) spaced apart by an air gap (G) from, and generally conformal with, an outer surface (34) of the encapsulant. At least one phosphor (50) is disposed on or embedded in the conformal shell to output converted light responsive to irradiation by the at least one light emitting chip. A thermally conductive filler material disposed in the generally conformal shell (40) is effective to enhance a thermal conductivity of the composite shell material to a value higher than 0.3 W/(m.K).

Abstract: A light emitting apparatus having a light source for emitting short wavelength radiation and an optic device configured to receive the radiation emitted from the light source. A device directs at least some of the short wavelength radiation emitted from the light source into the optic device and a down conversion material receives at least some of the short wavelength radiation directed into the optic device in one spectral region and emits the radiation in another spectral region.

Abstract: An oxynitride-based fluorescent material is formed of what results from substituting Eu for part of M of a general formula 2MO.Si3N4, wherein M denotes one or more elements selected from among Be, Mg, Ca, Sr and Ba. The oxynitride-based fluorescent material can be produced by a method comprising mixing an oxide of Be, Mg, Ca, Sr, Ba or Eu, or a compound of Be, Mg, Ca, Sr, Ba or Eu enabled by heating to form an oxide, and silicon nitride or a compound enabled by heating to form silicon nitride to obtain a mixture and firing the mixture in a vacuum or a non-oxidizing atmosphere at 1200 to 1900° C.

Abstract: Example embodiments are directed to a polarized light emitting diode and method of forming the same. The polarized light emitting diode may include a support layer, a semiconductor layer structure, and/or a polarization control layer. The semiconductor layer structure may be formed on the support layer and may include a light-emitting layer. The polarization control layer may be formed on the semiconductor layer structure and may include a plurality of metal nanowires. The polarized light emitting diode may be configured to control the polarization of emitted light. The method of forming a polarized light emitting diode may include forming on a substrate a semiconductor layer structure with a light emitting layer. A reflecting layer may be formed on the semiconductor layer structure with an attached support layer. The substrate may be removed from the semiconductor layer structure and a polarization control layer including metal nanowires may be formed on the semiconductor layer structure.

Abstract: A light emitting packaged diode ids disclosed that includes a light emitting diode mounted in a reflective package in which the surfaces adjacent the diode are near-Lambertian reflectors. An encapsulant in the package is bordered by the Lambertian reflectors and a phosphor in the encapsulant converts frequencies emitted by the LED chip and, together with the frequencies emitted by the LED chip, produces white light. A substantially flat meniscus formed by the encapsulant defines the emitting surface of the packaged diode.

Abstract: Disclosed is a light emitting device. The light emitting device comprises a substrate, a light emitting diode on the substrate, a molding member sealing the light emitting diode in a double sealing structure and comprising a flat upper surface.

Abstract: Light emitting device packages, light emitting diode (LED) packages and related methods are disclosed. According to one aspect, a light emitting device package is provided. The package includes a mounting pad adapted for attachment of a light emitting device. A lens coupler is attached to the mounting pad and defines an opening for containing the light emitting device and a quantity of encapsulant. The lens coupler includes a surface defining a depression which comprises at least one edge that shapes an outer surface of the encapsulant.

Abstract: A semiconductor light emitting device includes: a body having a recess, a step being provided on a side wall of the recess; a semiconductor light emitting element mounted in the recess; and a resin layer. The resin layer covers at least a portion of an inner surface of the recess of the body. The resin layer has a higher reflectivity than the inner surface of the recess of the body.

Abstract: The present invention provides a lighting device package with one or more light-emitting elements operatively coupled to a substrate and a frame disposed at least in part around the one or more light-emitting elements. The frame and substrate define a cavity in which the one or more light-emitting elements are positioned, wherein this cavity can be substantially enclosed by an optically transmissive system. At least a portion of the cavity can be filled with an encapsulation material. The frame defines one or more passageways, wherein each passageway interconnects the cavity with the outside through an outside port. For example, the outside port can be accessible from the ambient when the lighting device package is in an assembled state, thereby enabling fluidic movement of the encapsulation material into and/or out of the cavity.

Abstract: The present invention provides a light emitting device, which includes a transparent substrate, an epitaxial stack structure having a first portion and a second portion on the transparent substrate, a II/V group compound contact layer on the first portion of the epitaxial stack structure, a nitride-crystallized layer on the II/V group compound contact layer, a transparent conductive layer covering the nitride-crystallized layer, a first electrode on a portion of the transparent conductive layer, and a second electrode on the second portion of the epitaxial stack structure and structurally separated from the structure on the first portion of the epitaxial stack structure. The nitride-crystallized layer may help increase the external quantum efficiency of the light emitting device, thereby the light emitting efficiency of the light emitting device may also be improved.

Abstract: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed so as to improve the heat dissipation efficiency of the light-emitting device.

Abstract: Provided is a vertical semiconductor light-emitting device and a method of manufacturing the same. The method may include sequentially forming a lower clad layer, an active layer, and an upper clad layer on a substrate to form a semiconductor layer and forming first electrode layers on the upper clad layer. A metal support layer may be formed on each of the first electrode layers and a trench may be formed between the first electrode layers. The substrate may be removed and a second electrode layer may be formed on the lower clad layer.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: A method of manufacturing a nitride semiconductor substrate is provided. A partial surface treatment process is performed to rough a portion of a surface of a substrate. Next, a nitride semiconductor layer is formed over the substrate. Since the nitride semiconductor layer simply grows on the unroughened surface of the substrate through selective area epitaxy growth and lateral epitaxy growth, some of the threading dislocations in the nitride semiconductor layer are blocked. Thereby, the threading dislocation density of the grown nitride semiconductor layer is reduced.

Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.

Abstract: Provided is a nitride-based semiconductor light emitting device having increased efficiency and power characteristics and method of manufacturing the same. The method may include forming a sacrificial layer on a substrate, forming a passivation layer on the sacrificial layer, forming a plurality of masking dots of a metal nitride on the passivation layer, laterally epitaxially growing a nitride-based semiconductor layer on the passivation layer using the masking dots as masks, forming a semiconductor device on the nitride-based semiconductor layer, and wet etching the sacrificial layer to separate and/or remove the substrate from the semiconductor device.

Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

Abstract: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal coupling layer is configured for thermal coupling to a heat sink. The power module further includes at least one laminar interconnect that includes first and second electrically conductive layers and an insulating layer disposed between the first and second electrically conductive layers. The first electrically conductive layer of the laminar interconnect is electrically connected to the upper layer of the substrate. Electrical connections connect a top side of the power devices to the second electrically conductive layer of the laminar interconnect.

Abstract: An image sensor includes a photo diode formed over a semiconductor substrate. At least one IMD layer is formed on the semiconductor substrate. A dielectric medium fills a through-hole formed in the IMD layer over the photo diode. The dielectric medium may be made with materials with a higher refractive index than the materials forming the IMD layer.

Abstract: A field effect transistor is formed on a substrate and includes a semiconductor channel region formed over the substrate and a metallic source region formed on the channel region. A metallic drain region is formed on the channel region and a metallic gate region formed on the channel region between the source and drain regions. A first metallic body contact region is formed adjacent the drain region and extending through the channel region to contact the substrate. The field effect transistor may further include a second metallic body contact region formed adjacent the source region and extending through the channel region to contact the substrate.