Abstract: A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.

Abstract: Disclosed is a field effect transistor including: an electron supplying layer made of AlGaAs; an interface stabilizing layer, provided on the electron supplying layer, and not containing Al; an etching stop layer, provided on the interface stabilizing layer, and made of TnGaP; and a contact layer, provided on the etching stop layer, and made of GaAs. This prevents a interfacial layer such as an AlGaAsP layer from being formed in the interface between the AlGaAs electron supplying layer and the InGaP etching stop layer, and prevents deterioration in the Schottky characteristic.

Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.

Abstract: A semiconductor device including a lateral field-effect transistor and Schottky diode and method of forming the same. In one embodiment, the lateral field-effect transistor includes a buffer layer having a contact covering a substantial portion of a bottom surface thereof, a lateral channel above the buffer layer, another contact above the lateral channel, and an interconnect that connects the lateral channel to the buffer layer. The semiconductor device also includes a Schottky diode parallel-coupled to the lateral field-effect transistor including a cathode formed from another buffer layer interposed between the buffer layer and the lateral channel, a Schottky interconnect interposed between the another buffer layer and the another contact, and an anode formed on a surface of the Schottky interconnect operable to connect the anode to the another contact. The semiconductor device may also include an isolation layer interposed between the buffer layer and the lateral channel.

Abstract: A semiconductor structure is fabricated with two different portions. The first portion forms a first transistor, while the second portion forms a second transistor. Notably, portions of the first transistor also a make up portions of the second transistor. That is, both the first transistor and the second transistor are made of portions of the same structure.

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.

Abstract: A first intermediate power supply wiring is arranged on an upper layer of a lowest power supply wiring arranged along a first direction. A second intermediate power supply wiring is arranged on an upper layer of the first power supply wiring. A third intermediate power supply wiring is arranged on an upper layer of the second intermediate power supply wiring. A highest power supply wiring is arranged along a second direction on an upper layer of the third intermediate power supply wiring. The first intermediate power supply wiring extends from an intersecting region of the highest power supply wiring and the lowest power supply wiring to an outer side of the intersecting region along the first direction. The second intermediate power supply wiring includes a wiring site extending from the intersecting region to the outer side of the intersecting region along the first direction and a wiring site extending from the intersecting region to the outer side of the intersecting region along the second direction.

Abstract: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair.

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract: The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a second zone doped by a second type of dopant. The channel is doped by the second type of dopant. The gate insulator comprises a first part corresponding to the first doped zone and a second part corresponding to the second doped zone of the gate. The first part of the gate insulator has a higher tunnel resistance than the second part. Data storage is realized by means of charge carrier transportation from the gate to the floating substrate through the lower tunnel resistance part of the gate insulator.

Abstract: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate (6) is constructed by laminating a support substrate (16) composed of silicon, a buffer layer (18), and a thin silicon layer (20) composed of single-crystal silicon. p? regions (26) (overflow barrier) and n-type regions (28) which function as transfer paths are formed under the optical sensors (4). The first and the second transfer electrodes (12 and 14) are disposed between the buffer layer (18) and the n-type regions (28), and an insulating film (30) is interposed between the n-type regions (28) and the first and the second transfer electrodes (12 and 14). In this structure, the light-receiving area is large since the transfer electrodes are not disposed in the front region.

Abstract: A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor substrate; a first conductivity type epitaxial layer formed on the second conductivity type epitaxial layer; a second conductivity type source region which penetrates the first conductivity type epitaxial layer in a layer thickness direction thereof and is connected to the second conductivity type epitaxial layer; a second conductivity type drain region which is spaced from the source region, penetrates the first conductivity type epitaxial layer in the layer thickness direction, and is connected to the second conductivity type epitaxial layer; a source electrode connected to the source region; a drain electrode connected to the drain region; and a gate electrode electrically connected to the first conductivity type epitaxial layer between the source region and the drain region.

Abstract: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.

Abstract: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device by forming a gate pattern over a semiconductor substrate. A material, which has a higher atomic weight than that of a pocket implant dopant, is implanted at an angle or tilt into the respective pocket implant areas at both sides of the gate pattern. The pocket implant dopant is then implanted into the respective pocket implant areas at both sides of the gate pattern.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: An image sensor is provided. The image sensor includes a transistor region over a substrate, an interlayer insulating layer having a via hole over the transistor region, a silicon layer over the interlayer insulating layer, and a photodiode over the silicon layer.

Abstract: A golf bag is provided including a carrying system having two members attached to a surface of the golf bag and arranged to form an “X” pattern. A casing is affixed to the golf bag and defines a recess in a surface of the golf bag. A stand system is mounted in the recess. The stand system includes a pair of attached pivotal members and a center rod assembly disposed between the pivotal members. The stand system further includes a spring mounted to an upper end of the center rod assembly, whereby compression and release of the spring cause the pivotal members to pivot between extended and retracted positions.

Abstract: A pixel circuit, and method of forming a pixel circuit, an imager device, and a processing system include a photo-conversion device, a floating diffusion region for receiving and storing charge from the photo-conversion device, and a transparent transistor for use in operation of the pixel, wherein the transparent transistor is at least partially over the photo-conversion device, such that the photo-conversion device receives light passing through the transparent transistor.

Abstract: Method, apparatus and systems are disclosed in which a digital imager has optically black reference pixels in at least one row of a pixel array. The signals from the reference pixels in one row of the array are used as reference signals to cancel out the row-wise noise from pixel signals readout from active pixels in other rows of the array. An arrangement for locating the array driving circuit relative to the reference pixels is also provided.

Abstract: A CMOS image sensor for converting an optical signal into an electric signal includes a plurality of unit pixels, each having a photodiode on one side of an active region, a plurality of gate electrodes over the active region, and source/drain region on opposed sides of the gate electrodes, the source/drain region being formed by impurity implantation. The pixels include a transfer transistor, a reset transistor, a drive transistor, and a select transistor, and the gate electrode of the drive transistor extends from a region between the gate electrodes of the reset transistor and the select transistor to a region between the gate electrodes of the reset transistor and the transfer transistor.

Abstract: A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

Abstract: A memory cell comprises a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes.

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.

Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.

Abstract: Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.

Abstract: A voltage controller having an input distribution network with imbedded input switches, a number of charge storage elements such as capacitors, an output distribution network with imbedded output switches, and a switch actuator which controls the input switches and output switches to provide for the controlled charging and discharging of the charge storage elements.

Abstract: The method includes the steps of forming an upper electrode of a capacitor by patterning a second conductive film; forming a capacitor dielectric film by patterning a ferroelectric film; and forming a lower electrode by patterning a first conductive film. A step of forming the first conductive film includes the steps of forming a lower conductive layer made of a noble metal other than iridium over a first interlayer insulating film; and forming an upper conductive layer made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Abstract: A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a metal capacitor. The metal capacitor can be formed in one or more metal levels and in one embodiment is in a shape of a comb with multiple fingers. In one embodiment, the non-volatile memory transistor is an NMOS non-volatile memory transistor.

Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.

Abstract: Provided are a semiconductor device and a manufacturing method thereof. A pair of adjacent gate structure can be formed on a substrate. Mask patterns exposing a portion located between the gate structures are formed. The substrate portion located between the gate structures can be etched using the mask patterns as an etch mask to form a pocket. First conduction type impurities can be implanted into the pocket to form a first impurity layer in a surface of the pocket. Second conduction type impurities can be implanted into the pocket to form a second impurity layer on the first impurity layer. The pocket can be filled with an insulating material. Accordingly, impurities having a type opposite to the type of source junction impurities are implanted into the pocket to reduce a potential barrier of a source junction. Consequently, punch-through generated between a source and a drain can be inhibited.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: Disclosed in a non-volatile (NV) memory device and a method of manufacturing the same. The method includes forming transistor and EEPROM regions by implanting first and second conductive impurity ions into a semiconductor substrate, depositing a gate oxide on an entire surface of the semiconductor substrate, forming a first gate poly on the EEPROM region, removing the gate oxide not below the first gate poly, forming a logic gate oxide, a tunnel oxide and a coupling oxide, forming a logic gate poly on the transistor region and a second gate poly on a sidewall of the first gate poly, forming source/drain extension regions by implanting first and second conductive impurity ions, forming a sidewall spacer on the logic gate poly and the second gate poly, and forming a silicide on the source, drain and logic gate poly of the transistor region.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.

Abstract: Disclosed is a flash memory device comprising a semiconductor substrate in which a channel region is formed, an ONO (oxide-nitride-oxide) layer on the semiconductor substrate, a floating gate on the ONO layer, an anti-reflection layer on the floating gate; and a control gate on the anti-reflection layer. The channel region can be ion implanted before forming the floating gate.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device that may improve a reliability of process by obtaining a Depth of Focus (DOF) in an exposure process. In embodiments, a method may include sequentially stacking an oxide film, a floating gate poly film, an ONO film, a control gate poly film, and a BARC (Bottom AntiReflect Coating) on a semiconductor substrate, forming a photoresist pattern for a stack gate on the BARC, and etching the BARC, the control gate poly film, the ONO film and the floating gate poly film at once by using the photoresist pattern until the oxide film is exposed.

Abstract: A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region may be formed by injecting a dopant into a part of the P-well region or N-well region. A gate oxide layer and a poly-silicon layer may be formed over the well region, the drift region, and the STI. A control gate pattern may be formed by patterning the gate oxide layer and the poly-silicon layer. A source region and a drain region may be formed on opposite sides of the control gate pattern. A silicon nitride layer may be deposited over the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern.

Abstract: A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.

Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: A semiconductor device and methods of fabricating the same are provided. The semiconductor device can include a tunnel oxide layer on a semiconductor substrate, a floating gate having a top surface with concave-convex shapes on the tunnel oxide layer, an ONO (oxide/nitride/oxide) layer on the floating gate, and a control gate on the ONO layer.

Abstract: A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.

Abstract: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

Abstract: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

Abstract: A semiconductor device includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor adjacent the gate stack and having at least a portion in the semiconductor substrate, wherein the stressor comprises an element for adjusting a lattice constant of the stressor. The stressor includes a lower portion and a higher portion on the lower portion, wherein the element in the lower portion has a first atomic percentage, and the element in the higher portion has a second atomic percentage substantially greater than the first atomic percentage.

Abstract: A semiconductor device may include a semiconductor substrate with a well area; a conductive body in the well area; a source in the body; a drift region and a drain in a vertical region of the well area other than the body; and a gate electrode between the source and the drain.

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.