Abstract: A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.

Abstract: Methods, constructions, and devices that include tantalum oxide layers adjacent to niobium nitride are disclosed herein. In certain embodiments, the niobium nitride is crystalline and has a hexagonal close-packed structure. Optionally, the niobium nitride can have a surface that includes niobium oxide adjacent to at least a portion thereof. In certain embodiments, the tantalum oxide layer is crystallographically textured and has a hexagonal structure.

Abstract: A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

Abstract: Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on different horizontal planes relative to the substrate to reduce parasitic capacitance therebetween.

Abstract: Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided.

Abstract: A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D). The gate (G) is disposed near the channel region (CO) and the memory element (ME) is disposed in between the channel region (CO) and the gate. The channel region is disposed within a beam-shaped semiconductor layer (4), with the beam-shaped semiconductor layer (4a, 4b, 4c, 4d) extending in the first direction (X) between the source (12,S) and drain (12,D) regions and having lateral surfaces (4a, 4b, 4c, 4d) extending parallel to the first direction (X).

Abstract: A vertically oriented self terminating discrete trench MOS device (1) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate.

Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.

Abstract: A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.

Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Abstract: Accumulation mode MOS transistors and methods for fabricating such transistors are provided. A method comprises providing an SOI layer disposed overlying a substrate with an insulating layer interposed therebetween. The SOI layer is impurity doped with a first dopant of a first conductivity type and spacers and a gate stack having a sacrificial polycrystalline silicon gate electrode is formed on the SOI layer. A first and a second silicon region are impurity doped with a second dopant of the first conductivity type. The first silicon region and the second silicon region are aligned to the gate stack and spacers. The sacrificial polycrystalline silicon gate electrode is removed and a metal-comprising gate electrode is formed from a metal-comprising material having a mid-gap work function.

Abstract: Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.

Abstract: A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer.

Abstract: A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.

Abstract: A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film.

Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

Abstract: A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a liner without nitride portions. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have their threshold values set independently from one another.

Abstract: Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated signal or an amplitude modulated signal.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract: A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.

Abstract: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.

Abstract: Source/drain extensions and source and drain regions are formed in a semiconductor substrate utilizing an optional temporary first gate spacer and a temporary second gate spacer. After forming a gate silicide and a source and drain silicide in a silicidation process, the optional temporary first gate spacer and a temporary second gate spacer are removed. Low-k dielectric material is disposed directly on the sidewalls of the gate electrode. The low-k dielectric material may form a portion of a lower gate spacer. Alternatively, the low-k dielectric material may form a layer that contacts and covers the source and drain regions. The low-k material displaces the optional temporary first gate spacer and the temporary second gate spacer to lower the overlap capacitance between the gate electrode and the source/drain extensions. A continuous mobile ion diffusion barrier dielectric layer is formed over the low-k material.

Abstract: A packaged micro-electromechanical systems (MEMS) device assembly includes a MEMS device, a substrate within which the MEMS device is disposed, and a lid disposed over the substrate. The assembly may include one or more first cavities within the lid having a predetermined volume satisfying packaging specifications for the packaged MEMS device assembly. The assembly may include one or more second cavities within the lid and one or more corresponding overflow areas within the lid, where each second cavity contains a material and each corresponding overflow area is adapted to catch overflow of the material. The assembly may include one or more third cavities within the lid and one or more channels within one of the substrate and the lid to fluidically connect the MEMS device to the third cavities.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: An integrated circuit having a magnetic tunnel junction device is disclosed. In one embodiment, the device includes: a spin transfer torque magnetization reversal structure including a first ferromagnetic structure, a second ferromagnetic structure, and a tunnel barrier structure between the first ferromagnetic structure and the second ferromagnetic structure.

Abstract: A solid-state image pickup device 1 has a construction in which a P-type semiconductor layer 102, an insulating layer 104, a color filter 106, a light transmitting layer 107, and a light focusing layer 108 are sequentially laminated on an N-type semiconductor layer 101. A plurality of photodiodes 103 are formed in the P-type semiconductor layer 102 on the insulating layer 104 side. A light shielding film 105 is formed in the insulating layer 104. The plurality of photodiodes 103 are densely mounted by being unequally arranged two-dimensionally. The light-focusing efficiency can be improved because the plurality of photodiodes 103 closely arranged to each other share the light transmitting layer 107 and the light focusing layer 108.

Abstract: A portable optical detection chip comprises a substrate, a plurality of avalanche-type photosensitive device modules and a plurality of plane mirrors. The plurality of avalanche-type photosensitive device modules are formed on the substrate, and each of them comprises a plurality of avalanche-type photosensitive devices and a plurality of lenses. Each of the lenses is stacked on one of the avalanche-type photosensitive devices. The plurality of plane mirrors are disposed between the avalanche-type photosensitive device modules. That is, the avalanche-type photosensitive device modules are separated from each other by the plane mirrors.

Abstract: An image sensor and method of manufacturing the same are provided. The image sensor can include a semiconductor substrate having unit pixels; an interlayer dielectric layer formed on the semiconductor substrate and including metal interconnections; a first protective layer comprising an oxide layer formed on the interlayer dielectric layer; a second protective layer comprising an oxide-nitride layer formed on the first protective layer; and a microlens formed on the second protective layer.

Abstract: An image sensor that includes a hard mask layer formed in the upper surface region of the planarization layer and under a microlens to protect an underlying planarization layer from chemicals used during performing a cleaning process after formation of the microlens. The microlens is composed of inorganic materials to prevent cracking by physical impacts.

Abstract: An optical device cooling apparatus includes an image sensor array and a MEMS fan. The MEMS fan is formed integrally with the image sensor array, and cools the image sensor array.

Abstract: It is realized a high sensitive solid-state imaging apparatus which corresponds to an optical system having a short focal length (an optical system having a large incident angle ?). Each pixel (2.8 mm square in size) includes a distributed refractive index lens (1), a color filter (2) for green, Al wirings (3), a signal transmitting unit (4), a planarized layer (5), a light-receiving element (Si photodiode) (6), and an Si substrate (7). The concentric circle structure of the distributed index lens is made of four types of materials having different refractive indexes such as TiO2 (n=2.53), SiN (n=2.53), SiO2 (n=2.53), and air (n=1.0). In the concentric structure, a radial difference of outer peripheries of adjacent circular light-transmitting films is 100 nm. Furthermore, the film thickness is 0.4 ?m.

Abstract: An n/p semiconductor substrate is formed in such a manner that an n type semiconductor layer is deposited on a p+ semiconductor substrate. An imaging area including a plurality of n type semiconductor regions making photoelectric conversion and a plurality of p type semiconductor region for isolation formed around the n type semiconductor regions, is formed in the n/p semiconductor substrate. The n type semiconductor layer is divided into an upper layer and a lower layer. A second n type semiconductor region is formed to connect to the p+ type semiconductor substrate from a surface of the n/p semiconductor substrate in a peripheral region of the imaging area.

Abstract: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

Abstract: A semiconductor device and method of manufacturing the same are provided. According to certain embodiments, a device layer structure can be formed above a metal wiring line by using a stepped portion of the wiring line as an alignment key. The stepped portion can be provided by a height difference between a first insulating layer and the metal wiring line formed in a trench of the first insulating layer. In one embodiment, the stepped portion can be formed by removing a thickness from a top surface of the first insulating layer after forming the metal wiring line in the trench.

Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.

Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.

Abstract: A nitride-based semiconductor device according to the present invention includes a semiconductor multilayer structure supported on a substrate structure 101 with electrical conductivity. The principal surface of the substrate structure 101 has at least one vertical growth region, which functions as a seed crystal for growing a nitride-based semiconductor vertically, and a plurality of lateral growth regions for allowing the nitride-based semiconductor that has grown on the vertical growth region to grow laterally. The sum ?X of the respective sizes of the vertical growth regions as measured in the direction pointed by the arrow A and the sum ?Y of the respective sizes of the lateral growth regions as measured in the same direction satisfy the inequality ?X/?Y>1.0.

Abstract: A process and apparatus for growing a group (III) metal nitride film by remote plasma enhanced chemical vapour deposition are described. The process comprises heating an object selected from the group consisting of a substrate and a substrate comprising a buffer layer in a growth chamber to a temperature in the range of from about 400° C. to o about 750° C., producing active neutral nitrogen species in a nitrogen plasma remotely located from the growth chamber and transferring the active neutral nitrogen species to the growth chamber. A reaction mixture is formed in the growth chamber, the reaction mixture containing a species of a group (III) metal that is capable of reacting with the nitrogen species so as to form a group (III) metal nitride film and a film of group (III) s metal nitride is formed on the heated object under conditions whereby the film is suitable for device purposes. Also described is a group (III) metal nitride film which exhibits an oxygen concentration below 1.6 atomic %.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.

Abstract: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Backgrinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern.

Abstract: An integrated circuit package for blocking electromagnetic interference includes a top layer formed in a package substrate. A first plurality of via groups is formed in the top layer surrounding an area on the top layer for an integrated circuit die. At least one lower layer is formed in the package substrate. A lower via group is formed in the lower layer below each of the first plurality of via groups, respectively. An electrical connection is formed in the lower layer between each lower via group and the first plurality of via groups, respectively. A ground connection is formed in the integrated circuit package for each lower via group to connect each lower via group to an electrical ground to block electromagnetic interference.

Abstract: A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding.