Abstract: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second poly-silicon layer is formed on the first poly-silicon layer and within the opening. The second poly-silicon layer is patterned to form a wire, while the first poly-silicon layer is patterned to form a gate. Finally, a source/drain is formed.

Abstract: An image sensor is provided. The image sensor includes a substrate; a first isolation region, a second isolation region, a plurality of photoelectric transducer devices, a read element and a floating diffusion region. The second isolation region has a depth that is less than that of the first isolation region. The plurality of photoelectric transducer devices is isolated from one another by the first isolation region. The read element and the floating diffusion region are isolated from the photoelectric transducer devices by the second isolation region.

Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film which is formed on the semiconductor substrate, a floating gate electrode which is formed on the first insulating film and made of a conductive metal oxide, a second insulating film which is formed on the floating gate electrode, has a relative dielectric constant of not less than 7.8, and is made of an insulating metal oxide of a paraelectric material, and a control gate electrode which is formed on the second insulating film and made of one of a metal and a conductive metal oxide.

Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

Abstract: A nonvolatile semiconductor memory device includes: a gate dielectric made of a multilayer dielectric that is formed on a substrate and discretely accumulates charges; a gate electrode formed on the gate dielectric; a pair of diffusion regions formed in the surface of the substrate with the gate electrode interposed therebetween and serving as a source and a drain; and a channel region existing between the diffusion regions.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same may be provided. The semiconductor memory device may include a substrate, at least a pair of fins protruding from the semiconductor substrate and facing each other with a gap between fins of the pair of fins, an insulating layer formed between the pair of the fins, a storage node formed on the pair of fins and/or a surface of a portion of the insulating layer, and/or a gate electrode formed on the storage node.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm) the CHSP is sets to satisfy the following equation: CHSP?3.80+0.148?.

Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A gate electrode is buried in a trench passing through a second conductivity type first body region formed on a first conductivity type drain region so as to form a recessed portion at the upper part of the trench. An insulating film is formed on the gate electrode so as to occupy the recessed portion partway. A first conductivity type source region is formed in at least a region of the upper part of the first body region which serves as at least the wall part of the trench. A second conductivity type second body region is formed in the other region of the upper part thereof so as to be adjacent to the source region in the direction that the trench extends. A second conductivity type third body region is formed in the respective upper parts of the source region and the second body region.

Abstract: The present invention is an SOI wafer in which at least a silicon active layer is formed over a support substrate via an insulator film or on a support substrate directly, wherein, at least, the silicon active layer consists of a P(phosphorus)-doped silicon single crystal grown by Czochralski method, which is occupied by N region and/or defect-free I region, and contains Al (aluminum) with concentration of 2×1012 atoms/cc or more. There can be provided with ease and at low cost an SOI wafer with high electrical reliability in a device fabrication process, that has an excellent electric property without generation of micro pits by cleaning with hydrofluoric acid etc. even in the case of forming an extremely thin silicon active layer, or that retains high insulation property even in the case of forming an extremely thin inter-layer insulator film.

Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.

Abstract: This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.

Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Abstract: Silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a semiconductor device comprises: a gate conductor spaced above a semiconductor layer by a gate dielectric; dielectric spacers disposed laterally adjacent to sidewalls of the gate conductor; source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and a conductive implant region comprising metallic species disposed in a bottom region of the semiconductor layer for electrically connecting the source junction to the body region, wherein a drain-side of the implant region is spaced apart from the body region and a source-side of the implant region contacts the body region.

Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

Abstract: Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer comprises tensile sections above digital logic n-type transistors, compressive sections above digital logic p-type transistors and additional tensile sections above SRAM cells and/or analog FETs. An amorphization ion-implant is performed to relax the strain over SRAM cell p-FETs and, thereby, eliminate variability and avoid p-FET performance degradation in the SRAM cells. Additionally, this ion-implant can relax the strain above both analog p-FETs and n-FETs and, thereby, eliminate variability and the coupling of the logic device process to the analog FETs and provide more predictable and well-controlled analog FETs.

Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.

Abstract: The invention relates to a field-effect microelectronic device, and the production method thereof. Said device comprises a substrate (700) and at least one improved structure (702), capable of forming one or several transistor channels. Said structure, composed of several bars stacked on the substrate, may allow space saving in the integration of field-effect transistors and the performances thereof to be improved.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A power semiconductor device has a first base layer of first conductive type, a contact layer of first conductive type formed on a surface of the first base layer, a second base layer of first conductive layer which is formed on the surface of the first base layer at a side opposite to the first contact layer and has an impurity concentration higher than that of the first base layer, a second contact layer of second conductive type formed on the surface of the first base layer or the second base layer, and a junction termination region formed in vicinity of or in contact with outside in a horizontal direction of the second contact layer.

Abstract: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain junctions having asymmetrical junction structures, respectively, wherein the gate has a lower portion arranged on the active region of the substrate, the lower gate portion having a stepped profile having a lower surface, an upper surface and a vertically-extending side surface. The invention also provides a method for manufacturing this transistor. In accordance with this transistor structure, an increase in the dopant concentration of a storage node is prevented. Accordingly, a reduction in the amount of leakage current is achieved, so that an improvement in the refresh characteristics of the transistor is achieved.

Abstract: An insulating film includes an oxide or an oxynitride of a constituent element having a positive valence. The oxide or the oxynitride contains an additive element having a larger valence than the constituent element in a range not less than 3×10?8 at % and less than 1.6×10?3 at %.

Abstract: A semiconductor integrated circuit (IC) chip includes an IC chip body and a nano-structure-surface passivation film. The IC chip body has at least one surface. The nano-structure-surface passivation film is formed on the at least one surface. The nano-structure-surface passivation film including nano-particles and a carrier resin protects the IC chip body from encountering any external interference. The IC chip body further has a plurality of fingerprint sensing members for sensing a whole fingerprint or a partial fingerprint.

Abstract: An arrangement having a component mounted on a carrier in a flip chip construction which is encapsulated by a film, in particular a plastic film, laminated over the entire surface of the component. For additional sealing and mechanical stabilization, a plastic compound in liquid form is subsequently applied and hardened so as to surround the chip.

Abstract: A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.

Abstract: Semiconductor detector includes semiconductor substrate (HK), source region (S), drain region (D), external gate region (G) and inner gate region (IG) for collecting free charge carriers generated in semiconductor substrate, wherein inner gate region is arranged in semiconductor substrate at least partially under external gate region to control conduction channel (K) from below as a function of the accumulated charge carriers, as well as with clear contact (CL) for the removal of the accumulated charge carriers from inner gate region, as well as with drain-clear region (DCG) that can be selectively controlled as an auxiliary clear contact or as a drain. Barrier contact (B) is arranged in a lateral direction between external gate region and drain-clear region to build up a controllable potential barrier between inner gate region and clear contact that prevents the charge carriers accumulated in inner gate region from being removed by suction from clear contact.

Abstract: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate.

Abstract: A semiconductor package has a substrate made of WCu, WAg, MoCu or MoAg. A plurality of leads are fixed to the substrate by hermetic sealing without an intervening nickel plating layer. A cover is bonded to the substrate with a seal ring which is directly bonded to the substrate by brazing without an intervening nickel plating layer. The leads are nickel plated and gold plated after hermetic sealing, and the seal ring is nickel plated and gold plated after brazing. Even though the substrate is made of a metal alloy, this arrangement provides the package with a high degree of air tightness.

Abstract: The semiconductor device according to this invention is characterized by a package structure of a semiconductor substrate 100 equipped with a photoelectric converting portion, wherein a light-shading means 104 is arranged in an area corresponding to at least the photoelectric converting portion on the side of the rear surface of the semiconductor substrate.

Abstract: The ternary alloy CdSexTe1-x(2 1 1) and the quaternary alloy Cd1-zZnzSexTe1-x have been grown on Si(2 1 1) substrates using molecular beam epitaxy (MBE). The growth of CdSeTe is facilitated using a compound CdTe effusion source and a Se effusion source while the growth of CdZnSeTe is facilitated using a compound CdTe effusion source, a compound ZnTe effusion source, and an elemental Se source. The alloy compositions (x) and (z) of CdSexTe1-x ternary compound and Cd1-zZnzSexTe1-x are controlled through the Se/CdTe and ZnTe/CdTe flux ratios. The rate of Se incorporation is higher than the rate of Te incorporation as growth temperature increases. As-grown CdSeTe with 4% Se and CdZnSeTe with 4% Zn+Se, which is substantially lattice matched to long-wavelength infrared HgCdTe materials, exhibits excellent surface morphology, low surface defect density (less than 500 cm2), and a narrow X-ray rocking curve (a full-width at half maximum of 103 arcsec).

Abstract: A semiconductor device has a first region and a second region formed on a surface of a substrate. Plural first conductors and second conductors are formed in the first and second regions respectively. A first semiconductor region and a second semiconductor region are formed between adjacent first conductors. The second semiconductor region is in the first semiconductor region and has a conductivity type opposite to that of the first semiconductor. A third semiconductor region is formed between adjacent second conductors. The third semiconductor region has the same conductivity type as the second semiconductor region and is lower in density than the second semiconductor region. The third semiconductor region has a metal contact region for contact with a metal, which is electrically connected to the second semiconductor region. A center-to-center distance between adjacent first conductors is smaller than that between adjacent second conductors.

Abstract: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

Abstract: Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.

Abstract: The invention is directed to a chip comprising a substrate having a plurality of pads located thereon and a passivation layer located over the substrate, wherein the passivation layer has a plurality of openings and recesses formed therein and the openings expose the pads respectively. During the later performed packaging process, a molding compound can fill out the recesses on the passivation layer to provide a stronger mechanical adhesion between the molding compound and the passivation layer. Therefore, the peeling issue of the molding compound can be solved.

Abstract: The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure.

Abstract: A nonvolatile variable resistance memory device may include a lower electrode; a stacked structure including a first Cu compound layer disposed on the lower electrode, and a second Cu compound layer disposed on the first Cu compound layer; and an upper electrode disposed on the second Cu compound layer.

Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.

Abstract: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate 1, such as a sapphire substrate having the (0001) plane, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus 11. Next, gaseous iron compound GFe from a source 13 for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source 15 are caused to react with each other in a mixing container 16 to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source 17, and second substance gas GGa containing elemental gallium are supplied to a reaction tube 21 to form iron-doped gallium nitride 23 on the substrate 1.

Abstract: A semiconductor wafer is manufactured in such a way that a main surface of a semiconductor substrate is partitioned into a plurality of semiconductor element forming regions defined by scribing regions, wherein at least one pattern for measuring a width of a cut region and its positional shift is formed in proximity to a peripheral portion of the semiconductor substrate on a scribing line. The pattern is constituted by a plurality of micro patterns that are aligned in a reverse V-shape to traverse the scribing line and a pair of elongated patterns that partially overlap seal rings formed in both sides of the scribing line. It is possible to form a channel whose width is larger than the width of the cut region on the backside of the semiconductor substrate in correspondence with the scribing region in order to avoid the formation of chipping, cracks, and burrs during cutting.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: A heat spreader lid includes an outer periphery region having a lip for bonding to an underlying substrate board, a center region, and one or more strain isolation regions. The strain isolation regions are located between the center region and the outer periphery region and may comprise a number of slots cut partially or completely through the lid in a pattern surrounding or partially surrounding the center region. The strain isolation regions provide isolation of strain and relief of stress due to thermal expansion of the lid despite constraint at its periphery by the bonded lip, resulting in less thermally-induced warping of the center region, less thermally-induced stress on the bond between the lip and the substrate board, and/or less thermally-induced deflection of the substrate board.

Abstract: An FBGA semiconductor component has a chip side for receiving a semiconductor chip, a solder ball side for applying solder balls on ball pads, and a bonding channel embodied as an opening between the chip side and the solder ball side and serving for leading through wire bridges between the semiconductor chip and bonding islands on the solder ball side. The bonding channel has side areas extending between the chip side and the solder ball side and can be closed off with a housing part comprising potting composition. Positively locking elements for a potting composition are arranged in that region of the substrate in which the housing part is produced.