Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: An apparatus and system including a substrate having a plurality of through-holes therethrough, and an integrated circuit (IC) socket frame to mount to the substrate. The IC socket frame may include a plurality of beam features, each extending from a socket frame body and corresponding in arrangement to the plurality of through-holes through the substrate.

Abstract: A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith. Adjacent stacked semiconductor devices may include abutting nonconfluent spacer layers which together define a distance between opposed surfaces of the semiconductor devices. Each nonconfluent spacer layer includes voids therein that communicate with an exterior periphery of the layer to facilitate the lateral introduction of adhesive or encapsulant material into the layer and between the adjacent, stacked semiconductor devices. Multi-chip modules are also disclosed, as are methods for forming the nonconfluent spacer layers and assembly and packaging methods.

Abstract: An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, forming a contact pad on the base substrate, mounting a first integrated circuit on the base substrate, forming a base package body around the first integrated circuit, providing an offset substrate, mounting a second integrated circuit on the offset substrate, and coupling the offset substrate to the contact pad, including placing the offset substrate on the base package body.

Abstract: A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.

Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a solid-state device.

Abstract: A multi-chip package comprising at least a first die and a second die, wherein each die comprises an integrated circuit (IC) disposed thereon. Each of the first die and the second die comprise a plurality of contact pads coupled with the respective IC. The contact pads on the first IC comprise a first mode pad coupled to a first device formed on the first die, and the contact pads on the second IC comprise a second mode pad coupled to a second device formed on the second die. The first mode pad is coupled to a first potential and causes the first device to operate in a first mode. The second mode pad is coupled to a second potential and causes the second device to operate in a second mode. The first and second mode are selected based on the relative position of the first and second die.

Abstract: The present invention relates to a plasma display panel (PDP) that includes a first substrate, an address electrode formed on the first substrate, a dielectric layer formed on the first substrate and covering the address electrode, a barrier rib formed on the dielectric layer, a second substrate, a display electrode formed on the second substrate, a dielectric layer formed on the second substrate and covering the display electrode, and a protection layer formed on the dielectric layer of the second substrate. Discharge cells are defined by barrier ribs, and a phosphor layer is formed in the discharge cells. Barrier ribs contains inorganic adsorbent. When a PDP is operated for a long time, residual carbon or water is generated inside discharge cells, and thereby contaminates a discharge gas contained in the discharge cells. The inorganic adsorbent included in the barrier ribs absorb the residual carbon or water improving efficiency and lifespan of the PDP.

Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.

Abstract: Methods of bulk manufacturing high temperature sensor sub-assembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

Abstract: An integrated circuit chip mounting structure includes a chip carrier electrically connected to a circuit board with an integrated circuit chip mounted on the chip carrier. In addition, a thermally conductive device is thermally connected to the chip and a set of compressible support members are provided to transmit a portion of an applied compressive load from the thermally conductive device to the chip and chip carrier.

Abstract: A power circuit package includes a base including a substrate, a plurality of interconnect circuit layers over the substrate with each including a substrate insulating layer patterned with substrate electrical interconnects, and via connections extending from a top surface of the substrate to at least one of the substrate electrical interconnects; and a power semiconductor module including power semiconductor devices each including device pads on a top surface of the respective power semiconductor device and backside contacts on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure, the membrane structure including a membrane insulating layer and membrane electrical interconnects over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts are coupled to selected substrate electrical interconnects or via connections.

Abstract: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further include adhesively attaching the microfeature workpiece to the support member by contacting the first adhesive with the second adhesive while the second adhesive is only partially cured. In further particular embodiments, the first and second adhesives can have different compositions, and the second adhesive can be fully cured after the microfeature workpiece and support member are adhesively attached.

Abstract: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, a conductive member and an external electrode. A penetrating hole is formed in the substrate, the penetrating hole having an internal wall surface, the internal wall surface having a protrusion formed of a material constituting the substrate. The semiconductor chip has an electrode. The conductive member is formed over a particular region including the penetrating hole on one side of the substrate, and is electrically connected to the electrode of the semiconductor chip. The external electrode is provided through the penetrating hole, electrically connected to the conductive member, and projects from the other side of the substrate.

Abstract: A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip. The backside of the wafer includes a metal layer patterned into discrete spaced-apart deposits that form an electrical contact to the semiconductor and the respective group of active devices. The deposits are not contiguously or laterally connected to each other and function to protect the metal layer from peeling or detaching from the wafer during dicing of the semiconductor wafer into chips.

Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Abstract: A semiconductor device has a bonding pad configured to be bonded to a bonding member, a test pad configured to contact with a test probe at a test, and an internal circuit electrically connected to the bonding pad and the test pad. The bonding pad overlaps with the internal circuit in a direction vertical to a surface of a semiconductor chip. The test pad does not overlap with the internal circuit in the direction.

Abstract: A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings of the first metal wiring layer and the second metal wiring layer positioned above the first metal wiring layer. And, potential of predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, and a capacitance value between the wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less.

Abstract: By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in different directions. As integrated circuits scale, importance of line to line capacitance in one plane increases. Thus, in some embodiments, the dielectric constant of the oriented dielectric may be lower in the plane that controls line to line capacitance.

Abstract: In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to expose another region of the conductive pad. The semiconductor device also includes a conductive contact extending through the opening. The conductive contact is electrically connected to the conductive pad. As a result, manufacturing cost for the semiconductor device may be reduced while manufacturing throughput may be improved.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.

Abstract: A component includes a carrier substrate having a coefficient of thermal expansion ?p and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion ?1 in a first direction x1 and a first expansion difference, ??1 equal to the absolute value of ?p??1. The chip also has a second coefficient of thermal expansion ?2 in a second direction x2 and a second expansion difference ??2 is equal to the absolute value of ?p??2,. The bumps are arranged such that a first distance, ?x1, corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x1 is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x2.

Abstract: A first solder resist section and a second solder resist section are formed over an upper surface of a wiring board. A semiconductor chip is bonded onto the first solder resist section via an adhesive interposed therebetween. Electrodes of the semiconductor chip are respectively electrically connected to connecting terminals exposed through openings of the second solder resist section via bonding wires. An encapsulating resin is formed over the upper surface of the wiring board so as to cover the semiconductor chip and the bonding wires. A plane dimension of the first solder resist section is smaller than that of the semiconductor chip, and the encapsulating resin is filled even below an outer peripheral portion of a back surface of the semiconductor chip.

Abstract: A stacked electronics module comprises a first layer including a first substrate having a front side and a backside, a first electrical interconnect layer disposed on the first substrate and a first electronic device disposed on the front side of the first substrate. In addition, the stacked electronics module comprises a second layer including a second substrate having a front side and a backside, a second electrical interconnect layer disposed on the second substrate and a second electronic device disposed on the front side of the second substrate.

Abstract: A thin-film semiconductor substrate includes an insulative substrate, an amorphous semiconductor thin film that is formed on the insulative substrate, and a plurality of alignment marks that are located on the semiconductor thin film and are indicative of reference positions for crystallization.

Abstract: A solar-powered wind chime has a solar energy system for powering an electrical subsystem. The electrical subsystem may include lighting elements for illuminating the wind chime and the area around the wind chime in a decorative and functional manner.

Abstract: The present invention is directed to a control strategy for operating a plurality of prime power sources during propulsion, idling and braking and is applicable to large systems such as trucks, ships, cranes and locomotives utilizing diesel engines, gas turbine engines, other types of internal combustion engines, fuel cells or combinations of these that require substantial power and low emissions utilizing multiple power plant combinations. The present invention is directed at a general control strategy for multi power plant systems where the power systems need not be of the same type or power rating and may even use different fuels. The invention is based on a common DC bus electrical architecture so that prime power sources need not be synchronized.

Abstract: A system for generating electrical power for an individual property (10) comprises a wind powered electricity generator (16) mounted on that property and arranged so that the electrical power generated be used in that property in preference to or to supplement electrical power provided by the national grid or other general electrical energy source.

Abstract: A control system for a double-fed induction generator (DFIG) comprising a rotor (1) having rotor windings and a stator (2) having stator windings connectable to a grid for electric power distribution. The control system comprises a converter (17-0, 171), having a clamping unit comprising at least one passive voltage-dependent resistor element (291, 292, 293, 294) for providing a clamping voltage over the rotor windings when the clamping unit is triggered. The invention also relates to a double-fed induction generator (DIFIG) system and to a method for protecting the converter in a power generation system.

Abstract: The present invention relates to a hybrid power-generating device and a power generating method thereof. The hybrid power-generating device is primarily comprised of: a primary electrical generator and an auxiliary electrical generator with different characteristics, both mechanically coupled to a prime while enabling the rated power of the auxiliary electrical generator to be smaller than that of the primary electrical generator; wherein, as the prime is operating at a low rotation speed or at its initial operating stage, the auxiliary electrical generator is enabled to be driven and activated thereby; and as the operating speed of the driver is stabilized and reaches a predetermined value, the primary electrical generator is then being driven and activated thereby. By the aforesaid hybrid power-generating device, not only the overall performance and the stability of power grid are enhanced, but also the operating cost is reduced.

Abstract: SYSTEM FOR OPERATING A GENERATOR AS A MOTOR IN A TURBINE WIND POWER GENERATING SYSTEM includes a controller and Four Quadrant or Regenerative Drive Circuitry which alternatively operates one or more generators as motors.

Abstract: An assembly includes a water turbine and a rotary electrical generator, the rotor of which is connected to the turbine. The turbine has at least three axially directed blades, each blade being individually directly connected to the rotor of the generator.

Abstract: A vehicle traffic monitoring apparatus includes an imaging device; an image processing device; a global positioning device; and, a wireless communications system. The image processing device includes a computer program to process a data stream from the imaging device, to recognize individual vehicles substantially in view of the vehicle; and, quantify motion of the recognized individual vehicles. A second data stream is a signal output from the image processing device and includes code representing the recognized individual vehicles in view of the vehicle, quantified motion of the recognized vehicles; and vehicle position data from the global positioning system receiver. The wireless communications device receives the second data stream and communicates it a remote device. Localized traffic is monitored in metrics of traffic density, congestion, and, turbulence.

Abstract: The electronic control unit includes a control section monitoring a manipulation of an ignition switch of a vehicle and a timer section for automatically starting up said control section. The electronic control unit is provided with a fault diagnosis function of monitoring, by use of the control section, a state of an electric load connected to said electronic control unit and supplied with electric power from the vehicle battery when the main relay is in the on state after the control section outputs the stop command, and diagnosing whether or not the main relay is in a fault state where the main relay cannot be controlled from the on state to the off state on the basis of monitored state of the electric load.

Abstract: A power supply system for supplying power to a plurality of loads includes a plurality of fuel cells for generating and supplying power to be supplied to the respectively corresponding loads, wherein the fuel cells are provided to correspond to the plurality of loads, a power network for receiving surplus power, which is generated by the fuel cells except power to be supplied to the loads corresponding to the fuel cells, and supplying the surplus power to the loads short of power, wherein the power network is coupled to the plurality of fuel cells, and a control unit for stopping power generation of a first fuel cell among the fuel cells corresponding to a first load among the loads and controlling a second fuel cell among the fuel cells to generate power to be supplied to the first load as the surplus power if an amount of power to be supplied to the first load is less than a predetermined first threshold.

Abstract: A time delay synchronous control scheme for a power supply, which has multiple outputs and tight output regulations, is provided. The switching mode power supply includes (1) a front-end DC/DC converter with current mode output, which can be a LLC Series Resonant converter (SRC) or a flyback converter; (2) one or several post buck converters directly cascaded from the output capacitor of the front-end DC/DC converter; (3) a new scheme of time delay synchronous control used to make the post buck synchronize and modulate from the front-end LLC-SRC or flyback converter. The proposed time delay synchronous control circuit can eliminate the conventional input filter of the post buck converters, as well as reduce the ripple current on the output capacitor of the front-end DC/DC converter, as a result of which, a high efficiency for the overall architecture can be obtained.

Abstract: The present invention relates to a digital current share apparatus and method for supplies in parallel wherein a digital current sharing is used to eliminate oscillations during current sharing by raising current in steps until the currents in power supplies in parallel are brought within a certain tolerance of one another.

Abstract: An uninterruptible power supply (“UPS”) is provided with a backup power supply that has an adjustable reserve power level that is based on a user's input. The UPS provides reserve power that can later be utilized to reactivate the UPS after a shutdown or deactivation state has occurred, when a user demand for reserve power is received. The UPS utilizes a rechargeable battery that can supply stored AC power when the AC power line input voltage level falls below a threshold level and a shutdown has occurred. The user can adjust the reserve level in proportion to her input and the user can later reactivate the UPS to supply stored AC power for a period of time. In one embodiment, the user can execute computer code on her computer that can remotely adjust the reserve power level, based on a measurement of the backup power available from the UPS.

Abstract: An electric power transmission system that isolates a local AC transmission network from a surrounding AC system includes a local AC load center having a plurality of local AC loads, and a distribution feeder serving the plurality of local AC loads and at least one distant electric power generating station or other power source for supplying AC power to the local AC load center. A complete or partial DC transmission ring is interposed between the local AC load center and the distant electric power generating station for isolating the AC power received from the distant electric power generating station from the local AC load center by converting the AC power to DC power. The DC power is re-converted into AC power based on load requirements and the distribution feeder supplies the AC power while all local AC loads are isolated from the distant electric power generating station.

Abstract: An adapter allows a remote device to use a contactless power supply. The adapter has a contactless power interface for receiving power from a contactless power supply and a power regulator for supplying power to the remote device. The adapter may have a rechargeable power source for operating the adapter and a power regulator.

Abstract: According to one example a linear translation stage is provided. The linear stage includes a first portion (e.g., a base portion) and a second portion (e.g., a stage portion) configured for relative translation with respect to each other. One of the first portion or the second portion has a coil associated therewith and the other of the first portion or the second portion has a magnetic source associated therewith. The magnetic source may include one or more magnets to produce a magnetic field that generally encompasses the coil such that current through the coil causes a force on the coil, thereby causing translation of the first portion relative to the second portion.

Abstract: An actuator using a permanent magnet comprises: a first core and a second core facing each other with a certain gap and having a space therein; a hollow bobbin coil fixedly installed at one side of the space for generating a magnetic force at the time of a current supply; a stator fixedly installed at another side of the space with a certain gap from the bobbin coil; a mover linearly moving in the space by a magnetic force generated by the bobbin coil, and having a rod portion exposed to outside of the first core and the second core; and a permanent magnet fixedly installed at an inner surface of the space for fixing the mover. In the actuator, one bobbin coil is provided thus to lower a production cost, and a driving function is enhanced. Accordingly, the actuator can be widely applied to a vacuum circuit breaker or a high speed transfer switch requiring a fast driving.

Abstract: A stepper motor includes a rotor having equally spaced rotor teeth defining a full step angle, and a stator with stator poles wound with coils that can be driven in a series of phases so as to magnetically interact with the rotor to produce stepping motion. The stator poles have teeth organized into two groups when there is an even number of stator teeth per pole, or into three groups for an odd number of stator teeth per pole. The stator teeth have an average pitch different from the rotor's tooth pitch, but the groups of stator teeth are also displaced relative to other groups by a specified offset angle of one-half or one-quarter step to double the number of detent positions, and to displace such detent positions from full one-phase ON or two-phase ON positions.