Abstract: A transmitting or receiving coil assembly for nuclear spin tomographs comprises a multi-layer structure of conducting layers forming inductive components on an insulating support layer. Discrete components such as capacitors are accommodated in recesses of the support layer. Reinforcement members make it possible to increase the mechanical stability of the arrangement.

Abstract: A magnetic resonance system that has a magnet system that generates magnetic fields in an excitation region, allowing nuclei in an examination subject in the excitation region to be excited to emit a magnetic resonance signal. A reception antenna device with multiple local coils for reception of the magnetic resonance signals is arranged in proximity to the examination subject, and has a base part and an attachment part. The attachment part can be placed on the base part such that the examination subject is located between the base part and the attachment part (6). The multiple local coils are respectively connected with an evaluation device for evaluation of magnetic resonance signals.

Abstract: A portable locator for detecting a buried object characterized by an electromagnetic (EM) field emission employing three-dimensional (3D) sensor arrays each having three substantially-identical EM field sensors disposed on a flexible annular wall having a radial centroid defining a sensing axis. The flexible annular sensors are retained in substantial concentricity with the corresponding sensing axes disposed in substantial mutual orthogonality. A pair of 3D sensor arrays disposed on a first axis substantially orthogonal to a second axis defined by another pair of EM field sensors each having a sensing axis disposed along the second axis. The locator introduces a user-reconfigurable user interface (UI) employing a “sticky” ratcheting audio UI and a hollow hinge assembly for redisposing the sensor assembly from an operating to a storage disposition.

Abstract: Disclosed is a method of estimating a maximum output of a battery for a hybrid electric vehicle (HEV). The method comprises extracting maximum charge/discharge outputs of the battery depending on a plurality of charged states (SOC) of the battery under which the vehicle is able to be driven and calculating an interrelation between them; extracting maximum charge/discharge outputs of the battery at plural temperatures under which the vehicle is able to be driven, and calculating an interrelation between them; extracting degradations of outputs of the battery as a capacity of the battery is discharged during the traveling, and calculating an interrelation between them; and based on the interrelations obtained, estimating a maximum output of the battery using a function.

Abstract: This is an electronic scanning probe, preferably made up of at least two sensing elements, each sensing element substantially surrounded by reference electrodes. These sensing elements are separated at a distance that causes little or no cross-interference to take place between these sensing elements when positioned in concert with a surface of interest. Ideally, this probe is used in electrostatic marking systems where an electrostatic charge is placed onto a receiving surface.

Abstract: A signal whose voltage level fluctuates with respect to a high voltage is measured with favorable accuracy.

Abstract: The errors related to the resistance of test conductors and sense/load resistances for a pulse I-V measurement system are determined by making open circuit and through circuit measurements using a combination of DC and pulse instrument measurements.

Abstract: A connection unit for electrically connecting a DUT mounting board, on which an IC socket is mounted, with a testing apparatus for testing an electronic device inserted into the IC socket, the connection unit has a holding substrate provided to face the DUT mounting board and a connection-unit-side connector, which is provided on the holding substrate to be able to change a position of the connection-unit-side connector on the holding substrate, for being connected to a performance-board-side connector included in the DUT mounting board.

Abstract: A chemical impedance detector having several electrodes situated on or across a dielectric layer of a substrate. The electrodes may be across or covered with a thin film polymer. Each electrode may have a set of finger-like electrodes. Each set of finger-like electrodes may be intermeshed, but not in contact, with another set of finger-like electrodes. The thin-film polymer may have a low dielectric constant and a high porous surface area. The chemical impedance detector may be incorporated in a micro fluid analyzer system.

Abstract: A touch sensor assembly. The touch sensor assembly may include a housing, at least one touch sensor and a sensor cover. The sensor cover may identify a touch area associated with each touch sensor. The housing may form a water tight cavity for the sensor cover and the touch sensor when coupled to an housing cover. A raised dome may be provided, e.g. on the sensor cover or another element, to provided tactile feed back. LEDs may be provided for illuminating the touch areas and/or sensing ambient light. A controller may control the illumination level of the LEDs in response to sensed ambient light. Adjacent key suppression algorithms are also provided.

Abstract: A sensor chip for measuring of structures in a finger surface includes an electronic chip provided with a number of sensor electrodes for capacitance measurements. The chip further includes a first layer comprising a metal or another electrically conducting material over and coupled to the sensor electrodes and a first dielectric layer substantially covering the first metal layer.

Abstract: A visual inspection apparatus and method using the scanning electron microscope are disclosed. An electron beam is scanned repeatedly on a sample, and an inspection and a reference image are generated by the secondary electrons generated from the sample or reflected electrons. From the differential image between the inspection image and the reference image, a defect is determined. The number of pixels in the generated image along the direction of repetitive scanning by the electron beam can be changed.

Abstract: One or more test probe access structures for accessing vias on a printed circuit assembly and method of fabrication thereof is presented. Each test probe access structure is conductively connected to a via at a test probe access location above an exposed surface of a via to be accessible for probing by a test probe.

Abstract: A method and apparatus for probing an electrical signal. The apparatus comprises simplified circuit, comprising an input pin for receiving an input signal having an inductance and parasitic capacitance associated therewith and a first resistor coupled between the input pin and an output. A first capacitor is coupled between the first resistor and the output, and a ground. A second capacitor and an associated inductance in series are coupled between the junction of the first resistor and first capacitor and a parallel circuit arrangement. The parallel circuit comprises a second resistor and second associated inductance coupled in parallel between the first inductor and ground.

Abstract: The objective of the present invention is to provide a type of probe assembly with a long lifetime and low cost, as well as a type of probe card using same. Probe assembly 100 attached on the probe card has probe holder 200 that holds plural probes Q at prescribed positions and leaf spring mechanism 300 with probe holder 200 attached on it. Said leaf spring mechanism 300 has leaf spring cover 360 connected to probe card base plate 410 and leaf spring 330, as well as pin row base plate 310 with probe holder 200 attached on it. When the bump electrodes are contacted, pin row base plate 310 can move towards leaf spring cover 360 via leaf spring 330.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A contactor configured to be electrically connected to the terminals of an electronic component is disclosed. The connector includes multiple contact electrodes contacting the terminals of the electronic component and multiple elastic electrodes each composed of an electrically conductive elastic body. The elastic electrodes generate a pressing force for pressing the contact electrodes against the terminals of the electronic component. The contact electrodes are separable from the elastic electrodes.

Abstract: An interface assembly provided at a test head, for connecting a probe card to the test head. The interface assembly includes an interface comprising an interface body and a coaxial connector supported by the interface body, and a casing for enclosing a dry gas that is introduced between the test head and the probe card and leaks into the test head through a gap formed by the interface (20) in a state where the coaxial connector is engaged with a mating coaxial connector provided at the probe card.

Abstract: A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

Abstract: A method and system for defect localization including (i) receiving a test structure that includes at least one conductor that is at least partially covered by an electro-optically active material; (ii) providing an electrical signal to the conductor, so as to charge at least a portion of the conductor; and (iii) imaging the test structure to locate a defect.

Abstract: Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide high speed pin continuity and pin-to-pin short tester circuits. Such circuits include a threshold driver, a test driver, and a comparator. An input of the threshold driver is electrically coupled to a voltage threshold, and an output of the threshold driver is electrically coupled to a test pin node via a current limiting resistor. An input of the test driver is electrically coupled to a drive data input, and an output of the test driver is electrically coupled to the test pin node. One input of the comparator is electrically coupled to the test pin node, and the other input of the comparator is electrically coupled to a threshold comparator input.

Abstract: A pixel circuit flows a current having a current value corresponding to a test voltage without intervening any display element.

Abstract: A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memory cell. The memory cell PMV may be used, for example, to measure the amount of margin available for memory cell flips and how process variation affects the memory cell write margin. The memory cell PMV is implemented as a plurality of shift register bits interconnected as a ring oscillator, where each shift register bit is comprised of a memory cell. By adjusting the drive current for each memory cell and measuring the resultant change in oscillation frequency of the ring oscillator, information may be obtained concerning process variation and its effect on memory cell performance.

Abstract: An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and are temporarily activated responsive to a transition in an input signal to the driver to effectively decrease the output impedance and boost the pull-up and pull-down time response characteristics of the driver during the transition of the output. The additional output stages are active only for a small part of a cycle, so the slew rate is thereby increased while the effective output impedance during most of the cycle is essentially unaffected.

Abstract: A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.

Abstract: A circuit for enabling an IC having a normal mode for performing normal functions and a program mode for programming settings of the IC to use same pins in both modes. The circuit includes an input circuit for receiving the input data; internal circuits for processing the input data in the normal mode; a program circuit for processing the input data in the program mode, a program enable circuit for providing a program enable signal for switching the IC from the normal to the program mode; and a demultiplexer circuit for providing the input data as normal data to internal circuits when the IC is in the normal mode and as program data to the program circuit when the IC is in the program mode.

Abstract: An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.

Abstract: A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaining logic blocks. The level of activity may be monitored by observing the input and output pin of the logic blocks. The PLD further includes a plurality of driven wires defining a routing pattern between the array of logic blocks. When one of the array of logic blocks detect inactivity in any one of the remaining logic blocks for a certain duration, the one of the array logic blocks transmits a signal invoking a sleep mode for the inactive logic blocks. A sleep transistor with a threshold voltage level that is capable minimizing the leakage current is associated with each of the remaining block. The gate of the sleep transistor receives the signal transmitted by one of the array logic blocks and the signal switches off the sleep transistor.

Abstract: Some embodiments provide a barrel shifter on a configurable integrated circuit (IC). The barrel shifter has a first set of tiles and a second set of tiles with configurable circuits. The barrel shifter also has a first set of non-neighboring offset connections (NNOCs) connecting at least one of the tiles in the first set to at least one of the tiles in the second set.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC.

Abstract: For raising low voltage levels of a voltage range without over-broadening the voltage range, a first stage voltage level shifting circuit, which is capable of raising an upper bound of its input voltage range, is coupled to a second voltage level shifting circuit, which is capable of raising both an upper bound and a lower bound of its input voltage range. Therefore, a two-stage voltage level shifting module, which is generated by coupling the first voltage level shifting circuit to the second voltage level shifting circuit, is capable of providing appropriate voltages for external I/O devices having different biasing voltage ranges, where an upper bound and a lower bound of each of the provided biasing voltage ranges precisely indicates a digital logic 0 or a digital logic 1 indicated by a digital signal.

Abstract: A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

Abstract: A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor test apparatus. The impedance matching circuit includes: a resistance; an analog computing unit which multiplies a voltage from one end of the resistance by a predetermined number, subtracts a voltage from the other end of the resistance from the voltage multiplied by the predetermined number and outputs a resultant voltage; and a buffer which outputs a signal from the analog computing unit with low impedance. The impedance matching circuit produces an output signal from the DUT with low impedance, thereby sufficiently driving the transmission line.

Abstract: A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.

Abstract: A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the gate electrode of the transistor. An initial voltage before a bootstrap effect can be set to the potential of the power source, which is independent of the threshold voltage of the transistor. Therefore, the source output of the transistor rising or dropping due to the bootstrap effect is not affected by variations that depend on the threshold voltage of the transistor.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.

Abstract: A duplexer is provided. The duplexer includes a first band pass filter (BPF) coupled to a first signal port and a second signal port; and a second BPF coupled to the first signal port and a third signal port, each of the first BPF and the second BPF including a first resonance circuit which comprises a plurality of first resonators coupled in series; a second resonance circuit which comprises a plurality of second resonators coupled in series; and a third resonance circuit which comprises a plurality of third resonators coupled in parallel and formed in divided lines coupling the first and second resonance circuits.

Abstract: A semi-dual reference voltage data receiving apparatus includes a first input buffer, a second input buffer, and a phase detector wherein the first input buffer includes a first input receiving unit, a first sense amplifier, and a first current offset controlling unit. The first sense amplifier senses and amplifies the voltage difference between the voltage of a first terminal of a first input transistor and the voltage of a first terminal of a second input transistor. The first current offset controlling unit controls the offset of the current that flows through the second terminal of the second input transistor.

Abstract: A current mirror circuit includes p-type MOS (PMOS) transistors, whereby the current flowing when the input voltage is “H” is interrupted when an output node of the current mirror circuit goes from “L” to “H,” so that a cascode-connected PMOS transistor within the current mirror circuit is automatically turned OFF. The gates of PMOS transistors within the current mirror circuit are connected by a signal line directly to the output node. The rise time of the output voltage of the current mirror circuit and the consumption current can thus be reduced.

Abstract: An upper end voltage and a lower end voltage of a current detection resistor Rs are supplied, via first and second switches S1 and S2, to one end of a main capacitor Ci. A reference voltage VREF is supplied, via a third switch S3, to the other end of the main capacitor Ci. The operational amplifier OP has a negative input terminal to which a voltage of the other end of the main capacitor Ci is supplied and a positive input terminal to which the reference voltage VREF is supplied. The circuit performs an operation for charging the main capacitor Ci with a voltage corresponding to a difference between the lower end voltage and the reference voltage in a state where the first and third switches S1 and S3 are turned on and the second switch S2 is turned off.

Abstract: A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.

Abstract: A voltage buffer and the source driver thereof are disclosed. The above-mentioned voltage buffer includes an operational amplifier and an overdriving unit, wherein the operational amplifier outputs an output voltage. The overdriving unit is coupled between an input voltage and the operational amplifier for comparing the input voltage with the output voltage and outputting an overdriving voltage to the positive input terminal of the operational amplifier. Herein if the input voltage is greater than the output voltage, the overdriving voltage is greater than the input voltage; if the input voltage is less than the output voltage, the overdriving voltage is less than the input voltage; if the input voltage is equal to the output voltage, the overdriving voltage is equal to the input voltage.

Abstract: The present invention provides a method and apparatus for detecting a continuous current of a switching current. A current signal is produced in response to a switching current of the magnetic device. By sampling the waveform of the current signal in response to the enabling of a switching signal, a first current signal and a second current signal are generated. A continuous current signal is produced according to the first current signal and the second current signal. The continuous current signal is corrected to the continuous current of the switching current.

Abstract: A frequency divider comprises a first differential input pair, a second differential input pair, a first capacitive element having first and second ends, a second capacitive element having first and second ends, and four current sourcing elements. The first differential input pair includes first and second transistors that receive a differential local oscillator signal. The second differential input pair includes first and second transistors that receive the differential local oscillator signal. The first capacitive element communicates with first terminals of the transistors of the first differential input pair. The second capacitive element communicates with first terminals of the transistors of the second differential input pair. The four current sourcing elements respectively communicate with the first terminals of the transistors of the first and second differential input pairs.

Abstract: In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Ith cycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the differential clock signal divided by N, N being equal to I plus a fraction F.

Abstract: A power-on reset circuit includes a trigger circuit that indicates when a power supply has been turned on, and when the supply has reached a voltage level that is sufficient for normal chip operation. For chips that contain a crystal oscillator, the power-on reset circuit also includes logic that determines the duration of the crystal warm-up delay.

Abstract: A delay limit detect circuit can determine the delay of a current steering delay cell, like those utilized in a voltage controlled oscillator (VCO), by monitoring a current (ISENSE) that tracks a delay cell current (I2). When the monitored current (ISENSE) outside of a limit, a signal LIMIT can be activated. A monitored current (ISENSE) can be generated by a control replica circuit having the same circuit component types as a control circuit within a delay cell. Such limit detection can provide a way to prevent a ring VCO from entering a runaway state, particularly in cases where a maximum frequency can be reached before a maximum control voltage is reached.

Abstract: A kick back compensated charge pump circuit with kicker capacitor is disclosed. The charge pump circuit comprises a pump up circuit that comprises a first PMOS transistor and a second PMOS transistor in a cascode configuration and coupled to a first kicker capacitor. The charge pump circuit also comprises a pump down circuit that comprises a first NMOS transistor and a second NMOS transistor in a cascode configuration and coupled to a second kicker capacitor. The kicker capacitors increase the speed of the charge pump circuit by charging and discharging a gate to source capacitance (CGS) of the pump up circuit and of the pump down circuit of the charge pump circuit.