Abstract: A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A fine delay is implemented upon the reference signal based upon a phase shift between the reference signal and a feedback signal. Providing the fine delay includes switching on a capacitive delay. A synchronized output signal is generated based upon the fine delay.

Abstract: A digital DLL circuit includes: a register configured to hold a delay target value; an oscillator; a first counter configured to count an external reference clock or an oscillation output from the oscillator; a second counter configured to count the oscillation output from the oscillator or the external reference clock in every measurement cycle determined by the first counter; and a digitally-controlled variable delay circuit. The DLL circuit further includes a control circuit configured to control the reset and activation of the first counter and the second counter, and control the stop of the first and second counters according to need, based on a count value of the first counter, the control circuit subjecting a count value of the second counter and the delay target value of the register to a digital arithmetic operation, and supplying the variable delay circuit with a result of the arithmetic operation as a delay control value.

Abstract: An output circuit comprises an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit, and a second slew rate control circuit. The first output transistor and the second output transistor are coupled in series. The first slew rate control circuit is coupled between the first output transistor and a first power supply terminal. The second slew rate control circuit is coupled between the second output transistor and a second power supply terminal. The input node is coupled to gates of the first output transistor and the second output transistor. The output node is coupled to a common node of the first output transistor and the second output transistor.

Abstract: A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.

Abstract: A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received, and a clock control circuit to receive the clock and the input, to determine whether the output will be changed by the input and to provide the clock to the clocked gate if the output will be changed by the input.

Abstract: Various embodiments include a latch having a node to receive input information, and a first pseudo-inverter with a first input node, a second input node, and an output node to generate output information based on information at the first and second input nodes. The latch may have a feedback circuit to generate feedback information based on at least the output information. The latch may also have a select circuit to selectively transfer the input information and the feedback information to the first and second input nodes. Other embodiments including additional apparatus, systems, and methods are disclosed.

Abstract: In a phase compensation circuit having a resistance connected to the output side of an error amplifier, a capacitor, and a conductance amplifier functioning as a capacitance amplifier circuit, capacitance is amplified by the conductance amplifier and used, whereby an essentially required capacitance is ensured, even when the capacitance of the capacitor is small.

Abstract: A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: A semiconductor integrated circuit includes a charge pump circuit that repeats charge and discharge of a capacitor based on a clock signal when an ON/OFF control voltage is ON; a first delay circuit that delays the ON/OFF control voltage; a switch that shorts an output of the charge pump circuit and a GND input terminal when the delayed ON/OFF control voltage is OFF and opens when the delayed ON/OFF control voltage is ON; a first circuit block that is driven by a power voltage which is supplied from a power source input terminal and the charge pump circuit; and a second circuit block that is driven by a power voltage which is supplied from the power source input terminal and the GND input terminal. The first and second circuit blocks are mounted on the same semiconductor integrated circuit chip.

Abstract: A low noise multiphase charge pump comprises a plurality of capacitors and a plurality of switches configured as a network, the switches are so switched that the charge pump operates in at least three phases by turns, and the operational durations and the operational currents of the phases are preferably balanced, so as to reduce the noise of the charge pump.

Abstract: A voltage pumping device is disclosed. The device may include a voltage level detector for detecting a level of a voltage fed back thereto and generating a voltage pumping enable signal according to the detected voltage level, an oscillator for operating in response to the voltage pumping enable signal and generating a desired pulse signal in a normal operation mode, a clock supply controller for receiving an external clock signal, operating in response to the voltage pumping enable signal and outputting the external clock signal in a low-power operation mode, and a voltage pump for performing a voltage pumping operation in response to the pulse signal from the oscillator in the normal operation mode and performing the voltage pumping operation in response to the clock signal from the clock supply controller in the low-power operation mode.

Abstract: A method and apparatus for power supply rejection in a reference voltage circuit using a variable resistance circuit.

Abstract: A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor is connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches.

Abstract: A current difference circuit is provided. The currents difference circuit provides an output current that is the difference of two input currents, while employing feedforward to clamp the output current. The current difference circuit brings the lower of the two input currents along with the higher of the two such that the difference between them is always constant if the difference is beyond the clamp range.

Abstract: A constant current circuit and a constant current generating method, wherein when a voltage in substantially no temperature dependence is applied to an element to output a constant current, temperature dependence of the element can be cancelled. A current indicative of first temperature dependence, which is generated by applying a bias voltage in substantially no temperature dependence to a first current setting section, and a current indicative of second temperature dependence, which is generated by applying a bias voltage in substantially no temperature dependence to a second current setting section are added and outputted as a constant current in substantially no temperature dependence.

Abstract: An FM detector circuit includes an unbalanced/balanced conversion circuit, a signal synthesis circuit, a parallel circuit including a first diode connected between a first balanced output terminal of the unbalanced/balanced conversion circuit and one signal input terminal of the signal synthesis circuit and a resonator, a parallel circuit including a second diode connected between a second balanced output terminal of the unbalanced/balanced conversion circuit and the other signal input terminal of the signal synthesis circuit and a capacitor element, and a low-pass filter connected to an output terminal of the signal synthesis circuit.

Abstract: An amplifier circuit uses capacitor as voltage sources so that the amplifier can achieve high precision gain without either ratioed capacitors or absolute value of capacitors or resistors. In one embodiment, the amplifier circuit includes two or more capacitors that are each charged up to the input voltage during the sample phase. Then, during the hold phase, the switching network operates to connect the two or more capacitors in series between the input and output terminals of an operational amplifier, thereby generating an output voltage being N times the input voltage, N being the total number of capacitors connected in series. The amplifier circuit of the present invention is capable of achieving very high precision gain with very high slew rate. In particular, the amplifier circuit achieves very accurate integer gain (1×, 2×, 3×, and so on). Fractional gains can also be obtained with the use of a ratioed capacitor.

Abstract: A dual path chopper-stabilized amplifier (100) includes first (11) and second (11A) chopping/notch-filtering paths, each including an input chopper (9,9A), a transconductance amplifier (2,2A), and a notch filter (15,15A). Chopping and notch filtering in the first path are controlled by first (CHOPCLK) and second (FILTERCLK) clock signals, respectively. Chopping and notch filtering in the second path are controlled by the second (FILTERCLK) and first (CHOPCLK) clock signals, respectively. Outputs of the first (15) and second (15A) switched capacitor notch filters are combined to provide an amplifier output signal (23A,B) that updates a capacitance (C4) at 4 times the frequency of the filter clock signal, to thereby improve amplifier stability without increasing clock frequency.

Abstract: A signal processor has an input terminal and an output terminal for use in a wireless transmitter, for generating a radio frequency signal suitable for transmission, either with or without further power amplification. The signal processor separates an input signal into first and second processing paths, the first processing path generating a pulse train signal which is a digitised envelope signal, and the second processing path comprising phase processing means operable to generate a constant envelope phase signal. An RF switch is operable to switch the phase signal by means of the pulse train signal.

Abstract: A class D amplifier is provided. The class D amplifier includes a modulator and a class D power stage. The modulator provides a PWM output signal to the class D power stage. For each pulse of the PWM input signal, the class D amplifier provides a corresponding pulse in the PWM output signal, such that the pulse is terminated when the area under the pulse of the output of the class D power stage is substantially equal to the area under the pulse of the corresponding PWM input signal. In this way, the class D amplifier provides instantaneous per-pulse PWM feedback.

Abstract: An amplifier circuit with current noise reduction employs first and second variable impedance devices between a signal source and an amplifier. A modulation frequency generator establishes a modulation frequency fmod to alter the first and second impedance values out of phase from one another at the modulation frequency so that the sum of the first and second impedance values at the input of the amplifier is relatively constant. The modulation at frequency fmod shifts the signal to side bands about the modulation frequency. The output from the amplifier is passed to a bandpass filter centered on the modulation frequency in order to remove all frequencies outside the bandwidth of interest. The signal itself is recovered by demodulating the output of the bandpass filter using a synchronization signal that is derived from the modulation signal.

Abstract: Systems and methods for improving the stability of feedback and/or feed-forward subsystems in digital amplifiers. One embodiment comprises a digital pulse width modulation (PWM) controller. The controller includes an input for receiving a digital audio input signal and is configured to generate a PWM output signal based on the input signal at an output. The controller also has control inputs for receiving external audio correction signals such as feedback and power supply feed-forward signals. The controller has correction circuitry for processing the received external control signals and modifying the input signal based on these signals. Fault detectors monitor fault conditions at various locations within the correction circuitry, and a protection control unit receives fault signals from the fault detectors and modifies operation of the controller in response to the fault signals.

Abstract: Systems, methods, and apparatuses are provided for linear envelope elimination and restoration transmitters that are based on the polar modulation operating in conjunction with the orthogonal recursive predistortion technique. The polar modulation technique enhances the battery life by dynamically adjusting the bias level. Further, the analog orthogonal recursive predistortion efficiently corrects amplitude and phase errors in radio frequency (RF) power amplifiers (PA) and enhances the PA output capability. Additionally, even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. Also, the predistortion scheme, which uses instantaneously feed-backed envelope distortion signals, allows for correction of any distortion that may occur within the correction loop bandwidth, including envelope memory effects.

Abstract: A multi-mode RF amplifier is disclosed having high and low output power modes composed of two power paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (first and second) paths. While in the low power, LP, mode, power is delivered via second path only which is designed to reduce current consumption and improve efficiency under low power (backoff) operation. The multi-mode RF amplifier has power amplifiers in one embodiment, but no mechanical or electronic switches. The multi-mode amplifier utilizes impedance matching circuits where the impedances change under different power amplifier bias conditions in order to optimize current consumption under both modes of operations and is power efficient for portable applications. Note that, in a preferred embodiment, even in the HP mode more power is delivered to the second power path than to the first power path.

Abstract: A transimpedance amplifier (TIA) circuit comprises an input and an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to the input. A bias stage generates a second signal and that is DC coupled to the input. An output stage is driven by the first signal from the amplifying stage and the second signal from the bias stage.

Abstract: A power amplifier includes a main amplifier having a first output. An auxiliary amplifier has a second output coupled to the first output. A splitter splits a RF input into a first input provided to the main amplifier and a second input delayed by one/quarter wavelength provided to the auxiliary amplifier. A bias control is coupled to the auxiliary amplifier for controllably switching operation of the power amplifier between two different modes of operation.

Abstract: A Doherty amplifier includes a Doherty amplification circuit and an active bias circuit. The active bias circuit includes an average power detector for detecting a value of a voltage representing an average power of an input signal, an envelop detector for detecting an envelope of the input signal, a threshold calculator for calculating a boundary value of the envelop detected by the envelope detector based on the value of the voltage detected by the average power detector, and a voltage limiter for limiting the envelop detected by the envelope detector below a predetermined value. The bias voltage corresponding to the average power of the input signal is applied to the Doherty amplification circuit.

Abstract: Recently, the use of class D audio amplifiers has become more and more widespread. In contrast to the generally employed class AB linear amplification technology, class D allows for improved efficiency. However, the class D principle is known for its poor distortion characteristics. According to the present invention, switching delays of the end stage (6) are measured and used for compensating distortions caused by the dead time of the end stage (6). This is done by modifying the switching delay of the power stage. In this way, the output pulse duration is corrected to reflect the input duty cycle. Advantageously, variations in the switching-time due to device property spread, aging, current and temperature may be compensated.

Abstract: A switch mode power amplifier includes a transistor responsive to input signals above 1.0 GHz and which includes one terminal coupled to ground and another terminal conductively coupled to a power source. A resonant circuit coupled the second terminal to an output with a resistive load coupled across the output and ground. When the transistor is turned on the second terminal is coupled to ground and when the transistor is turned off, current from the power supply to the second terminal is steered into internal capacitance of the transistor and causes voltage on the second terminal to rise to a maximum value and then decrease, the voltage at the second terminal being coupled to the output terminal through the resonant circuit. In preferred embodiments, the transistor comprises a compound semiconductor field effect transistor with the first terminal being a source terminal and the second terminal being a drain terminal.

Abstract: A voltage-controlled current source includes a current source having temperature dependency, a voltage source having process dependency, a first signal conversion circuit which generates second voltage having temperature dependency and process dependency by use of current of the current source and first voltage of the voltage source, a second signal conversion circuit which converts a first control signal used to control transfer conductance into a second control signal by using the second voltage as a reference, and a voltage-controlled current source circuit whose transfer conductance is controlled according to the second control signal.

Abstract: A variable gain amplifier comprising a differential input amplifier comprising a pair of transistors each having an input across which an input voltage is provided, the transistors being coupled such that each transistor is provided in series with a respective current source providing a reference current and whereby a current is developed across a resistor element coupling the transistors that is proportional to the voltage between the inputs; further comprising further transistors each coupled in series with a transistor of the transistor pair, and wherein the further transistors are arranged such that a current is developed in each further transistor due to the voltage provided across the inputs that is substantially equal to, in one further transistor, a sum of the reference current and the current in the resistor element, and in the other further transistor, a difference between the reference current and the current in the resistor element; further comprising a gain stage for developing currents equal to

Abstract: A current feedback-type operational amplifier comprising multiple input parts and one output part, wherein each of the multiple input parts comprises a first input terminal, a second input terminal, and an output terminal, the signals input from the first input terminal are buffer amplified and output to the second input terminal, and current is output to the output terminal in an amount corresponding to the current that flows to the second input terminal; the output terminal part comprises an input terminal and an output terminal, signals obtained by adding in terms of current the signals of all of the input parts are input to the input terminal, and the signals input to the input terminal are converted to voltage signals, amplified, and output to the output terminal; and one of the above-mentioned input parts is made effective and the other input parts are made ineffective in response to first external signals, the impedance of the first input terminal, the second input terminal, and the output terminal of

Abstract: A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).

Abstract: A microwave generator comprises: a high-frequency power section that includes a diamond SAW oscillator and outputs a high-frequency signal outputted from the diamond SAW oscillator to a subsequent stage; and a waveguide unit that emits the high-frequency signal inputted from the high-frequency power section in a form of microwave.

Abstract: An LC resonant circuit of an oscillator includes a parallel circuit of an inductor, a first fine adjustable capacitor and a first capacitor bank, and a series circuit of a second fine adjustable capacitor and a second capacitor bank. A frequency conversion gain of the oscillator is the sum of a frequency conversion gain of the oscillator based upon the first fine adjustable capacitor which decreases according to increase of a capacitance value of the capacitor bank and a frequency conversion gain based upon the second fine adjustable capacitor which increases according to increase of a capacitance value of the second capacitor bank. Accordingly, an LC resonant circuit for an oscillator with reduced fluctuation of a frequency conversion gain, and an oscillator and a data processing equipment using the same are provided.

Abstract: A harmonic-rejection modulation device is provided, which includes a phase splitter, a low pass filter, and a modulator. Based on a square wave, the phase splitter generates a plurality of unfiltered local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The low pass filter filters the high frequency components of the unfiltered local oscillating signals to generate a plurality of local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The modulator modulates a baseband signal with the local oscillating signals, wherein the third harmonics of the local oscillating signals are eliminated by the modulation process of the modulator. The invention also provides a method of modulating a baseband signal.

Abstract: The present invention relates to an amplitude modulation apparatus, an amplitude limiting method, and a transmission apparatus for performing amplitude limitation on an orthogonally modulated signal. The amplitude modulation apparatus, the amplitude limiting method, and the transmission apparatus enable peak value suppression of a transmission wave with a simple structure. An amplitude limiting apparatus that performs amplitude limitation on an orthogonally modulated signal includes first amplitude limiting means (31, 32) for limiting to predetermined amplitudes the amplitudes of an I-component and a Q-component of the orthogonally modulated signal that are orthogonal to each other, and second amplitude limiting means (33-41) for performing further amplitude limitation on the I-component and the Q-component according to the difference between the amplitude-limited I-component and Q-component obtained by the first amplitude limiting means.

Abstract: A polar-based modulator includes an amplitude signal generator operating at a set gain and a command module that selects an appropriate one parameter lookup table based on an identification of the current network communication system. The command module receives a digital representation of the desired amplitude and using the received digital amplitude and selected parameter lookup table determines control commands used by a scalar to appropriately modulate an amplitude modulated signal output from the amplitude signal generator. Use of the parameter lookup table and command module in the digital realm eliminates the complexities of comparable functionality in the analog realm. Further, operating the amplitude signal generator at a set gain and scaling the output eliminates the complexities associated with generating an appropriately amplified signal within the amplitude signal generator and improves the overall efficiency for generating such an amplitude modulated signal.

Abstract: A transmission line pair has two transmission lines placed adjacent to each other in parallel to a signal transmission direction of the transmission lines as a whole. Each of the transmission lines includes a first signal conductor which is placed on one surface of a substrate formed from a dielectric or semiconductor and which is formed so as to be curved toward a first rotational direction within the surface, and a second signal conductor which is formed so as to be curved toward a second rotational direction opposite to the first rotational direction and which is placed in the surface so as to be electrically connected in series to the first signal conductor. A transmission-direction reversal portion in which a signal is transmitted along a direction reversed with respect to the signal transmission direction of the transmission lines as a whole is formed so as to include at least part of the first signal conductor and part of the second signal conductor.

Abstract: A circuit assembly has a conical inductor disposed in a slot formed in a substrate.

Abstract: Conductor segments are positioned within a transmission line structure in order to generate microwave pulses. The conductor segments are switchably coupled to one or the other of the transmission lines or to each other, in parallel with the transmission line structure. Microwave pulses will be induced in the transmission line by closing the switches in a controlled manner to discharge successive segments or successive groups of segments into the transmission lines. The induced waves travel uninterrupted along the transmission lines in a desired direction.

Abstract: A tunable high impedance surface device (100) includes a conductive ground plane (105) and a plurality of conductive elements (110-114) electrically connected to the conductive ground plane (105). The device (100) also includes a plurality of capacitive elements (120-124) operable to vary a predetermined electromagnetic characteristic of the apparatus and standoffs (130, 132) between the plurality of capacitive elements (120-124) and the plurality of conductive elements (110-114). In one form, laser-drilled and electrically conductive micro-vias (136, 138) extend through the standoffs (130, 132) thereby electrically connecting the plurality of capacitive elements (120-124) to a data bus (140). The capacitive elements (120-124) may be integral with a circuit board (144) that supports the plurality conductive elements (110-114).

Abstract: Apparatus and methods are provided that are adapted to match the impedance of an electrical load to an impedance of an electrical signal generator. The invention includes providing a plurality of electrical components adapted to collectively match the impedance of the electrical load to the impedance of the electrical signal generator. The electrical components are arranged symmetrically and concentrically about an axis. Additionally, the invention may also include a first connector adapted to electrically couple the electrical signal generator to the electrical components. Additionally, the invention may also include a second connector adapted to electrically couple the load to the electrical components. Numerous other aspects are provided.

Abstract: A monolithic thin film variable power divider is disclosed for variable power level distribution. The thin film power divider includes a substrate having a main surface, a first stage and a second stage, each formed as thin film networks on the main surface of the substrate. The first stage includes a plurality of transmission lines, at least one of the transmission lines having a variable dielectric deposition layer providing variable power level distribution. The variable dielectric deposition is a paraelectric, such as Barium-Strontium-Titanate. The second stage includes a hybrid combiner. The thin film power divider is capable of operating at frequencies extending into the millimeter wave spectrum. The thin film power divider provides a cost effective device that varies the balance of power through a multiport RF distribution network while simultaneously maintaining little, or low, frequency dispersion during the dynamic dissemination process.

Abstract: A power distribution and combination circuit for distributing a signal input from a first port to a second and third ports and combining signals input from the second and the third port so as to be outputted to the first port. A transmission line of the power distribution and combination circuit has a first end connected to a power (the first port) and a second end connected to the second and third ports for distributing and combining the input signals. A second transmission line has a first end connected directly to the second end of the transmission line and a second end connected to the third port so as to be unified with the transmission line.

Abstract: A multi-band high-frequency circuit for performing wireless communications among pluralities of communication systems having different communication frequencies, comprising a high-frequency switch circuit comprising switching elements for switching the connection of pluralities of multi-band antennas to transmitting circuits and receiving circuits; a first diplexer circuit disposed between the high-frequency switch circuit and transmitting circuits for branching a high-frequency signal into frequency bands of the communication systems; a second diplexer circuit disposed between the high-frequency switch circuit and receiving circuits for branching a high-frequency signal into frequency bands of the communication systems; the first and second diplexer circuits each comprising a lower-frequency filter circuit and a higher-frequency filter circuit, a bandpass filter circuit being used as the lower-frequency filter circuit in the second diplexer circuit, or disposed between the lower-frequency filter circuit in t

Abstract: A surface acoustic wave element 1 comprises a piezoelectric substrate 19, IDT electrodes 3, 4, 5 of an odd number not less than three formed along a propagation direction of surface acoustic waves that propagates on the piezoelectric substrate, wherein IDT electrodes 3, 5 of the odd number of IDT electrodes 3, 4, 5 disposed on both sides of an IDT electrode 4 that is located at the center are connected to first and second reference potential terminals 14, 15, respectively, and the first and second reference potential terminals 14 and 15 are formed asymmetrically with respect to a virtual central axis A that passes through the center of the IDT electrode 4 located at the center and provided in a direction perpendicular to the propagation direction.

Abstract: A surface acoustic wave filter (cascaded dual mode SAW filter) includes three IDT electrodes disposed adjacent to each other along the propagation direction of a surface wave on a piezoelectric substrate and two primary-tertiary longitudinally-coupled dual mode SAW filters cascaded and constructed by arranging grating reflectors on both sides of three IDT electrodes. At least a pair of electrode fingers are thinned out from the IDT electrodes disposed outside, and floating electrodes are then disposed.

Abstract: A transmission line having a slot line with a slot formed on a front surface electrode on a dielectric substrate, and two such slot lines are positioned with the front surface electrodes separated from one another with a gap therebetween. A slot resonator with one end open at the gap side is provided at the front edge side of each slot line, and these slot resonators are positioned so as to be capable of coupling to one another .A slot stub which is branched out from the gap side is provided on each front surface electrode. Thus, leakage of a high-frequency signal in the gap can be suppressed with the slot stub.