Abstract: A modular lift assembly includes a frame, at least one head block connected to the frame, a drum rotatably connected to the frame about an axis of rotation and having at least one winding section, and a drive mechanism operatively connected to the drum for rotating the drum. In various examples, the lift assembly includes at least one loft block internal or external relative to the frame. The loft block is configured to guide a cable from the at least one head block to a load. The lift assembly can further include a load brake positioned along the axis of drum rotation to reduce risks associated with a drive or motor failure.

Abstract: A band brake for rotating machinery and equipment, in particular, a band brake for hoists, winches, and similar load lifting equipment. The band brake includes a resilient flexible band disposed about a rotatable drum, a tension bar pivotally coupled to a frame, a positioner attached to the frame and coupled with the tension bar to move the band brake between an engaged position and a disengaged position. The positioner includes a linear actuator, an articulated link assembly, and a magnetic retention assembly.

Abstract: An elevating mechanism includes a bottom seat on which is provided with a first support body and a driving motor. An interior of the first support body is defined with an elevating region which is emplaced with a second support body and a gear set to drive the second support body to elevate. A top end of the second support body is provided with a holding element which is extended downward and exposes the first support body. Through a support piece, the holding element allows medicines to enter into a concentration detection device for measurement.

Abstract: A fence system including a first post attached in the ground and a second post attached in the ground. The fence system also includes a rail coupled to the first post and the second post with a female member attachment mechanism and a lip. The fence system also includes a slat including a male member attachment mechanism with a flap and a locking mechanism defining a step. The slat is coupled to the rail such that the male member attachment mechanism is coupled to the female member attachment mechanism and the step abuts the lip. If a force is applied to remove the male member attachment mechanism from the female member attachment mechanism, the lip exerts a force on the step resisting the force applied to remove the male member attachment mechanism.

Abstract: A hidden-fastener fence is disclosed, which features wavelike seizing surfaces on the opposite inner walls of horizontal tubes of the fence. And wavelike embedding verges are set up at both sides of horizontal plate of a fixing bar to fit in the seizing surfaces of the horizontal tube. Accordingly, the joining of the embedding verges at the both sides of the horizontal plate of the fixing bar and the seizing surfaces of the corresponding inner walls of the horizontal tube would prop the bottom opening of the horizontal tube outward, which considerably boosts the structural strength of the bottom opening of the horizontal tube, and the wavelike seizing surfaces on the inner walls of the horizontal tube further fortifies the rigidity of the horizontal tube.

Abstract: The present teachings provide a gate or fence that is reconfigurable and portable. The reconfigurable gate includes a first fence section, a section fence section and third fence section. The first fence section includes a plurality of first cross members. The second fence section includes a plurality of second cross members. The third fence section includes a plurality of third cross members. The first fence section and the second fence section are rotatably attached to the third fence section such that when the gate or fence is in a fully collapsed configuration, the plurality of first cross members and the plurality of second cross members are substantially interleaved with the plurality of third cross members.

Abstract: A memory cell structure, including a substrate having a via therein bound at first and second ends thereof by electrodes. The via is coated on side surfaces thereof with GST material defining a core that is hollow or at least partially filled with material, e.g., germanium or dielectric material. One or more of such memory cell structures may be integrated in a phase change memory device. The memory cell structure can be fabricated in a substrate containing a via closed at one end thereof with a bottom electrode, by conformally coating GST material on sidewall surface of the via and surface of the bottom electrode enclosing the via, to form an open core volume bounded by the GST material, optionally at least partially filling the open core volume with germanium or dielectric material, annealing the GST material film, and forming a top electrode at an upper portion of the via.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2).

Abstract: A resistance change element including: a lower electrode formed on at least one of a semiconductor and insulating substrate; a resistance change material layer formed on the lower electrode and including a transition metal oxide as a major component; and an upper electrode formed on the resistance change material layer. The resistance change material layer is formed of a nickel oxide containing nickel vacancy and having a higher oxygen concentration than a stoichiometric composition, and has a stacked structure with different composition ratios.

Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

Abstract: A nonvolatile memory device according to an embodiment of the present invention includes a first wire that extends in a first direction, a second wire that is formed at a height different from the first wire and extends in a second direction, and a nonvolatile memory cell that is arranged to be sandwiched between the first wire and the second wire at a position at which the first wire and the second wire intersect with each other. The nonvolatile memory cell includes a structure in which a nonvolatile storage element is sandwiched by semiconductor layers having different polarities.

Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.

Abstract: A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: The present invention generally relates to nanotechnology and sub-microelectronic devices that can be used in circuitry, and, in particular, to nanoscale wires and other nanostructures able to encode data. One aspect of the present invention is directed to a device comprising an electrical crossbar array comprising at least two crossed wires at a cross point. In some cases, at least one of the crossed wires is a nanoscale wire, and in certain instances, at least one of the crossed wires is a nanoscale wire comprising a core and at least one shell surrounding the core. For instance, the core may comprise a crystal (e.g., crystalline silicon) and the shell may be at least partially amorphous (e.g., amorphous silicon). In certain embodiments, the cross point may exhibit intrinsic current rectification, or other electrical behaviors, and the cross point can be used as a memory device.

Abstract: A method of patterning nanostructures comprising printing an ink comprising the nanostructures onto a solvent-extracting first surface such that a pattern of nanostructures is formed on the first surface.

Abstract: A method is for the synthesis of an array of metal nanowires (w) capable of supporting localized plasmon resonances. A metal film (M) deposited on a planar substrate (D) is irradiated with a defocused beam of noble gas ions (IB) under high vacuum, so that, with increasing ion doses a corrugation is produced on the metal film surface, formed by a mutually parallel nanoscale self-organized corrugations (r). Subsequently, the height of the self-organized corrugations peaks is increased relative to the valleys (t) interposed therebetween. Then the whole the metal film is eroded so as to expose the substrate at the valleys, and to mutually disconnect the self-organized corrugations, thereby generating the array of metal nanowires. Finally, the transversal cross-section of the nanowires is reduced in a controlled manner so as to adjust the localized plasmon resonances wavelength which can be associated thereto. The nanowires array constitutes an electrode of an improved photonic device.

Abstract: A light-emitting device includes a substrate, a first doped semiconductor layer situated above the substrate, a second doped semiconductor layer situated above the first doped layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped layer and a first passivation layer situated between the first electrode and the first doped layer in areas other than an ohmic-contact area. The first passivation layer substantially insulates the first electrode from edges of the first doped layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped layer and a second passivation layer which substantially covers the sidewalls of the first and second doped layers, the MQW active layer, and the horizontal surface of the second doped layer.

Abstract: Semiconductor emitting devices that offset stresses applied to a quantum well region and reduce internal fields due to spontaneous and piezoelectric polarizations are disclosed. In one embodiment, a semiconductor emitting device includes a quantum well region comprising an active layer that emits light and at least one barrier layer disposed adjacent the active layer, a means for impressing an electric field across the quantum well region to inject carriers into the quantum well region, and a means for impressing an offset electric field across the quantum well region to offset the polarization field formed in the quantum well region.

Abstract: Compound semiconductors capable of emitting light in the green spectrum are provided. The compound semiconductors may display improved quantum efficiencies when applied to various optical devices. Also, light emitting diodes and light emitting diode modules comprising the compound semiconductors are provided.

Abstract: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers, and an active layer disposed between the n-type and p-type nitride semiconductor layers and having a stack structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked. A net polarization of the quantum barrier layer is smaller than or equal to a net polarization of the quantum well layer. A nitride semiconductor light emitting device can be provided, which can realize high efficiency even at high currents by minimizing the net polarization mismatch between the quantum barrier layer and the quantum well layer. Also, a high-efficiency nitride semiconductor light emitting device can be achieved by reducing the degree of energy-level bending of the quantum well layer.

Abstract: Apparatuses capable of and techniques for detecting the visible light spectrum are provided.

Abstract: Apparatuses capable of and techniques for detecting long wavelength radiation are provided.

Abstract: A nitride semiconductor chip is provided that offers enhanced luminous efficacy and an increased yield as a result of an improved EL emission pattern and improved surface morphology (flatness). This nitride semiconductor laser chip (nitride semiconductor chip) includes a GaN substrate having a principal growth plane and individual nitride semiconductor layers formed on the principal growth plane of the GaN substrate. The principal growth plane is a plane having an off angle in the a-axis direction relative to the m plane, and the individual nitride semiconductor layers include a lower clad layer of AlGaN. This lower clad layer is formed in contact with the principal growth plane of the GaN substrate.

Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.

Abstract: A color unit is disclosed in which is included in an imaging device. The color unit includes; a first p-type electrode layer disposed on a light receiving side of the color unit, and including a light-absorptive organic material which selectively absorbs a wavelength other than a desired wavelength in a visible light band of the electromagnetic spectrum, a second p-type electrode layer disposed under the first p-type electrode layer and including a light-absorptive organic material which absorbs a desired wavelength and an n-type electrode layer disposed under the second p-type electrode layer and including an organic material, wherein photoelectric conversion is performed through a p-n junction between the second p-type electrode layer and the n-type electrode layer and light of the desired wavelength is converted into electrical current.

Abstract: [Problem] To provide an organic compound which shows an excellent electron-injecting/transporting performance, has a hole-blocking ability and shows a high stability as a film, that is, having excellent characteristics as a material for organic electroluminescent device having high efficiency and high durability; and to provide an organic EL device comprising the compound and having high efficiency and high durability. [Means for Solution] A substituted bipyridyl compound represented by the general formula (1); and an organic electroluminescent device comprising a pair of electrodes and at least one organic layer sandwiched between then, wherein the compound is used as the constitutive material of at least one organic layer.

Abstract: An organic electroluminescence device (1) includes: an anode (3); a cathode (4); and an organic thin-film layer (10) interposed between the anode (3) and the cathode (4). The organic thin-film layer (10) includes a phosphorescent-emitting layer (5) containing a host and a phosphorescent dopant. The host contains a first host and a second host. The first host includes a substituted or unsubstituted polycyclic fused aromatic skeleton, the skeleton having 10 to 30 ring-forming atoms not including an atom of a substituent.

Abstract: An organic semiconductor polymer, a transistor including an organic semiconductor polymer and methods of fabricating the same are provided, the organic semiconductor polymer including an aromatic or heteroaromatic main chain and at least one of a fluoro or a perfluoroalkyl at a polymer terminal end.

Abstract: A semiconductor device includes a conductive layer formed in the junction region and a boundary layer arranged to wrap a side and a bottom of the conductive layer.

Abstract: A material which can emit phosphorescence is disclosed. Further, a light-emitting element having good chromaticity is disclosed. An embodiment of the present invention is an organometallic complex including a structure as represented by the general formula (1): wherein R1 represents an alkyl group having 1 to 4 carbon atoms; each of R2 to R5 represents any one of hydrogen, a halogen element, an acyl group, an alkyl group, an alkoxyl group, an aryl group, a cyano group, and a heterocyclic group; Ar represents an aryl group or a heterocyclic group, preferably, an aryl group having an electron withdrawing group or a heterocyclic group having an electron withdrawing group; and M represents a Group 9 element or a Group 10 element. By virtue that the Ar has an electron withdrawing group, an organometallic complex which emits phosphorescence with higher emission intensity can be obtained.

Abstract: An excellent composition for a charge-transport film, which can be used to produce an organic electroluminescence device having excellent heat-resistant property, high hole injection/transport capacity and capable of functioning at a low voltage, is proposed. It comprises at least an ionic compound expressed by the following general formula (1) or the like and a charge-transporting compound, (R11-A1+-R12)n1Z1n1???(1) wherein in general formula (1): R11 represents an organic group bound to A1 via a carbon atom; R12 represents an arbitrary group; R11 and R12 may combine together to form a ring; A1 represents an element belonging to the third and subsequent periods and group 17 of the long form periodic table; Z1n1? represents a counter anion; and n1 represents an ionic valency of the counter anion.

Abstract: A method for manufacturing a self-aligned thin-film transistor (TFT) is described. Firstly, an oxide gate, a dielectric layer, and a photoresist layer are deposited on a first surface of a transparent substrate in sequence. Then, an ultraviolet light is irradiated on a second surface of the substrate opposite to the first surface to expose the photoresist layer, in which a gate manufactured by the oxide gate serves as a mask, and absorbs the ultraviolet light irradiated on the photoresist layer corresponding to the oxide gate. Then, the exposed photoresist layer is removed, and a transparent conductive layer is deposited on the unexposed photoresist layer and the dielectric layer. Then, a patterning process is executed on the transparent conductive layer to form a source and a drain, and an active layer is formed to cover the source, the drain, and the dielectric layer, so as to finish a self-aligned TFT structure.

Abstract: The present invention provides an oxide semiconductor material, a method for manufacturing such oxide semiconductor material, an electronic device and a field effect transistor. The oxide semiconductor material contains Zn, Sn, and O, does not contain In, and has an electron carrier concentration higher than 1×1015/cm3 and less than 1×1018/cm3. The electronic device comprises a semiconductor layer formed of the oxide semiconductor material, and an electrode provided on the semiconductor layer. The field effect transistor comprises a source electrode and a drain electrode which are arranged in separation from each other on the semiconductor layer; and a gate electrode placed at a position where the gate electrode can apply a bias potential to a region of the semiconductor layer positioned between the source electrode and the drain electrode.

Abstract: Provided is a thin-film transistor (TFT) display panel having improved electrical and reliability properties and a method of fabricating the TFT display panel. The TFT display panel includes gate wiring formed on a substrate; an oxide active layer pattern formed on the gate wiring; data wiring formed on the oxide active layer pattern to cross the gate wiring; a passivation layer formed on the oxide active layer pattern and the data wiring and made of nitrogen oxide; and a pixel electrode disposed on the passivation layer.

Abstract: A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same.

Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.

Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Abstract: In step S103, a gallium nitride semiconductor layer 13 is grown on an n-type GaN substrate 11. In step S104, a PL spectrum for the gallium nitride based semiconductor layer in a wavelength region including the yellow band of wavelength and the band edge wavelength of the gallium nitride based semiconductor is measured at room temperature. In step S106, a screened epitaxial substrate E1 is prepared through selection based on comparison of the photoluminescence spectrum intensity in the yellow band of wavelength and the band edge wavelength with a reference value. In step S107, an electrode 15 for an electron device is formed on the screened epitaxial substrate 13.

Abstract: A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Abstract: A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

Abstract: Embodiments provide a semiconductor light emitting device which comprises a light emitting structure comprising a plurality of compound semiconductor layers, an insulation layer on an outer surface of the light emitting structure, an ohmic layer under the light emitting structure and on an outer surface of the insulation layer, a first electrode layer on the light emitting structure, and a tunnel barrier layer between the first electrode layer and the ohmic layer.

Abstract: It is an object to provide a flexible light-emitting device with high reliability in a simple way. Further, it is an object to provide an electronic device or a lighting device each mounted with the light-emitting device. A light-emitting device with high reliability can be obtained with the use of a light-emitting device having the following structure: an element portion including a light-emitting element is interposed between a substrate having flexibility and a light-transmitting property with respect to visible light and a metal substrate; and insulating layers provided over and under the element portion are in contact with each other in the outer periphery of the element portion to seal the element portion. Further, by mounting an electronic device or a lighting device with a light-emitting device having such a structure, an electronic device or a lighting device with high reliability can be obtained.

Abstract: A semiconductor light-emitting device comprises a substrate, a first conductive type semiconductor layer positioned on the substrate, a light-emitting structure positioned on the first conductive type semiconductor layer, and a second conductive type semiconductor layer positioned on the light-emitting structure. The substrate includes an upper surface and a plurality of protrusions positioned on the upper surface. Each of the protrusions includes a top surface, a plurality of wall surfaces, and a plurality of inclined surfaces sandwiched between the top surface and the wall surfaces.

Abstract: Thin, flat solid state light source device and methods for manufacturing is described. LED chips and their circuit boards are mounted on a thermal conductive substrate. The LED chips are surrounded with a flat layer of reflecting material which may embed the circuit boards. The LED chips and the reflecting layer is then topped with a layer of diffusion material and a layer of cover material.

Abstract: LED packages and LED displays utilizing the LED packages are disclosed where the peak emission of the LED display can be tilted or shifted to customize its peak emission to the mounting height or location of the LED display. One embodiment of an LED display comprises a plurality of LED package where the peak emission from at least some of the LED packages is tilted off the package centerline. The LED packages are mounted within the display in such a way as to generate an image having a peak emission that is tilted off the perpendicular emission direction of the display.

Abstract: The present invention provides a light-emitting diode (LED) and a method for manufacturing said LED. The LED is characterized that, the silica gel as the interlayer is provided between the transparent organic material and the chip. The method for manufacturing is characterized that, a gel applying step for applying the silica gel and the solidifying step for solidifying the semi-finished product of LED applied with the silica gel are included prior to the material packaging step for packaging using the transparent organic material. The LED of this invention and the LED manufactured by the method of this invention have no light decay for the low-power, such as Ø5 mm or less LED, and little light decay for the high-power LED, and have the advantages of excellent weathering resistance and low production cost.