Abstract: An LED package comprises at least one LED that emits LED light in an LED emission profile. The LED package includes regions of scattering particles with the different regions scattering light primarily at a target wavelength or primarily within a target wavelength range. The location of the regions and scattering properties are based at least partially on the LED emission profile. The regions scatter their target wavelength of LED light to improve the uniformity of the LED emission profile so that the LED package emits a more uniform profile compared to the LED emission profile. By targeting particular wavelengths for scattering, the emission efficiency losses are reduced.

Abstract: An LED package structure includes a substrate unit, a light-emitting unit, a light-reflecting unit and a convex package unit. The substrate unit has a substrate body and a chip-placing area. The light-emitting unit has a plurality of LED chips electrically disposed on the chip-placing area. The light-reflecting unit has an annular reflecting resin body surroundingly formed on the substrate body by coating. The annular reflecting resin body surrounds the LED chips that are disposed on the chip-placing area to form a resin position limiting space above the chip-placing area, and the annular reflecting resin body has an inner surface that has been cleaned by plasma to form a clean surface. The convex package unit has a convex package resin body disposed on the substrate body in order to cover the LED chips. The position of the convex package resin body is limited in the resin position limiting space.

Abstract: A substrate bearing, on one main face, a composite electrode, which includes an electroconductive network which is a layer formed from strands made of an electroconductive material based on a metal and/or a metal oxide, and having a light transmission of at least 60% at 550 nm, the space between the strands of the network being filled by an electroconductive fill material. The composite electrode also includes an electroconductive coating, which may or may not be different from the fill material, covering the electroconductive network, and in electrical connection with the strands, having a thickness greater than or equal to 40 nm, of resistivity ?1 less than 105 ?·cm and greater than the resistivity of the network, the coating forming a smoothed outer surface of the electrode. The composite electrode additionally has a sheet resistance less than or equal to 10?/?.

Abstract: A method of preparing oxynitride phosphor represented by Formula 1: (M(1-x)Eux)aSibOcNd??Formula 1 wherein M is an alkaline earth metal; and 0<x<1, 1.8<a<2.2, 4.5<b<5.5, 0?c<8, 0<d?8, and 0<c+d?8, the method including: mixing an alkaline earth metal precursor compound, an europium precursor compound, an acid, an Si3N4 powder, and a chelate compound to form a gel-phase product; drying the gel-phase product, sintering the gel-phase product to form a first sintered powder; grinding the first sintered powder; mixing the first sintered powder with about 20 to about 200 parts by weight of carbon, based on 100 parts by weight of the first sintered powder, to obtain a mixture of the first sintered powder and the carbon; and sintering the mixture of the first sintered powder and the carbon to provide the oxynitride phosphor.

Abstract: A method of fabricating a light emitting device comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface, forming a plurality of light emitting stack layers on the first major surface, forming an etching protection layer on the plurality of light emitting stack layers, forming a plurality of discontinuous holes or continuous lines on the substrate by a laser beam with the depth of 10˜150 ?m, cleaving the substrate through the plurality of discontinuous holes or continuous lines, providing a adhesion layer on the second major surface of the substrate, and expanding the adhesion layer to form a plurality of separated light emitting device.

Abstract: A light emitting device includes: a substrate; an LED chip provided on a main surface of the substrate; and a printed resistor element connected in parallel with the LED chip, the printed resistor element being provided in at least one of regions (i) on the main surface of the substrate, (ii) on a back surface of the substrate, and (iii) inside the substrate. According to the arrangement, it is possible to provide: a light emitting device which can emit light having preferable luminance without a reduction in optical output by suppressing light shielding and light absorption of light emitted from the LED toward the outside; and a method for manufacturing the light emitting device.

Abstract: A light emitting module with improved optical functionality and reduced thermal resistance is described, which comprises a light emitting device (LED), a wavelength converting (WC) element and an inorganic optically-transmissive thermally-conductive (OTTC) element. The WC element is capable of absorbing light generated from the LED at a specific wavelength and re-emitting light having a different wavelength. The re-emitted light and any unabsorbed light exits through at least one surface of the module. The OTTC is in physical contact with the WC element and at least partially located in the optical path of the light. The OTTC comprises one or more layers of inorganic material having a thermal conductivity greater than that of the WC element. As such, a compact unitary integrated module is provided with excellent thermal characteristics, which may be further enhanced when the OTTC provides a thermal barrier for vertical heat propagation through the module but not lateral propagation.

Abstract: The present disclosure relates to a Ill-nitride semiconductor light emitting device, comprising: a substrate with a plurality of protrusions formed thereon, each of the plurality of protrusions having three acute portions and three obtuse portions; and a plurality of Ill-nitride semiconductor layers formed over the substrate and including an active layer for generating light by recombination of electrons and holes.

Abstract: An organic LED element having improved reliability in a long-term use, and having improved external extraction efficiency up to 80% of emitted light is provided. A substrate for an electronic device according to the present invention includes: a translucent substrate; a scattering layer including a glass and being provided on the translucent electrode; a coating layer provided on the scattering layer; and scattering materials that are present in the scattering layer and the coating layer and are not present on a surface of the coating layer, in which a surface of the coating layer has waviness in which a ratio Ra/R?a of waviness height Ra to waviness period R?a exceeds 1.0×10?4 and is 3.0×10?2 or less.

Abstract: A semiconductor light emitting device includes a substrate, a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a roughness layer on the second conductive semiconductor layer. The second conductive semiconductor layer includes a shape of multiple horns, and the roughness layer includes a shape of multiple horns. The second conductive semiconductor layer includes a roughness in which horn shapes and inverse-horn-shaped shapes are alternately formed, and the roughness has a height of about 0.5 ?m to about 1.2 ?m and a diameter of about 0.3 ?m to about 1.0 ?m.

Abstract: Disclosed are a light emitting diode, a method of manufacturing the same, a light emitting device and a method of manufacturing the same. The light emitting device includes a circuit board formed with a first conductive pattern and a second conductive pattern electrically isolated from the first conductive pattern; a light emitting diode electrically connected to the first and second conductive patterns on the circuit board; a first molding member surrounding the light emitting diode; and a second molding member on the first molding member.

Abstract: To provide a light emitting diode package of which the height of protrusion of a thermal via is decreased without decreasing the flexural strength of an insulating substrate. A light emitting diode package comprising a light emitting diode element mounted on a substrate, wherein the substrate is obtained by firing a glass ceramic composition containing a powder of glass containing, as represented by mole percentage, from 57 to 65% of SiO2, from 13 to 18% of B2O3, from 9 to 23% of CaO, from 3 to 8% of Al2O3 and from 0.5 to 6% of at least one of K2O and Na2O in total, and a ceramic filler.

Abstract: A method for producing a group III nitride semiconductor light-emitting device including: an intermediate layer formation step in which an intermediate layer containing group III nitride is formed on a substrate by sputtering, and a laminate semiconductor formation step in which an n-type semiconductor layer having a base layer, a light-emitting layer, and a p-type semiconductor layer are laminated on the intermediate layer in this order, wherein the method includes a pretreatment step in which the intermediate layer is treated using plasma between the intermediate layer formation step and the laminate semiconductor formation step, and a formation step for the base layer which is included in the laminate semiconductor formation step is a step for laminating the base layer by sputtering.

Abstract: A semiconductor light emitting device according to an embodiment includes a top layer having a top surface and a bottom surface, the top layer being an n electrode; an uneven pattern formed in the bottom surface of the n electrode; an n-type semiconductor layer formed under the n electrode, the n-type semiconductor layer having a top surface and a bottom surface; an uneven pattern formed in the top surface of the n-type semiconductor layer, the uneven pattern of the n-type semiconductor layer corresponding to the uneven pattern of the n electrode; an active layer formed under the n-type semiconductor layer; a p-type semiconductor layer formed under the active layer; and a p electrode formed under the p-type semiconductor layer.

Abstract: A unit cell for use in an imaging system may include an absorber layer of semiconductor material formed on a semiconductor substrate, at least one contact including semiconductor material formed on the semiconductor substrate and electrically coupled to the absorber layer, and a cap layer of semiconductor material formed on the semiconductor substrate and electrically coupled to and formed between the absorber layer and the at least one contact. The absorber layer may be configured to absorb incident photons such that the absorbed photons excite electrons in the absorber layer to generate a photocurrent. The at least one contact may be configured to conduct the photocurrent to one or more electrical components external to the unit cell. The cap layer may be configured to conduct the photocurrent between the absorber layer and the at least one contact.

Abstract: This invention provides a photo-FET, in which a FET part and photodiode part are stacked, and the FET part and photodiode part are optimized independently in design and operational bias conditions. The semiconductor layer serving as a photo-absorption layer (41) is formed on the cathode semiconductor layer (10) of a photodiode part (50). An electron barrier layer (40) with a wider bandgap semiconductor than a photo-absorption layer (41), which also serves as an anode layer of a photodiode part (50), is formed on a photo-absorption layer (41). The channel layer (15) which constitutes the channel regions of the FET part is formed with a narrower bandgap semiconductor than an electron barrier layer (40) on an electron barrier layer (40). The hole barrier layer (16) with a bandgap wider than the semiconductor which constitutes a channel layer (15) is formed on a channel layer (15). The source electrode (30) and drain electrode (32) which are separated each others, are formed on a hole barrier layer (16).

Abstract: A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

Abstract: By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding material may be nickel (Ni), the diffusion barrier may be titanium (Ti) or titanium nitride (TiN). Generally, the diffusion barrier may be any material which will inhibit, but not block, diffusion of the siliciding material into the silicon. In this manner, a non-conformal barrier deposition, in conjunction with a non-conformal silicide material deposition, after anneal, results in substantially conformal silicide formation.

Abstract: A semiconductor device according to the embodiment includes an element region provided with a transistor, a plurality of mixed crystal layers, a drain electrode and a source electrode, an element isolation layer and a dummy pattern. The mixed crystal layers are the layers made of a first atom composing the semiconductor substrate and a second atom having a lattice constant different from the lattice constant of the first atom and formed on both ends of a region, which becomes a channel of the transistor. The dummy pattern is a layer made of the same material as the mixed crystal layers and formed to extend on the surface of the semiconductor substrate and outside of the element region such that a major direction thereof is different from a <110> direction of the semiconductor.

Abstract: For a DC to DC converter circuit integrated on a packaged die, the relative positions of various die pads and power MOSFETs on the die for a small outline integrated circuit package are described.

Abstract: A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.

Abstract: The present invention relates to a device for detecting millimeter waves, having at least one field effect transistor with a source, a drain, a gate, a gate-source contact, a source-drain channel, and a gate-drain contact. Compared to a similar such device, the problem addressed by the present invention, among others, is that of providing a device which enables the provision of a field effect transistor for detecting the power and/or phase of electromagnetic radiation in the Thz frequency range. In order to create such a device, it is suggested according to the invention, that a device be provided which has an antenna structure wherein the field effect transistor is connected to the antenna structure in such a manner that an electromagnetic signal received by the antenna structure in the THz range is fed into the field effect transistor via the gate-source contact, and wherein the field effect transistor and the antenna structure are arranged together on a single substrate.

Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.

Abstract: The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capacitor formed on a first side of a source/drain region positioned between gate patterns of adjacent cell transistors; a plate layer connected to an upper portion of the capacitor, the plate layer being formed in a direction intersecting the gate pattern; and a bit line connected to a second side of the source/drain region of the cell transistor, the bit line being formed in the direction intersecting the gate pattern.

Abstract: An insulation structure is provided. The insulation structure includes a deep trench filled with silicon and disposed in a substrate, a first oxide layer serving as the insulation structure and disposed on the surface of the silicon in the deep trench, a first silicon layer disposed on the first oxide layer, a gate disposed on the first silicon layer and a shallow trench isolation adjacent to the deep trench.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.

Abstract: In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.

Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.

Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

Abstract: A semiconductor device includes a first diffusion region and a second diffusion region in an active region surrounded by an isolation insulation region, a recessed trench region formed between the first diffusion region and the second diffusion region, a gate insulation film formed on the trench region, a gate electrode formed on the gate insulation film to fill the trench region therewith, and a protection insulation film formed in an upper part of the region interposed between the gate insulation film and the isolation insulation region.

Abstract: A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

Abstract: An impact ionization MISFET includes: a gate insulating film which has one surface contacting the surface of a semiconductor substrate; a gate electrode that contacts the other surface of the gate insulating film; and a drain region, channel region, impact ionization region, and source region that are formed in one direction on the semiconductor substrate. The channel region is on the surface of the semiconductor substrate to which the gate insulating film is in contact, and a channel is generated when a voltage is applied to the gate electrode. When a voltage is applied between the drain region and the source region and when a channel is generated in the channel region, avalanche multiplication of carriers injected from the source region occurs in the impact ionization region. The flow path of the carriers between the channel and the source region occurs within the semiconductor substrate.

Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.

Abstract: An object of the present invention is to provide a polysiloxane compound that can be developed in an aqueous alkali solution and can yield a cured product or thin film having superior heat-resistant transparency and insulating properties, a curable composition thereof, and a thin film transistor provided with a passivation layer or gate insulator using the same, and the present invention relates to a polysiloxane compound having at least one photopolymerizable functional group in a molecule thereof, and having at least one member selected from the group consisting of an isocyanuric acid backbone structure, a phenolic hydroxyl group and a carboxyl group within the same molecule, to a curable composition containing the polysiloxane compound, and to a cured product thereof.

Abstract: A semiconductor device which includes: a semiconductor layer formed over an insulating layer over a semiconductor substrate; a gate electrode disposed over the semiconductor layer through a gate insulator; a sidewall insulator formed along the gate insulating film and a sidewall of the gate electrode; a source/drain layer including an alloy layer whose bottom surface is in contact with the insulating layer; and an impurity-doped layer which is segregated in a self-aligned manner in an interface between the alloy layer and the semiconductor layer and has a face for junction with a channel region formed along a crystal orientation plane of the semiconductor layer.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

Abstract: A semiconductor device includes a substrate of a first conductive type, a first doped region of a second conductive type, at least one second doped region of the first conductive type, a third doped region of the second conductive type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately.

Abstract: A sidewall spacer film or the like is removed without damaging a device structure section. Specifically disclosed is a method for manufacturing a semiconductor device, which comprises a step of forming a first thin film composed of GeCOH or GeCH on a substrate (21) to be processed, a step of removing a part of the first thin film and obtaining a remaining portion (30), and a processing step of performing a certain process on the substrate (21) through the space formed by removing the first thin film.

Abstract: A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.

Abstract: A pressure sensor having a second semiconductor layer wherein is formed diffused resistance interconnections, an insulating layer that is formed on top of the second semiconductor layer, and external conducting portions that are formed on top of the insulating layer, wherein contacts for connecting electrically between the external conducting portions and the diffused resistance interconnections are formed in the insulating layer, and wherein the external conducting portions are formed in ranges corresponding to the ranges wherein the diffused resistance interconnections are formed in the second semiconductor layer.

Abstract: A method for manufacturing a micromechanical component and the micromechanical component produced thereby. This component is preferably a diaphragm or a diaphragm layer which is independently produced for the purpose of subsequent assembly with other components.