Abstract: An integrated device includes a semiconductor body, in which an STI insulation structure is formed, which delimits laterally first active areas and at least one second active area, respectively, in a low-voltage region and in a power region of the semiconductor body. The integrated device moreover includes low-voltage CMOS components, accommodated in the first active areas, and a power component in the second active area. The power component has a source region, a body region, a drain-contact region, and at least one field-insulating region, set between the body region and the drain-contact region. The field-insulating region is provided entirely on the semiconductor body.

Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a source region (10) with a source portion (73) and a drain region (12). The source portion and drain region are of a second conductivity type opposite to the first conductivity type and are mutually connected through a channel region (28) in the substrate over which a gate electrode (14) extends. The drain region comprises a drain contact region (16) and a drain extension region (15) which extends from the channel region (28) towards the drain contact region. The drain contact region is electrically connected to a top metal layer (22) by a drain contact (20), and a poly-Si drain contact layer (80) is arranged as a first contact material in between the drain contact region and the drain contact in a contact opening (51) of a first dielectric layer (52) deposited on the surface of the drain region.

Abstract: Provided is a semiconductor device in which the first trench isolation regions is placed between a substrate potential-fixing P-type diffusion region of an ESD protection NMOS transistor and source and drain regions of the ESD protection NMOS transistor, and has a depth greater than a depth of the second trench isolation region that is placed between a substrate potential-fixing P-type diffusion region of an NMOS transistor for internal circuit and source and drain regions of the NMOS transistor for internal circuit.

Abstract: Provided is a semiconductor device including an ESD protection N-MOS transistor isolated from another element by a shallow trench structure, in which the ESD protection N-MOS transistor includes a drain region on which a thin insulating film is formed, and an electrode which receives a signal from an external connection terminal is formed on the thin insulating film.

Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract: A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.

Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

Abstract: A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.

Abstract: In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.

Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.

Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.

Abstract: An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract: Methods and apparatus are provided for fabricating a transistor. The transistor comprises a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and an oxygen-gettering conductive layer overlying the high-k dielectric layer. The oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive layer.

Abstract: A method for fabricating a semiconductor device includes forming a recess pattern by selectively etching a substrate; forming a gate dielectric layer filling the recess pattern on the substrate; forming a groove by selectively etching the gate dielectric layer; forming a polysilicon electrode filling the groove; forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and forming a gate pattern by etching the electrode metal layer and the gate dielectric layer. The recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery.

Abstract: An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.

Abstract: A method of forming a MEMS microphone forms circuitry and first MEMS microstructure on a first wafer in a first process, and second MEMS microstructure on a second wafer in a second process. The first process is thermally isolated from the second process. The method also layer transfers the second MEMS microstructure onto the first wafer. The first MEMS microstructure and second MEMS microstructure thus form a variable capacitor that communicates with the circuitry on the first wafer.

Abstract: An element array comprises a plurality of elements having a first electrode and a second electrode with a gap therebetween; the first electrode being separated for each of the elements by grooves, an insulating connection substrate being bonded to the first electrode, and a wiring being made from each of the respective first electrodes separated for each of the elements through the connection substrate to the side opposite to the first electrodes.

Abstract: An assembly and connection technology for a sensor system, including a sensor element having circuit elements integrated into the top side and a carrier for the sensor element, which is simple and robust and which does not require any further packaging measures for protecting the circuit elements and electrical terminals of the sensor elements after the isolation of the sensor elements. For this purpose, the carrier is provided with through contacts. In addition, the sensor element is installed in flip-chip technology on the carrier, so that the top side of the sensor element is at least regionally capped by the carrier and the circuit elements of the sensor element can be electrically contacted from the rear side of the carrier via the through contacts.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a variable magnetization and an easy-axis in a perpendicular direction to a film surface, a second magnetic layer with an invariable magnetization and an easy-axis in the perpendicular direction, and a first nonmagnetic layer between the first and second magnetic layers. The first magnetic layer comprises a ferromagnetic material including an alloy in which Co and Pd, or Co and Pt are alternately laminated on an atomically close-packed plane thereof. The first magnetic layer has C-axis directing the perpendicular direction. And a magnetization direction of the first magnetic layer is changed by a current flowing through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer.

Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.

Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Abstract: A semiconductor light detecting element includes: a semiconductor substrate; and a distributed Bragg reflector layer of a first conductivity type, an optical absorption layer, and a semiconductor layer of a second conductivity type, sequentially laminated on the semiconductor substrate. The distributed Bragg reflector layer includes first and second alternately laminated semiconductor layers with different band-gap wavelengths, sandwiching the wavelength of detected incident light. The sum of thicknesses a first and a second semiconductor layer is approximately one-half the wavelength of the incident light detected.

Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface at an opposite side thereof. The first surface has an active layer with a light-receiving part. The semiconductor device also includes an adhesive layer provided to surround the light-receiving part on the first surface of the semiconductor substrate; a light-transmissive protective member disposed above the light-receiving part of the semiconductor substrate with a predetermined gap and adhered via the adhesive layer; and plural external connection terminals arranged in a predetermined array on the second surface of the semiconductor substrate are included. Each center point of the external connection terminals forming two facing edges is positioned inside of an area of the adhesive layer projected on the second surface among the outermost external connection terminals.

Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.

Abstract: There is provided an amino acid generator comprising a protecting group for an amino group that is eliminated to generate an amino acid, and a coating film forming composition using the amino acid generator and a polysiloxane composition containing the amino acid generator. A coating film forming composition comprising: a component (A): an amino acid generator comprising a protecting group that is eliminated to generate an amino acid, which is a compound of Formula (1): D-A (1) where D is a protecting group for an amino group, and A is an organic group remaining after subtracting hydrogen atoms from an amino group of an amino acid; a component (B): a hydrolyzable silane, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a mixture thereof; and a component (C): a solvent.

Abstract: According to one embodiment, an infrared imaging device includes a substrate, an infrared absorption unit, a thermoelectric conversion unit, a support body, and an interconnection. The infrared absorption unit is provided on the substrate and apart from the substrate to absorb an infrared ray. The thermoelectric conversion unit is provided apart from the substrate and in contact with the infrared absorption unit between the infrared absorption unit and the substrate. The thermoelectric conversion unit converts a temperature change due to the infrared ray absorbed by the infrared absorption unit into an electrical signal. The support body supports the thermoelectric conversion unit on the substrate and apart from the substrate and transmits the electrical signal. The interconnection transmits the electrical signal in reading the electrical signal. The infrared absorption unit includes a protrusion provided on a rim of the infrared absorption unit to protrude toward the substrate.

Abstract: The present invention provides a detection element that can suppress leak current from an end face of a semiconductor layer. That is, of an n+ layer and a p+ layer respectively disposed between an i layer, in which an electric charge is generated as a result of being illuminated with light, and a pair of electrodes, an edge portion of a formed face of the p+ layer is formed further inward than that of the i layer.

Abstract: A light detecting apparatus is provided with a semiconductor substrate, a first electrode layer, and a second electrode layer. The semiconductor substrate has a first conductivity type first semiconductor region, and a second conductivity type second semiconductor region formed on the first semiconductor region and constituting a photodiode based on a pn junction formed between the first semiconductor region and the second semiconductor region. The first electrode layer is arranged above the second semiconductor region so as to be opposed to the second semiconductor region and is electrically connected to the second semiconductor region. The second electrode layer is arranged above the first electrode layer so as to be opposed to the first electrode layer and forms a capacitance component connected to the photodiode, between the first electrode layer and the second electrode layer.

Abstract: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.

Abstract: An improved inspection system using back-side illuminated linear sensing for propagating charge through a sensor is provided. Focusing optics may be used with a back side illuminated linear sensor to inspect specimens, the back side illuminated linear sensor operating to advance an accumulated charge from one side of each pixel to the other side. The design comprises controlling voltage profiles across pixel gates from one side to the other side in order to advance charge between to a charge accumulation region. Controlling voltage profiles comprises attaching a continuous polysilicon gate across each pixel within a back side illuminated linear sensor array. Polysilicon gates and voltages applied thereto enable efficient electron advancement using a controlled voltage profile.

Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.

Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.

Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

Abstract: Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.

Abstract: Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.

Abstract: One or more embodiments relate to a method for making a capacitor such as a trench capacitor. The method includes: providing a substrate; forming an opening within the substrate; forming a sidewall spacer over a sidewall surface of the opening; forming a first conductive layer within the opening after forming the sidewall spacer; removing the sidewall spacer; forming a dielectric layer over the first conductive layer within the opening; and forming a second conductive layer over the dielectric layer within the opening.

Abstract: To provide a redox capacitor that can be used at room temperature and a manufacturing method thereof. Amorphous semiconductor including hydrogen is used as an electrolyte of a redox capacitor. As a typical example of the amorphous semiconductor including hydrogen, an amorphous semiconductor including a semiconductor element such as amorphous silicon, amorphous silicon germanium, or amorphous germanium can be used. As another example of the amorphous semiconductor including hydrogen, oxide semiconductor including hydrogen can be used. As typical examples of the oxide semiconductor including hydrogen, an amorphous semiconductor including a single-component oxide semiconductor such as zinc oxide, titanium oxide, nickel oxide, vanadium oxide, and indium oxide can be given. As another example of oxide semiconductor including hydrogen, a multi-component oxide semiconductor such as InMO3(ZnO)m (m>0 and M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co) can be used.

Abstract: A first interlayer dielectric is formed over a substrate, and an electric conductor pillar is formed in the first interlayer dielectric. A damascene wiring part insulating film is formed over an upper surface of the first interlayer dielectric. The damascene wiring part insulating film above the electric conductor pillar is removed to form an opening part for capacitance, and an insulating film for capacitive element is formed over the upper surface of the first interlayer dielectric. The insulating film for capacitive element and the first interlayer dielectric above the electric conductor pillar are removed to form a trench for wiring. Metal bodies are embedded in the opening part for capacitance and the trench for wiring. The metal body in the opening part for capacitance is to be an upper electrode of the capacitive element, and the metal body in the trench for wiring is to be a logic wiring.

Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance whilst being efficient in utilisation of semiconductor real estate.