Abstract: A nanofiber composite including a nanofiber formed of a hydrophobic polymer, a nanowire formed of a conductive or semiconductive organic material that is oriented in the nanofiber in the longitudinal direction of the nanofiber, and an ionic active material.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: A method for forming a nanowire tunnel device includes forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, forming a gate structure around a channel region of the nanowire, implanting a first type of ions at a first oblique angle in a first portion of the nanowire and the first pad region, and implanting a second type of ions at a second oblique angle in a second portion of the nanowire and the second pad region.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device can include a recess formed in an active area of a semiconductor substrate, an insulating layer formed in the recess, a source electrode and a drain electrode spaced apart from the source electrode on the insulating layer, a carbon nanotube layer formed between the source and drain electrodes, an oxide layer pattern covering at least the carbon nanotube layer, and a gate electrode formed on the oxide layer pattern.

Abstract: Porphyrin compounds are provided. The compounds may further comprise a fused polycyclic aromatic hydrocarbon or a fused heterocyclic aromatic. Fused polycyclic aromatic hydrocarbon s and fused heterocyclic aromatics may extend and broaden absorption, and modify the solubility, crystallinity, and film-forming properties of the porphyrin compounds. Additionally, devices comprising porphyrin compounds are also provided. The porphyrin compounds may be used in a donor/acceptor configuration with compounds, such as C60.

Abstract: An organic light emitting diode display device and a method of manufacturing the same are disclosed. The organic light emitting diode display device includes a substrate having an emission section and anon-emission section, a semiconductor layer located on the substrate, a gate dielectric layer located over an entire front surface of the substrate, a gate electrode located in correspondence to the semiconductor layer, a dielectric layer located over the entire front surface of the substrate, source and drain electrodes and a first electrode located on the dielectric layer and electrically connected to the semiconductor layer, a pixel definition layer exposing a part of the first electrode, a spacer located on the pixel definition layer and located on the non-emission section of the substrate, an organic film layer located on the first electrode, and a second electrode located over the entire front surface of the substrate.

Abstract: A thin film deposition apparatus, a method of manufacturing an organic light-emitting display device by using the thin film deposition apparatus, and an organic light-emitting display device manufactured by using the method.

Abstract: An organic electronic device comprising: an anode; a hole injecting layer; a cathode; and organic semiconductive material disposed between the hole injecting layer and the cathode, wherein the cathode comprises an electron-injecting material having a higher electron-injection efficiency than BaO/Al, and wherein the hole injecting layer comprises a hole injecting material which has a lower workfunction than PEDOT:PSS (1:6).

Abstract: An OLED display is disclosed. The display includes: a substrate main body, and an organic light emitting diode (OLED) formed on above the substrate main body, where the OLED includes: a first electrode injecting holes, a second electrode injecting electrons, an emission layer formed between the first and second electrodes, a hole injection layer (HIL) and a hole transport layer (HTL) sequentially formed between the first electrode and the emission layer, and a semi-transparent layer formed between the first electrode and the emission layer in red and green pixels.

Abstract: The present invention discloses a high-molecule-based organic light-emitting diode (OLED) and a fabrication method thereof. The high-molecule-based OLED comprises a layer selected from a group consisting of an organic emissive layer, a first emission-auxiliary layer and a second emission-auxiliary layer. The organic emissive layer, first emission-auxiliary layer or second emission-auxiliary layer comprises a molecular material having a molecular weight of larger than approximately 730 g mol?1, and is formed by a solution-process.

Abstract: An organic electroluminescent element including at least an emission layer sandwiched between an anode and a cathode, wherein the emission layer comprises at least a compound represented by Formula (A),

Abstract: In one example embodiment, a molecular element is configured by bridging a gap between a source electrode and a drain electrode by a functional molecule. The functional molecule arises from covalent linkage of a side chain composed of a pendant molecule that has dielectric constant anisotropy and/or dipole moments and in which orientation change occurs due to an electric field to a main chain composed of a conjugated molecule in which structural change occurs due to the orientation change of the pendant molecule and an electrical characteristic changes. The molecular element is made to work as a diode, a transistor, or a memory by an electric field applied to the pendant molecule of the functional molecule by gate electrodes.

Abstract: The present invention relates to a novel compound, a method for manufacturing the same, and an organic electronic device using the same, and the novel compound according to the present invention may act as a hole injection, hole transport, electron injection and transport, or light emitting material in an organic light emitting device and an organic electronic device, and the device according to the present invention shows excellent properties in terms of efficiency, a driving voltage, and stability.

Abstract: Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.

Abstract: Disclosed is a sputtering target that can suppress the occurrence of anomalous discharge in the formation of an oxide semiconductor film by sputtering method and can continuously and stably form a film. Also disclosed is an oxide for a sputtering target that has a rare earth oxide C-type crystal structure and has a surface free from white spots (a poor appearance such as concaves and convexes formed on the surface of the sputtering target). Further disclosed is an oxide sintered compact that has a bixbyite structure and contains indium oxide, gallium oxide, and zinc oxide. The composition amounts (atomic %) of indium (In), gallium (Ga), and zinc (Zn) fall within a composition range satisfying the following formula: In/(In+Ga+Zn)<0.

Abstract: Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.

Abstract: A midwave infrared lead salt photodetector manufactured by a process comprising the step of employing molecular beam epitaxy (MBE) to grow a heterostructure photoconductive detector with a wide-gap surface layer that creates a surface channel for minority carriers.

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: A semiconductor wire grid may include a plurality of wires arranged separately on a substrate, formed of a semiconductor, and including a groove therebetween, wherein conductivity of the semiconductor wire grid varies according to an applied voltage such that a polarization rate of the semiconductor wire grid is controlled.

Abstract: A display substrate includes a first light blocking pattern formed on a base substrate, a first switching element, a second light blocking pattern formed on the base substrate, and a first sensing element. The first light blocking pattern is configured to block visible light and transmit infrared light. The first switching element includes a first semiconductor pattern, a first source electrode, a first drain electrode, and a first gate electrode. The second light blocking pattern is configured to block the visible light and transmit the infrared light. The first sensing element is configured to detect the infrared light, and includes a second semiconductor pattern, a second source electrode, a second drain electrode, and a second gate electrode.

Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.

Abstract: A pixel structure includes a substrate, a gate and a pixel electrode that are disposed on the substrate, a patterned dielectric layer and a patterned semiconductor layer disposed on the gate, a source and a drain disposed on two sides of the patterned semiconductor layer respectively, and a passivation layer disposed on the source, the drain and the semiconductor layer. The sidewall surfaces of the source and the drain are completely covered with the passivation layer, but a part of the pixel electrode is exposed by the passivation layer.

Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.

Abstract: An active matrix substrate of a display device of the present invention comprises a glass substrate, a plurality of connection terminals (41) formed on the surface of the glass substrate and arranged in parallel with one another at an equal interval, and an interlayer insulating film (38) covering the plurality of connection terminals. The edge of the interlayer insulating film is so formed that tips of the plurality of connection terminals are exposed. A notch (42) is formed along the edge of the interlayer insulating film between two adjacent connection terminals. The notch has a stepped portion (46) comprising the first face (43), which is the bottom face of the notch, the second face (44), which is at a higher level than the first face, and a sloped face (45), which continues from the first face to the second face.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: Example embodiments are directed to oxide thin film transistors and methods of manufacturing the oxide thin film transistors. The oxide thin film transistor includes an active region in a gate insulation layer and under a source and a drain in a bottom gate structure, thus improving electrical characteristics of the oxide thin film transistor.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.

Abstract: A light emitting device capable of performing signal electric current write-in operations at high speed and without dispersion in the characteristics of TFTs structuring pixels influencing the brightness of light emitting elements is provided. The gate length L of a transistor in which an electric current flows during write-in of a signal electric current is made shorter than the gate length L of a transistor in which electric current supplied to EL elements flows during light emission, and high speed write-in is thus performed by having a larger electric current flow than the electric current flowing in conventional EL elements. A converter and driver transistor (108) is used for signal write-in.

Abstract: In an organic light emitting diode (OLED) display and a manufacturing method thereof, the OLED display includes a substrate main body; an insulation layer pattern formed on the substrate main body, and including a first thickness layer and a second thickness layer thinner than the first thickness layer; a metal catalyst that is scattered on the first thickness layer of the insulation layer pattern; and a polycrystalline semiconductor layer formed on the insulation layer pattern, and divided into a first crystal area corresponding to the first thickness layer and to a portion of the second thickness layer adjacent to the first thickness layer and a second crystal area corresponding to the remaining part of the second thickness layer. The first crystal area of the polycrystalline semiconductor layer is crystallized through the metal catalyst, and the second crystal area of the polycrystalline semiconductor layer is solid phase crystallized.

Abstract: An organic light emitting diode display device and a method of manufacturing thereof, the device including a substrate, the substrate including a pixel part and a circuit part; a first semiconductor layer and a second semiconductor layer on the pixel part of the substrate; a gate insulating layer on an entire surface of the substrate; gate electrodes on the gate insulating layer, the gate electrodes corresponding to the first semiconductor layer and the second semiconductor layer, respectively; source/drain electrodes insulated from the gate electrodes, the source/drain electrodes being connected to the first and second semiconductor layers, respectively; a first electrode connected to the source/drain electrodes of the first semiconductor layer; an organic layer on the first electrode; a second layer on the organic layer; and a metal catalyst layer under the first semiconductor layer.

Abstract: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.

Abstract: Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form II-N post(s) followed by formation of the shell member(s).

Abstract: A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.

Abstract: A compound semiconductor device includes: an electron transit layer made of GaN; a channel layer made of AlGaN; a source electrode, a gate electrode and a drain electrode that are provided on the channel layer; a cap layer that is provided at least between the source electrode and the gate electrode and between the gate electrode and the drain electrode and is made of GaN; a recess portion that is provided in the cap layer between the gate electrode and the drain electrode; and a thick portion that is provided in the cap layer between the recess portion and the drain electrode and has a thickness larger than the recess portion.

Abstract: Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm?3.

Abstract: A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.

Abstract: An electronic device includes a substrate. The substrate includes a first pixel driving circuit, a first conductive member, and a second conductive member. The first and second conductive members are spaced apart from each other. The first conductive member is connected to the first pixel driving circuit. The second conductive member is part of a power transmission line. The electronic device further includes a well structure overlying the substrate and defining a pixel opening, a via, and a channel. The pixel opening is connected to the via through the channel. In addition, the electronic device includes a first electronic component. The electronic component includes a first electrode that contacts the first conductive member in the pixel opening, a second electrode that contacts the second conductive member in the via, and an organic layer lying between the first and second electrodes.

Abstract: An exemplary liquid crystal display device includes a data line, a pixel, a first gate line, a second gate line, an additional electrode and an additional gate line. The pixel includes a first sub-pixel and a second sub-pixel. The first gate line is electrically coupled to the first sub-pixel. The second gate line is electrically coupled to the second sub-pixel. The first sub-pixel is electrically coupled to the data line to receive a signal provided from the data line. The second sub-pixel is electrically coupled to the first sub-pixel through the additional electrode and to receive a signal provided from the data line through the first sub-pixel. The additional gate line is arranged crossing over the additional electrode and whereby a compensation capacitance is formed between the additional gate line and the additional electrode.

Abstract: In an electrophoretic display device comprising a plurality of pixels, each pixel having a cell area containing a plurality of charged pigment particles dispersed between two opposite electrodes, a semiconducting passivation layer is provided on one or both of the two opposite electrodes. The semiconducting passivation layer can be made of MOx/y, MSx/y, or MNx/y where M is a metal or semiconductor such as Al, Sn, Zn, Si, Ge, Ni, Ti or Cd; x is a positive integer; and y is independently a non-zero positive integer. The semiconducting passivation layer may have a doped Si, ZnOx/y, ZnSx/y, CdSx/y and TiOx/y or a III-V type semiconducting material. The semiconducting passivation layer can be doped with a dopant which can be an n-type doner or a p-type acceptor, the n-type doner is N, P, As or F; and the p-type acceptor is B, Al, Ga, In, Be, Mg or Ca.

Abstract: Side-mountable semiconductor light emitting device packages include an electrically insulating substrate having a front face and a back face and a side face extending therebetween. The side face is configured for mounting on an underlying surface. An electrically conductive contact is provided proximate an edge of the substrate on the back face of the substrate and/or on a recessed region on the side face of the substrate. The contact is positioned to be positioned proximate an electrical connection region of the underlying surface when the semiconductor light emitting device package is side mounted on the underlying surface. A conductive trace extends along the front face of the substrate and is electrically connected to the contact. A semiconductor light emitting device is mounted on the front face of the substrate and electrically connected to the conductive trace.

Abstract: Provided is a package of a light emitting diode. The package according to an embodiment includes a base layer, a light emitting diode chip on the base layer, a lead frame electrically connected to the light emitting diode chip, a reflective coating layer directly on the lead frame, and a molding material covering the light emitting diode chip in a predetermined shape.

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract: A method of making quasi-vertical light emitting devices includes growing semiconductor layers on a growth substrate and etching the semiconductor layers to produce device isolation trenches forming separable semiconductor devices and holes. Blind holes are drilled in the substrate at the location of each of the holes in the semiconductor layers. The drilling of the blind holes defines blind hole walls and a blind hole end in each of the blind holes. N-semiconductor metal is deposited in each of the blind holes. An n-electrode contact is formed in each of the blind holes by plating each of the blind holes with an n-electrode metal connected to the n-semiconductor metal. The substrate is thinned to expose the n-electrode metal as an n-electrode. Bonding metal is deposited to the n-electrode for packaging.

Abstract: A method is presented for reducing the light output capacity of light emitting components (C1, C2, C3), each with a different absorption band, of an OLED device (1). By irradiating at least a portion of each light emitting component (C1, C2, C3) with light (L) having a wavelength within at least one of the absorption bands, the light output capacity of the irradiated portion (P, P1, P2, P3) of each organic light emitting component having a light absorption band in which the wavelength of the light (L) is included is reduced. An OLED device (1) is also presented.

Abstract: The present invention provides a semiconductor optical element array including: a semiconductor substrate having a main surface in which a plurality of concave portions is formed; a mask pattern that is formed on the main surface of the semiconductor substrate and includes a plurality of opening portions provided immediately above the plurality of concave portions; a plurality of fine columnar crystals that is made of a group-III nitride semiconductor grown from the plurality of concave portions to the upper side of the mask pattern through the plurality of opening portions; an active layer that is grown on each of the plurality of fine columnar crystals; and a semiconductor layer covering each of the active layers.

Abstract: A device to emit light includes a light emitting diode (LED) die and a light guide coupled to the LED die. The light guide includes a first material having a first index of refraction with a plurality of apertures arranged in a grid. A second material having a second index of refraction that is larger than the first index of refraction fills the plurality of apertures. Each aperture extends from a first end adjacent the LED die to a larger second end. The first end may be a circle of approximately 1 to 2 ?m in diameter. The distance between the first and second ends may be from approximately 10 to 20 ?m. Each aperture may be in the form of a frustrated cone having an included angle between the sides from approximately 3 to 7 degrees. The light guide may be formed on a transparent substrate.

Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.

Abstract: Disclosed are a light emitting device chip, a light emitting device package, and a lighting system. The light emitting device chip includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between the first and second conductive semiconductor layers; a transmittive layer on the light emitting structure; and a luminescence material layer on the transmittive layer, wherein the luminescence material layer includes a pattern, which does not expose the transmittive layer, partially exposes the transmittive layer or partially exposes the transmittive layer and the light emitting structure.

Abstract: Optoelectronic components with a semiconductor chip, which is suitable for emitting primary electromagnetic radiation, a basic package body, which has a recess for receiving the semiconductor chip and electrical leads for the external electrical connection of the semiconductor chip, and a chip encapsulating element, which encloses the semiconductor chip in the recess. The basic package body is at least partly optically transmissive at least for part of the primary radiation and an optical axis of the semiconductor chip runs through the basic package body. The basic package body comprises a luminescence conversion material, which is suitable for converting at least part of the primary radiation into secondary radiation with wavelengths that are at least partly changed in comparison with the primary radiation.