Abstract: A method of and miniaturized apparatus adapted for in-situ measurement of degradation of automotive fluids and the like by micro-electron spin resonance (ESR) spectrometry, wherein the use of a modulated constant magnetic field in an RF resonating variable frequency microwave cavity resonator through which a fluid sample is passed, enables direct detection of molecular changes in such fluid sample resulting from fluid degradation during use.

Abstract: There is described embodiments of a coil and pad system for use with an MRI machine. The coil and pad system includes a plurality of coils sized to accommodate a plurality of patient ranges of various heights and body weights. There is also a plurality of pads designed to work in conjunction with the plurality of coils to accommodate patient ranges of various heights and body weights.

Abstract: There is described embodiments of a coil and pad system for use with an MRI machine. The coil and pad system includes a plurality of coils sized to accommodate a plurality of patient ranges of various heights and body weights. There is also a plurality of pads designed to work in conjunction with the plurality of coils to accommodate patient ranges of various heights and body weights.

Abstract: A disclosed fracture characterization method includes: collecting three-dimensional resistivity measurements of a volume surrounding an open borehole; analyzing the measurements to determine parameters describing fractures in the volume; and providing a report to a user based at least in part on said parameters. A fluid with a contrasting resistivity is employed to make the fractures detectable by a directional electromagnetic logging tool in the borehole. illustrative parameters include fracture direction, height, extent, length, and thickness. The resistivity measurements can be augmented using a borehole wall image logging tool. Also disclosed are fracturing methods that include: positioning a directional electromagnetic logging tool proximate to a formation; fracturing the formation; monitoring fracture progression with said tool; and halting the fracturing when measurements by said tool indicate that a predetermined set of criteria have been satisfied.

Abstract: A method and apparatus for steering a drilling assembly within a reservoir of an earth formation is disclosed. The drilling assembly is positioned within the reservoir between a conductive upper layer having a DC magnetic field and a conductive lower layer having a DC magnetic field. A sensor of the drilling assembly measures a magnetic field in the reservoir resulting from the DC magnetic field of the conductive upper layer and the DC magnetic field of the conductive lower layer. A processor uses the measured magnetic field to steer the drilling assembly within the reservoir.

Abstract: A method for estimating the capacity of a vehicle battery while in service. The method includes providing a previous battery state-of-charge, battery temperature and integrated battery current amp-hours, and determining that battery contactors have been closed after they have been opened and disconnected from a load. The method determines if the battery has been at rest for a long enough period of time while the contactors were open, where the battery rest time is based on battery temperature, and determines an initial battery voltage from a last time step when the battery contactors were closed prior to the contactors being open during the battery rest time. The method determines a present battery state-of-charge from the initial battery voltage and the battery temperature and calculates the battery capacity based on the battery integrated current amp-hours divided by the difference between the present battery state-of-charge and the previous battery state-of-charge.

Abstract: A battery system for vehicle comprises a battery unit that is constituted with a plurality of serially connected cell groups each include a plurality of serially connected battery cells, integrated circuits that are each disposed in correspondence to one of the cell groups of the battery unit and each measure terminal voltages at the battery cells in the corresponding cell group, and a signal transmission path through which one of the integrated circuits is connected to another one of the integrated circuits or to a circuit other than that of the integrated circuits.

Abstract: A test fixture for testing a plurality of longitudinal battery cells includes: a base plate; a plurality of holding structures for holding the battery cells, the holding structures being mounted on the base plate and configured to hold the battery cells with their longitudinal axes being perpendicular with respect to the base plate; and a plurality of contacts arranged on the base plate to electrically contact positive and negative terminals of each of the battery cells.

Abstract: A solar photovoltaic panel test platform includes a test section and a signal processing section. The test section has a frame, a light-emitting unit disposed on the frame, a first angle adjustment unit and a second angle adjustment unit arranged on the frame, an air-cooling unit mounted on the first angle adjustment unit for connecting with a first solar photovoltaic panel, and a water-cooling unit mounted on the second angle adjustment unit for connecting with a second solar photovoltaic panel. The signal processing section is connected to the first and second angle adjustment units, the light-emitting unit, the air-cooling unit, the water-cooling unit, and the first and second solar photovoltaic panels. The signal processing section serves to receive sensing signals and transmit control signals. The solar photovoltaic panel test platform can provide different illuminations, angles of incidence and heat dissipation modes to test the efficiency of the solar photovoltaic panels.

Abstract: In accordance with certain embodiments of the present disclosure, a cable fault detection device is described. The device includes a conformal monopole structure and a ground plane structure. The ground plane structure is configured to be generally parallel to the cable longitudinal axis.

Abstract: A method for detecting a capacitor loss is applicable to detecting a plurality of by-pass capacitors connected in parallel to each other. The detection method includes the following steps, an alternating current (AC) signal is input into the by-pass capacitors, in which the AC signal has a plurality of test frequencies; test voltages of the by-pass capacitors at each of the test frequencies are recorded, so as to form a test result table; it is determined whether the test result table is the same as a standard voltage table; and when a result of the determination is NO, a fail signal is output. By applying the detection method, whether a loss exists in the by-pass capacitors can be effectively identified, thereby solving the problem that small capacitors are undetectable when large capacitors are connected in parallel to the small capacitors.

Abstract: To reduce erroneous inspection caused by particular noise occurring when plate-shaped electrodes are used, the invention is related to a liquid-discharging device in which a discharge judgment for judging whether or not a liquid has been discharged from a nozzle is performed on the basis of a change in electric potential occurring in at least one of a first electrode and a second electrode when the liquid has been discharged from the nozzle. The discharge judgment is performed continuously a plurality of times for the nozzle that is an inspection target. Even if the liquid is judged to have been discharged in any of the plurality of discharge judgments, the liquid will be determined not to have been discharged from the nozzle that is an inspection target as long as a judgment that the liquid has not been discharged has been made in any of the plurality of discharge judgments.

Abstract: A sensing device includes an oscillator, a driver, a switch, a counter and a timer. The oscillator includes an input coupled to a reference capacitor. The driver alternately sources and sinks current in accordance with an oscillation signal outputted by the oscillator. The switch connects or disconnects the reference capacitor with a sensing capacitor. The counter counts value for the oscillation signal. The timer counts operation periods respectively when the switch connects the reference capacitor with the sensing capacitor and when the switch disconnects the reference capacitor with the sensing capacitor, and the counter counts values corresponding to conditions of the switch connecting and disconnecting the reference capacitor with the sensing capacitor during the operation periods, respectively.

Abstract: An electric security fence. An electric signal generator generates an initial electric signal. The generated initial electric signal is transmitted through a transmission line. The transmission line will generate a reflected electric signal when the transmission line is disturbed by the presence of a human or animal at a disturbance area. A receiver receives the reflected electric signal and forwards it to a signal processing unit. The signal processing unit calculates the location of the disturbance area after receiving the reflected electric signal. In one preferred embodiment, the signal processing unit calculates the location of the disturbance area by determining the amount of time required for the reflected signal to travel from the disturbance area.

Abstract: An electric security fence. An electric signal generator generates an initial electric signal. The generated initial electric signal is transmitted through a transmission line. The transmission line will generate a reflected electric signal when the transmission line is disturbed by the presence of a human or animal at a disturbance area. A receiver receives the reflected electric signal and forwards it to a signal processing unit. The signal processing unit calculates the location of the disturbance area after receiving the reflected electric signal. In one preferred embodiment, the signal processing unit calculates the location of the disturbance area by determining the amount of time required for the reflected signal to travel from the disturbance area.

Abstract: The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Abstract: Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Abstract: A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations.

Abstract: A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half.

Abstract: A probe includes: a single base portion; a plurality of beam portions whose rear end sides are supported by the base portion and whose front end sides protrude from the base portion; and a plurality of conductive patterns formed on surfaces of the beam portions. At least a part of the plurality of beam portions has a beam bent portion which is bent in a direction inclined to or substantially perpendicular to a protruding direction of the beam portions.

Abstract: A light source for injecting excess carriers into a semiconductor wafer, fully illuminating a surface of the wafer. According to the disclosed embodiments, the source includes at least one set of point sources which are spaced apart at regular intervals along the X and Y axes, such that the source emits a monochromatic beam of a size that is at least equal to that of the semiconductor wafer surface to be illuminated. Each of the point sources is sinusoidally modulated by a common electrical modulator, the distance between two point sources and the distance between the source and the semiconductor wafer surface to be illuminated being selected such that the monochromatic light beam uniformly illuminates the surface.

Abstract: An apparatus comprising a test circuit that is provided on a test substrate and tests the device under test; a sealing section that covers a region of the test substrate on which the test circuit is formed, and seals the test circuit to form a sealed space that is filled with a cooling agent; and a through-connector that passes through the sealing section and electrically connects the test circuit to an element provided outside the sealing section, such that the connection is not through the test substrate.

Abstract: A system for testing a magnetic sensor has a plurality of coils, wherein the coils are positioned along perpendicular planes. A magnetic field is generated along each of the perpendicular planes when a current is sent to each of the plurality of coils.

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device.

Abstract: A method of assembling a testing apparatus for a full-power converter assembly includes coupling an electric power supply apparatus to an electric power grid. The method also includes coupling a direct current (DC) generation apparatus to the electric power supply apparatus. The method further includes coupling an electric power grid simulation device to the DC generation apparatus. The method also includes coupling a full-power converter assembly test connection to the electric power grid simulation device.

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract: Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output.

Abstract: A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.

Abstract: A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor.

Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.

Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

Abstract: A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.

Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Abstract: A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.

Abstract: A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.

Abstract: A semiconductor device includes: a DLL circuit that generates an internal clock signal based on an external clock signal; a clock dividing circuit that generates two complementary internal clock signals having different phases based on the internal clock signal; and a multiplexer that outputs two internal data signals in synchronization with the two clock signals based on internal data signals, respectively. An internal power supply voltage supplied to the clock dividing circuit and an internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device. This prevents interaction among noises.

Abstract: Included are: a modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract: A delay circuit used in a schedule controller includes a voltage detection unit, a timer, and a first electronic switch. The voltage detection unit receives an input voltage and compares the input voltage with a predetermined voltage. The timer is controlled by the voltage detection unit to calculate duration of an interval time. The first electronic switch is switched on or off under the control of the timer. When the input voltage substantially equals or exceeds the predetermined voltage, the timer calculates duration of the interval time, the timer generates and transmits a switch signal to the first electronic switch when the timing is reached, and the first electronic switch is switched on by the switch signal and provides an output voltage.

Abstract: A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.

Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract: Some embodiments of the invention a circuit configured to apply a time domain processing sequence to a modulated input signal to estimate a mean value of the modulated input signal and to subtract the estimated mean value from the modulated input signal, thereby removing the DC offset from the input signal. In one particular embodiment, the time domain processing sequence is based on integration and differentiation of a demodulated output signal. In such an embodiment, a circuit is configured to integrate a demodulated signal to generate an integrated signal having a triangular shaped output signal. The circuit then measures the slopes of the integrated signal, by differentiation of the triangular shaped integrated signal, and generates an appropriate DC offset correction signal based upon the measured slopes. The DC offset correction signal may be added on top of the actual input signal to cancel the unwanted DC offset component.

Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.