Abstract: The instant disclosure relates to a manufacturing method of memory structure for dynamic random-access memory (DRAM). The method includes the steps of: (a) providing a substrate having a plurality of parallel trenches formed on a planar surface thereof each defining a buried gate, where a first insulating layer is formed on the planar surface of the substrate; (b) forming a gate oxide layer on the surface of each trench that defines the buried gate; (c) disposing a metal filler on the gate oxide layer to fill each of the trenches; (d) removing the metal filler in the upper region of each trench to selectively expose the gate oxide layer; (e) implanting ions at an oblique angle toward the exposed portions of the gate oxide layer in each trench to respectively form a drain electrode and a source electrode in the substrate abreast the gate oxide layer.

Abstract: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove.

Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.

Abstract: A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer.

Abstract: A method of forming a semiconductor device includes the following processes. A dummy insulating film is formed over a semiconductor substrate by using a source material that is free of carbon as an essential component. A hole that penetrates the dummy insulating film is formed. A conductive film is formed, which covers at least a side wall of the hole of the dummy insulating film. The dummy insulating film is removed to expose an outer surface of the conductive film.

Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Abstract: A gallium nitride (GaN) bonded substrate and a method of manufacturing a GaN bonded substrate in which a polycrystalline nitride-based substrate is used. The method includes loading a single crystalline GaN substrate and a polycrystalline nitride substrate into a bonder; raising the temperature in the bonder; bonding the single crystalline GaN substrate and the polycrystalline nitride substrate together by pressing the single crystalline GaN substrate and the polycrystalline nitride substrate against each other after the step of raising the temperature; and cooling the resultant bonded substrate.

Abstract: A method of cleaving a substrate and a method of manufacturing a bonded substrate using the same, in which warping in a cleaved substrate is reduced. The method includes the following steps of: forming an ion implantation layer by implanting ions into a substrate; annealing the substrate in which the ion implantation layer is formed; implanting ions again into the ion implantation layer of the substrate; and cleaving the substrate along the ion implantation layer by heating the substrate into which ions are implanted.

Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.

Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Abstract: A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies.

Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

Abstract: The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.

Abstract: The invention relates to a multilayer body arrangement, which comprises at least two multilayer bodies each having at least one surface to be processed as well as at least one device for positioning the multilayer bodies, wherein the device is configured such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. It further relates to a system for processing multilayer bodies with such a multilayer body arrangement, as well as a method for processing multilayer bodies, wherein the multilayer bodies are disposed such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs.

Abstract: A method of making a three-dimensional structure in semiconductor material includes providing a substrate (20) is provided having at least a surface including semiconductor material. Selected areas of the surface of the substrate are exposed to a focussed ion beam whereby the ions are implanted in the semiconductor material in the selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focussed ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focussed ion beam is etched away so as to provide a three-dimensional structure on the substrate (20).

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

Abstract: A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material.

Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.

Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.

Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Abstract: Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer.

Abstract: The present invention relates to a polishing slurry for performing chemical mechanical polishing on a surface to be polished including a surface made of silicon oxide and a surface made of metal, characterized in that it includes cerium oxide particles, a complexing agent, and water.

Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

Abstract: A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask.

Abstract: A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.

Abstract: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.

Abstract: Provided is a plasma etching method increasing the selectivity of a silicon nitride film in relation to the silicon oxide film or silicon functioning as a base. In a plasma etching method setting a pressure in a processing container as a predetermined level by exhausting a processing gas while supplying the processing gas into the processing container, generating plasma by supplying external energy to the processing container, and setting a bias applied to a holding stage holding a substrate in the processing container as predetermined value to selectively etch the silicon nitride film with respect to a silicon and/or silicon oxide film, the processing gas includes a plasma excitation gas, a CHxFy gas, and at least one oxidizing gas selected from the group consisting of O2, CO2, CO, and a flow rate of the oxidizing gas with respect to the CHxFy gas is set to be 4/9 or greater.

Abstract: A method to remove excess material during the manufacturing of semiconductor devices includes providing a semiconductor wafer comprising silicon nitride deposited thereon and applying a chemical solution to the semiconductor wafer, wherein the chemical solution comprises a combination of sulfuric acid and deionized water.

Abstract: A gas panel according to various aspects of the present invention is configured to deliver a constant flow rate of gases to a reaction chamber during a deposition process step. In one embodiment, the gas panel comprises a deposition sub-panel having a deposition injection line, a deposition vent line, and at least one deposition process gas line. The deposition injection line supplies a mass flow rate of a carrier gas to a reactor chamber. Each deposition process gas line may include a pair of switching valves that are configured to selectively direct a deposition process gas to the reactor chamber or a vent line. The deposition vent line also includes a switching valve configured to selectively direct a second mass flow rate of the carrier gas that is equal to the sum of the mass flow rate for all of the deposition process gases to the reactor chamber or a vent line.

Abstract: A method is developed to crystallize amorphous silicon (a-Si) thin films, in cold environment, by combining microwave-absorbing materials (MAM) and microwave irradiation. The MAM is set on top or around of the a-Si thin film. MAM composes of dielectric, magnetic, semiconductor, ferroelectric and carbonaceous material oxides, carbides, nitrides and borides, which will absorb and concentrate electric or magnetic field of the microwave. The microwave frequency is selected from 1 to 50 GHz, at a power density not less than 5 W/cm2. Temperature rise of the MAM is monitored and controlled by an optical pyrometer to be less than 600° C., and better be within 400-500° C. The application of MAM at patterned local areas leads to localized heating and crystallization of a-Si film right at the patterns to facilitate manufacture of semiconductor devices.

Abstract: A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film.

Abstract: The present invention generally relates to methods for thermally processing substrates. In one embodiment, a substrate having an amorphous thin film thereon is subjected to a first pulse of electromagnetic energy having a first fluence insufficient to complete thermal processing. After a predetermined amount of time, the substrate is then subjected to a second pulse of electromagnetic energy having a second fluence greater than the first fluence. The second fluence is generally sufficient to complete the thermal processing. Exposing the substrate to the lower fluence first pulse before the second pulse reduces damage to a thin film disposed on the substrate. In another embodiment, a substrate is exposed to a plurality of electromagnetic energy pulses. The plurality of electromagnetic energy pulses are spaced at increasing intervals to reduce the rate of recrystallization of a film on the substrate, thus increasing the size of the crystals formed during the recrystallization.

Abstract: The present invention provides a connector including a substrate, at least a conductive via disposed inside the substrate, a pad disposed on one surface of the substrate and electrically connected to the conductive via, a resilient flange disposed on the pad, and an anisotropic conductive adhesive interposed between the pad and the resilient flange to electrically connect the pad with the resilient flange.

Abstract: A bus bar edge structure of an electric junction box having a junction block main body, a bus bar-receiving gap arranged on the junction block main body, and a space communicating with the bus bar-receiving gap and arranged in a thickness direction of the bus bar includes a projection piece projecting from an edge of the bus bar at an opening side of the space in the thickness direction of the bus bar. An electric wire led from the junction block main body is guided to the projection piece so as to prevent interference with the edge of the bus bar. The projection piece functions as a press-operating portion configured to insert the bus bar into the bus bar-receiving gap. The projection piece is positioned in an opening of a longitudinal groove arranged in the space so as to prevent the electric wire from entering into the opening.

Abstract: A connector assembly includes an insertion member that includes a plurality of contact pads, and a housing that defines an opening at a first end configured to receive the insertion member. The upper inside surface and lower inside surface of the housing define a plurality of slots into which are placed electrical contacts. Each electrical contact includes a cross-member, a first and a second extension member, a resilient member, and a mating extension. The first and second extension members extend from respective ends of the cross-member and are positioned within respective slots of the housing. The resilient member extends from the cross member from a position between the first and the second extension members. A mating extension extends from the other side of the cross-member and through an opening defined in the rear wall of the housing. The resilient member is configured to make electrical contact with a contact pad of the insertion member.

Abstract: A connector assembly includes an insertion member that includes a plurality of contact pads, and a housing that defines an opening at a first end configured to receive the insertion member. The upper inside surface and the lower inside surface of the housing define a group of slots. Electrical contacts are positioned adjacent to one another in the slots of the housing. Each electrical contact includes a cross-member, and a first and a second extension member that extend from respective ends of the cross member. At least one of the first and second extensions is configured as a resilient member configured to make electrical contact with a contact pad of the insertion member. A mating extension extends from the cross-member and through an opening defined in the rear wall of the housing.

Abstract: A locking device is provided for an electrical socket. The locking device includes a device body having a projecting member projecting from the device body, wherein the projecting member is adapted for engagement with an aperture provided in an electrical socket. The projecting member has first and second positions. In a first position the projecting member is adapted for engagement with the aperture and the locking device can be connected and disconnected from the socket. In a second position, the projecting member cannot disengage from the aperture and the projecting member is lockable in the second position. The electrical socket may be a power cable receiver on an electrical appliance, or a power supply socket.

Abstract: A blockout device for a USB port is disclosed. The blockout device prevents contamination, damage or misuse of the USB port when not in use. The blockout device includes a locking member, a body member and a shell. The locking member has a bottom and a top. The bottom of the locking member includes a plurality of teeth for engaging the USB port. The body member has a top, a bottom and sides defining a channel therein. The locking member is positioned within the channel of the body. The shell has a cavity that receives the locking member and the body member. The locking member and the body member are positioned within the cavity of the shell when the blockout device is installed in the USB port.

Abstract: A socket protection device includes a fixing member, a cover, a limiting member, and an operation member. The fixing member is secured to a circuit board. The fixing member includes a pair of first connecting blocks. The cover includes a second connecting block, a first latching portion, and a second latching portion. The limiting member is secured to the circuit board. The operation member includes a shaft and an operation rod secured to the shaft. The shaft rotatably connects the cover to the fixing member via the first and second connecting blocks. When the operation rod is pressed to drive the shaft to rotate, the cover is rotated toward the socket. When the cover covers the socket, the first latching portion latches the limiting member, and the second latching portion latches the operation rod.

Abstract: A protecting plug for an audio jack includes a plug member and a decoration member. The plug member has a plug portion matching with an audio jack, a coupling portion, and a flange portion provided between the coupling portion and the plug portion. The decoration member includes a model portion, a coupling hole formed on the model portion, and a decoration connecting portion formed at a boundary surface of the coupling hole. By coupling the coupling portion to the coupling hole and making a receiving surface of the flange portion hold and/or connect with the decoration connecting portion, the plug member is assembled with the decoration member.

Abstract: The invention relates to a plug element (2, 2?) of a plug connector (1) for a sealed electrical plug-and-socket connection extending through a hole (4) in a wall (5), having a protective housing (9, 9?), which comprises an inner chamber (46), which at least in places forms a mating plug receptacle (45) for a mating plug element (3) complementary to the plug element (2, 2?), having a locking device (11, 11?), which is actuatable from outside the protective housing (9) and may be moved from an unlocked position (T) into a locked position (R), the locking device (11, 11?) extending at least in the locked position (R) into the inner chamber (46) and overlapping the mating plug receptacle (45) at least in places, and having at least one sealing element (18, 18?) resting against the protective housing (9, 9?) at least in a final plugged-together position of the plug connector (1), by means of which sealing element the mating plug receptacle 45) may be sealed relative to the external environment of the plug connecto

Abstract: A clip for connecting a conductor to a circuit interrupter in an electrical device is generally U-shaped and self-locking. The clip has a generally arcuate body and two generally linear legs. The legs extend vertically from the body. The legs have beveled edges that together with the generally arcuate body of the clip and a flat portion of the clip, allow an interlock to be formed between the clip and the conductor when the clip is in close contact with the conductor.

Abstract: A locking mechanism for a connector (100) facilitates the interconnect between the connector and an electronic device (200). The connector (100) is formed of a plug (102), a locking sleeve (104) and an o-ring (112). The locking sleeve has a locking pattern (108) that, upon rotation of the locking sleeve, engages and disengages lock between the plug and a socket within the electronic device. Friction from the o-ring (112) on the locking sleeve (104) prevents disengagement of the connector from the electronic device while providing a seal.

Abstract: A cable includes at least one conductor to transmit electrical signals and a shield layer positioned about the at least one conductor. The shield layer shields an environment external to the cable from electromagnetic radiation generated by the electrical signals. The cable also includes a first retention sleeve positioned about the shield layer and a second retention sleeve coupled with the first retention sleeve and to the shield layer.

Abstract: An electronic device includes a housing, a circuit board, a display having a plug, a jack defined in the circuit board, a locking plate releasably fixed to the housing. The jack is electrically connected to the plug so the display is electrically connected to the circuit board. After a plug is inserted into the jack, the locking plate is fixed to the housing to impact the plug, thereby preventing the plug from disconnecting from the jack.

Abstract: An outer sleeve of a coaxial cable connector comprising a tubular body operably attached to a coupling member, a compression portion frangibly connected to the tubular body, wherein the compression portion is configured to break away from the tubular body and displace towards the first end of the tubular body within the tubular body upon an axial compressive force is provided. Moreover, a post configured to receive a prepared end of a coaxial cable, a coupling member, axially rotatable with respect to the post, an outer sleeve engageable with the coupling member, the outer sleeve having a first end and a second end, wherein rotation of the outer sleeve rotates the coupling member, and a compression portion structurally integral with the outer sleeve, wherein the compression portion is configured to break apart from the outer sleeve when axially compressed is further provided. Furthermore, associated methods are also provided.

Abstract: In at least one embodiment, there is an electrical device comprising a functional module comprising a housing having a front face and a back face, and at least three arcuate blades extending out from the housing. At least one of the at least three arcuate blades has a locking section. The functional module can be used in a wiring system comprising at least one wiring module. The wiring module can include a housing having a front face and a back face and at least one opening for receiving at least one of the at least three arcuate blades. The disclosure can also include a wiring module which can be used separately from the functional module wherein the wiring module includes a housing having at least one movable arm. Inside the wiring module is a plurality of contacts disposed in the housing, wherein these contacts are configured to couple to electrical wiring.