Abstract: A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.

Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.

Abstract: A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

Abstract: A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.

Abstract: The present invention discloses a metal-gate/high-?/Ge MOSFET with laser annealing and a fabrication method thereof. The fabrication method comprises the following steps: forming a substrate; implanting a source area and a drain area on the substrate; activating the source area and the drain area by first laser light; depositing gate dielectric material on the substrate; annealing high-? dielectric material by second laser light; and forming a metal gate on the high-? dielectric material.

Abstract: An N-type MIS transistor includes an active region surrounded by an element isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the element isolation region and having a high-k insulating film, and a gate electrode formed on the gate insulating film. An N-type impurity region is formed at least in a portion located below the gate insulating film out of a portion of the active region which contacts the element isolation region.

Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion (20) and a second metal portion (21); a passivation stack (24, 26, 28) covering the metallization stack; a gas sensor including a sensing material portion (32, 74) on the passivation stack; a first conductive portion (38) extending through the passivation stack connecting a first region of the sensing material portion to the first metal portion; and a second conductive portion (40) extending through the passivation stack connecting a second region of the sensing material portion to the second metal portion. A method of manufacturing such an IC is also disclosed.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion (20) and a second metal portion (21); a passivation stack (24, 26, 28) covering the metallization stack; a gas sensor including a sensing material portion (32, 74) on the passivation stack; a first conductive portion (38) extending through the passivation stack connecting a first region of the sensing material portion to the first metal portion; and a second conductive portion (40) extending through the passivation stack connecting a second region of the sensing material portion to the second metal portion. A method of manufacturing such an IC is also disclosed.

Abstract: In one embodiment, a method of forming a MEMS device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a silicon based working portion on the sacrificial layer, releasing the silicon based working portion from the sacrificial layer such that the working portion includes at least one exposed outer surface, forming a first layer of silicide forming metal on the at least one exposed outer surface of the silicon based working portion, and forming a first silicide layer with the first layer of silicide forming metal.

Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base coupled to the lid and having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. At least one of the lid or the base can have at least one port hole. The one or more first electrically conductive leads can be configured to couple to the printed circuit board. Other embodiments are disclosed.

Abstract: A ferroelectric device comprises: a silicon substrate (a first substrate); a lower electrode (a first electrode) formed on one surface side of first substrate; a ferroelectric film formed on a surface of lower electrode opposite to first substrate side; and an upper electrode (a second electrode) formed on a surface of ferroelectric film opposite to lower electrode side. The ferroelectric film is formed of a ferroelectric material with a lattice constant difference from silicon. The ferroelectric device further comprises a shock absorbing layer formed of a material with better lattice matching with ferroelectric film than silicon and provided directly below the lower electrode. The first substrate is provided with a cavity that exposes a surface of shock absorbing layer opposite to lower electrode side.

Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

Abstract: A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form a MTJ stack, and forming a first dielectric cap layer over a top surface and on a sidewall of the MTJ stack. The step of patterning and the step of forming the first dielectric cap layer are in-situ formed in a same vacuum environment. A second dielectric cap layer is formed over and contacting the first dielectric cap layer.

Abstract: A Hall effect element includes a Hall plate having geometric features selected to result in a highest ratio of a sensitivity divided by a plate resistance. The resulting shape is a so-called “wide-cross” shape.

Abstract: A magnetic memory device includes a first fixing layer, a first tunnel barrier coupled to the first fixing layer, a free layer coupled to the first tunnel barrier and having a stacked structure including a first ferromagnetic layer, an oxide tunnel spacer, and a second ferromagnetic layer, a second tunnel barrier coupled to the free layer, and a second fixing layer coupled to the second tunnel barrier.

Abstract: A vertical magnetic memory device includes a pinned layer including a plurality of first ferromagnetic layers that are alternately stacked with at least one first spacer, wherein the pinned layer is configured to have a vertical magnetization, a free layer including a plurality of second ferromagnetic layers that are alternately stacked with at least one second spacer, and a tunnel barrier coupled between the pinned layer and the free layer.

Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

Abstract: A graphene structure includes a conductive layer and a protective layer. The conductive layer is formed of graphene doped with a dopant, and the protective layer is laminated on the conductive layer and formed of a material having a higher oxidation-reduction potential than water.

Abstract: A solid-state imaging apparatus including: a sensor substrate that has a plurality of pixels configured to receive incident light, the plurality of pixels being arranged on an upper surface of a semiconductor substrate; a transparent substrate that has a lower surface facing an upper surface of the sensor substrate and is configured to transmit the incident light therethrough; and a diffraction grating that is provided at any position between an upper surface of the transparent substrate and the upper surface of the sensor substrate and is configured to transmit the incident light therethrough, in which the diffraction grating is formed so as to diffract reflected diffraction light caused by that the incident light is incident on a pixel area in which the plurality of pixels are arranged on the upper surface of the semiconductor substrate and is diffracted.

Abstract: According to one embodiment, a solid state imaging device includes a substrate, and a plurality of interference filters. The substrate includes a plurality of photoelectric conversion units. The plurality of interference filters is provided individually for the plurality of photoelectric conversion units. The plurality of interference filters includes a plurality of layers with different refractive indices stacked. The plurality of interference filters is configured to selectively transmit light in a prescribed wavelength range. A space is provided between adjacent ones of the interference filters.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Abstract: This invention provides a solid-state image sensing apparatus in which a sensor portion that performs photo-electric conversion and plural layers of wiring lines including a signal line for the sensor portion are formed on a semiconductor substrate; which includes an effective pixel portion configured such that light enters the sensor portion, and an optical black portion shielded so that the light does not enter the sensor portion; and which has a light-receiving surface on the back surface side of the semiconductor substrate. The optical black portion includes the sensor portion, a first light-shielding film formed closer to the back surface side of the semiconductor substrate than the sensor portion, and a second light-shielding film formed closer to the front surface side of the semiconductor substrate than the sensor portion.

Abstract: An image sensor may include a semiconductor substrate, a plurality of light receiving devices formed within the semiconductor substrate, and a plurality of device isolation films for isolating the light receiving devices from each other. When an arrangement direction of a pixel array may be formed by arranging the light receiving devices is a horizontal direction, the pixel array may be formed by alternately arranging a first type light receiving device and a second type light receiving device having different horizontal lengths.

Abstract: There is provided a solid-state image pickup element including a pixel array part in which a plurality of pixels are arranged on a silicon substrate in arrays, and a drive part driving the pixel. The pixel includes a photoelectric conversion part formed near a second face of the silicon substrate opposite to a first face on which a wiring layer is laminated, for generating a charge corresponding to incident light, an overflow part formed in contact with the second face and fixed to a predetermined voltage, and a potential barrier part formed to be connected with the photoelectric conversion part and the .overflow part, for serving as a barrier against a charge overflowed from the photoelectric conversion part on the overflow part.

Abstract: An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.

Abstract: An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.

Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.

Abstract: A group III nitride composite substrate includes a support substrate, an oxide film formed on the support substrate, and a group III nitride layer formed on the oxide film. The oxide film may be a film selected from the group consisting of a TiO2 film and a SrTiO3 film, and an impurity may be added to the oxide film. Accordingly, the group III nitride composite substrate having a high bonding strength between the support substrate and the group III nitride layer is provided.

Abstract: Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates.

Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Abstract: The present invention relates to an epoxy resin composition for an optical semiconductor device, including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a silane coupling agent, in which a total content of the ingredient (C) and the ingredient (D) is from 69 to 94% by weight of the whole of the epoxy resin composition, and the ingredient (E) is contained in an amount satisfying the specific conditions.

Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.

Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.

Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.

Abstract: The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Abstract: A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Abstract: A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.

Abstract: A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively.