Abstract: A vertically folded probe is provided that can provide improved scrub performance in cases where the probe height is limited. More specifically, such a probe includes a base and a tip, and an arm extending from the base to the tip as a single continuous member. The probe arm is vertically folded, such that it includes three or more vertical arm portions. The vertical arm portions have substantial vertical overlap, and are laterally displaced from each other. When such a probe is vertically brought down onto a device under test, the probe deforms. During probe deformation, at least two of the vertical arm portions come into contact with each other. Such contact between the arm portions can advantageously increase the lateral scrub motion at the probe tip, and can also advantageously reduce the probe inductance.

Abstract: A probe card according to the present invention includes a support plate for supporting probes that contact an object to be inspected, a circuit board, a holding member for holding a lower surface of an outer peripheral portion of the support plate, and an abutting member disposed between the lower surface of the outer peripheral portion of the support plate and the holding member and protruding upward to abut to the lower surface of the outer peripheral portion of the support plate. Accordingly, horizontal expansion of the support plate itself is allowed, and at the time of inspecting electrical characteristics of the object to be inspected, even though the temperature of the support plate is increased and the support plate expands, the support plate can expand in a horizontal direction, thereby suppressing vertical deformation of the support plate.

Abstract: In a test method of a display panel, a test signal and a test voltage are generated according to a test control signal. A display area of the display panel is tested based on the test signal and the test voltage. A driving voltage line and an on/off voltage line formed on the display panel are tested based on the test signal and the test voltage.

Abstract: The embodiment is to provide a liquid crystal display device capable of detecting malfunctions. The liquid crystal display device includes pixels configured to be connected to scan lines and data lines, data pads electrically connected to the data lines, a data integrated circuit supplying data signals to the data lines through the data pads, first data transistors coupled to the data pads, and second data transistors coupled to the data lines. The first data transistors are disposed on the data integrated circuit and the second data transistors are separated from the data integrated circuit.

Abstract: A wafer inspection apparatus that performs surface inspection and internal inspection of solar cells using a single apparatus. The wafer inspection apparatus includes a loading unit configured to allow a cassette to be lifted up or lowered by an elevator. A surface inspection unit includes a plurality of stages, thus performing surface inspection of each wafer using a first vision module. A wafer transfer unit has a rotatably installed center portion and has both ends provided with adsorption parts. An internal inspection unit is configured such that a conveyor is installed to allow the wafer to be transferred, thus performing internal inspection of the transferred wafer through a second vision module. An unloading unit enables wafers having completed the internal inspection to be sequentially loaded onto the unloading unit. A control unit controls a series of wafer inspection procedures.

Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.

Abstract: A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

Abstract: Aspects of the disclosure provide a method for reducing crosstalk effects. The method includes tracking data for output onto at least a first transmission line and a second transmission line, determining a combined pattern in a first signal and a second signal to be respectively transmitted by the first transmission line and the second transmission line, and setting a delay to transmit at least one of the first signal and the second signal as a function of the combined pattern.

Abstract: A transceiving circuit resistance calibrating method, which is applied to a transceiving circuit. The method includes: inputting a first current to a transmitter to generate a first output voltage, wherein the first current is generated according to a ratio between a predetermined voltage and an inner resistor of a chip; inputting a second current to a transmitter to generate a second output voltage, wherein the first current is generated according to a ratio between the predetermined voltage and a predetermined resistor; and adjusting a first adjustable resistance module according to a difference between the first output voltage and the second output voltage.

Abstract: A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

Abstract: Some embodiments of the invention provide an integrated circuit (“IC”) that includes numerous configurable nodes arranged in an array having several rows and columns. In some embodiments, the configurable nodes include a first group of configurable aligned along a particular direction and a second group of configurable nodes aligned along a different direction. The IC also includes a set of direct offset turn connections arranged across the node array in a repetitive nested architecture. Each direct offset turn connection connects a node from the first group of configurable nodes to a node from the second group of configurable nodes. Each direct offset turn connection includes at least two wire segments that are arranged in at least two different directions and intersect to define a turn. No direct offset turn connection overlaps with another direct offset turn connection.

Abstract: A method of enabling partial reconfiguration in a device having configurable resources is disclosed. The method comprises receiving a configuration bitstream comprising configuration bits; configuring the configurable resources of the device using the configuration bits of the configuration bitstream; receiving a request for a partial reconfiguration of the device; loading updated configuration bits into memory elements associated with a portion of the configurable resources in response to the request for a partial reconfiguration; and providing a status of the partial reconfiguration while loading the updated configuration bits. A circuit for enabling partial reconfiguration in a device having configurable resources is also disclosed.

Abstract: Programmable logic units are described. A described unit includes one or more first logic elements that are individually programmable to be one of a plurality of first functions; one or more second logic elements that are a decoder; one or more third logic elements that are individually programmable to be one of a plurality of second functions; and a programmable interconnect array that selectively forms one or more interconnections within a group including the logic elements, one or more input interfaces, and one or more output interfaces. The array is programmable in routing one or more input signals to at least a portion of the logic elements, routing one or more intermediate signals among at least a portion of the logic elements, and routing one or signals from at least a portion of the logic elements to produce one or more output signals via the output interface.

Abstract: A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.

Abstract: A semiconductor integrated circuit in an embodiment includes a first circuit group that includes at least one first logic block and a second circuit group that includes second logic blocks. The number of the second logic blocks is greater than the number of the first logic blocks. The first circuit group includes a first switching block and a first power control circuit. The first power control circuit commonly controls a start of power supply and a stop of the power supply for the first logic block and the first switching block. The second circuit group includes second switching blocks and a second power control circuit. The second power control circuit commonly controls a start of power supply and a stop of the power supply for the second logic blocks and the second switching blocks.

Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.

Abstract: A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage.

Abstract: In embodiments of a serializing transmitter, the serializing transmitter includes one or more multiplexing drive units that each generate a series of output pulses derived from input data signals and multi-phase clock signals. Each of the multiplexing drive units includes a pulse-controlled push-pull output driver that has first and second inputs, and an output coupled to an output of the multiplexing drive unit. Each of the multiplexing drive units also includes a first M:1 (where M is two or more) pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and generating a first series of intermediate pulses at the output; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, and generating a second series of intermediate pulses at the output.

Abstract: An integrated circuit device includes at least a functional module arranged to receive a reference clock signal; a gating component configurable to perform gating of the reference clock signal; and a synchronization module. The synchronization module includes a trigger component arranged to receive a request for the functional module, the request being asynchronous with the reference clock signal, and to set an enable signal for the functional module in response to receiving the request therefor; and a synchronization component arranged to receive the enable signal, and in response to the enable signal being set to: configure the gating component to un-gate the reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the functional module following the reference clock signal being un-gated.

Abstract: A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.

Abstract: A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

Abstract: An on-load tap changer with semiconductor IGBT switching elements for uninterrupted switching over between winding taps of a tapped transformer, has two load branches connectable with the respective winding taps and each load branch is electrically connected with a common load output line through a respective series circuit consisting of two oppositely connected IGBTs. A diode is connected parallel to each IGBT, and the two diodes in each load branch are connected oppositely to one another. A respective mechanical switch is connected in series with the series circuit of IGBTs and parallel diodes in each load branch. A respective varistor is connected parallel to each parallel circuit of IGBT and diode, and the varistors are so dimensioned that the respective varistor voltages are lower than the maximum blocking voltage of the respective parallel IGBTs but higher than the maximum instantaneous value of the tap voltage.

Abstract: A circuit that produces a clocking signal for a low to medium capacitance input of a device includes a drive gate connected to a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through one coupling capacitor and to an emitter of a PNP bi-polar transistor through another coupling capacitor. The transistors are connected in a common-base configuration with the collectors of the transistors connected together. One voltage is connected to the base of the PNP transistor. Another voltage is connected to the base of the NPN transistor. A diode is connected in parallel with the base-emitter of the PNP transistor. Another diode is connected in parallel with the base-emitter of the NPN transistor. A damping resistor is connected between the collectors of the transistors and the low to medium capacitance clock input of the device.

Abstract: A switching device has a main IGFET having a Schottky barrier diode D3 for blocking an inverse current built therein, a protective switch means, and a protective switch control means. The protective switch means is connected in between a drain electrode D and a gate electrode G of the main IGFET. The protective switch control means turns on the protective switch means when an inverse voltage is impressed to the main IGFET. Thereby, the main IGFET is protected from the inverse voltage.

Abstract: A gate driving circuit includes a thermal sensing unit for sensing temperature to output a sensing voltage, a compare unit for comparing the sensing voltage with a reference voltage to output a control voltage, a charging control module for controlling a pre-charging operation according to the control voltage, and a plurality of shift register stages. Each shift register stage includes an input unit for outputting a driving control voltage according to a first input signal, a clock input unit for outputting a driving voltage according to a system clock, a driving unit for outputting a gate signal according to the driving control voltage and the driving voltage, and a pull-down unit for pulling down the gate signal and the driving control voltage according to a second input signal. The driving voltage is also controlled by the pre-charging operation for enhancing driving ability.

Abstract: A method includes setting a mode of operation of a buffer circuit outputting an output signal. The mode of operation is set to a first mode of operation or a second mode of operation. The output signal is substantially in-phase with an input signal received by the buffer circuit when the mode of operation is the first mode. The output signal is substantially out of phase with the input signal when the mode of operation is the second mode.

Abstract: An a.c. signal generator is provided with a first circuit (B1) capable of generating alternations of a first a.c. signal (S1) between a first potential (V+) formed by a first voltage source and a second potential (V?). A second circuit (B2) is capable of generating alternations of a second a.c. signal (S2), phase-shifted relative to the first signal (S1), between the first potential (V+) formed by the first voltage source and the second potential (V?). Such a generator can be used, for example, in a flight control calculator of an aircraft.

Abstract: The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

Abstract: The present invention is applicable to the field of electrics and provides an integrated circuit (IC) and a standby controlling method thereof. The IC comprises a reset device, a standby control device, a functional device and a power supply control device. The functional device at least comprises a functional unit that does not operate in a standby mode. The power supply control device is configured to supply power to the functional device, the standby control device and the reset device.

Abstract: An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern.

Abstract: Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.

Abstract: A signal synchronizing system includes comparison circuitry and control circuitry. The comparison circuitry compares a synchronizing signal with an input signal to generate a comparison result. The control circuitry adjusts the synchronizing signal into a range that is determined by the input signal, and controls the range according to the comparison result.

Abstract: A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.

Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract: A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.

Abstract: A processor frequency adjustment circuit for adjusting a frequency of a processor includes a voltage converting module, a first reference voltage generating module, a clock chip, a voltage comparing module. The voltage converting module converts a pulse voltage into a constant voltage. The first reference voltage generating module generates a first reference voltage. The voltage comparing module is connected with the voltage converting module, the first reference voltage generating module, and the clock chip to compare the constant voltage with the first reference voltage, and generates a first voltage level signal to a first terminal of the clock chip; the clock chip adjusts the frequency of the processor in response to obtaining the first voltage level signal.

Abstract: A circuit module includes: control object circuits which start operations when a power supply voltage reaches a target value; a current sink circuit which consumes a current supplied thereto; and a power supply activation control unit which increases the current flowing into the current sink circuit at a predetermined rate before starting the operations of the control object circuits and which starts the operations of the control object circuits and simultaneously blocks the supply of the current to the current sink circuit in a case where an amount of the current flowing into the current sink circuit is equivalent to an amount of current to be increased by starting the operations of the control object circuits when the power supply voltage reaches the target value.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: An electronic device comprising a level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain, the level shifter having a high-side transistor in series with a low-side transistor so as to provide an output node between the channel of the high-side transistor and the channel of the low-side transistor for driving a load with the high level output signal of the second voltage domain. The level shifter being configured to have a first state in which the high-side transistor is conducting and the low-side transistor is not conducting, a second state in which the low-side transistor is conducting and the high-side transistor is not conducting and a third state in which the high-side transistor is not conducting and the low-side transistor is not conducting.

Abstract: An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Abstract: This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold level. A positive charge pump embodiment charges the output to twice the positive supply voltage up to no more than a limit level. A negative charge pump embodiment charges the output to the same magnitude with opposite polarity as the positive supply voltage, and decreases the output magnitude if the positive supply voltage is above the threshold level. A Zener diode and controlled current mirror may be used for control.

Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: A reference voltage generating circuit includes a first power supply, a second power supply, a first variable resistance circuit having one end connected to the first power supply and configured to be capable of adjusting a resistance value of the first variable resistance circuit, a series resistance circuit having at least one resistance and one end connected to the first variable resistance circuit, a second variable resistance circuit having one end connected to the series resistance circuit and the other end connected to the second power supply, and configured to be capable of adjusting a resistance value of the second variable resistance circuit, a first terminal arranged between the first variable resistance circuit and the series resistance circuit, a second terminal arranged between the series resistance circuit and the second variable resistance circuit, and a voltage selecting circuit configured to select one of a voltage of the first terminal and a voltage of the second terminal, and output the se