Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

Abstract: A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.

Abstract: An exemplary aspect of the present invention is an SRAM including: a first gate electrode that constitutes a first load transistor; a second gate electrode that extends in a longitudinal direction of the first gate electrode so as to be spaced apart from the first gate electrode, and constitutes a first drive transistor; a third gate electrode that extends in parallel to the first gate electrode, and constitutes a second load transistor; a first p-type diffusion region that is formed so as to intersect with the third gate electrode, and constitutes the second load transistor; and a first shared contact formed over the first and second gate electrodes and the first p-type diffusion region. The first p-type diffusion region extends to the vicinity of a first gap region between the first and second gate electrodes, and is not formed in the first gap region.

Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.

Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.

Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

Abstract: A sensing device includes: a semiconductor layer of a field effect semiconductor having upper and lower surfaces; a conductive layer formed on the lower surface of the semiconductor layer; and a sensor layer of an insulator formed on the upper surface of the semiconductor layer. The insulator is made from lanthanide-titanium oxide.

Abstract: One aspect of the invention relates to an ultrathin micro-electromechanical chemical sensing device which uses swelling or straining of a reactive organic material for sensing. In certain embodiments, the device comprises a contact on-off switch chemical sensor. For example, the device can comprises a small gap separating two electrodes, wherein the gap can be closed as a result of the swelling or stressing of an organic polymer coating on one or both sides of the gap. In certain embodiments, the swelling or stressing is due to the organic polymer reacting with a target analyte.

Abstract: There is provided a memory element including a magnetic layer that includes FexNiyBz (here, x+y+z=1, 0.2x?y?4x, and 0.1(x+y)?z?0.4(x+y)) as a main component, and has magnetic anisotropy in a direction perpendicular to a film face; and an oxide layer that is formed of an oxide having a sodium chloride structure or a spinel structure and comes into contact with one face of the magnetic layer.

Abstract: To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.

Abstract: A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

Abstract: An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.

Abstract: An image sensor packaging structure with a predetermined focal length is provided. The image sensor packaging structure includes a substrate, a chip, an optical assembly, and an encapsulation compound. The chip has a sensitization area and is coupled to the substrate. Conductive contacts on the substrate are electrically connected with conductive contacts around the sensitization area. The optical assembly has the predetermined focal length and is disposed above the chip so as to form an air cavity between the optical assembly and the sensitization area of the chip. The encapsulation compound is formed on the substrate to surround the chip and the optical assembly. With the above stated structure, not only can the focus adjusting procedure be dispensed with, but also the image sensor packaging structure can be manufactured by a molding or dispensing process.

Abstract: According to one embodiment, an image detector comprises a plurality of photosensitive detector unit cells interconnected to a plurality of integrated circuits by a plurality of direct bond interconnects. Each unit cell includes an absorber layer and a separation layer. The absorber layer absorbs incident photons such that the absorbed photons excite photocurrent comprising first charged carriers and second charged carriers having opposite polarities. The separation layer separates the first charged carriers for collection at one or more first contacts and the second charged carriers for collection at one or more second contacts. The first and second contacts include the direct bond interconnects to conduct the first charged carriers and the second charged carriers from the unit cells in order to facilitate image processing.

Abstract: A manufacturing method of a solid-state imaging device includes: preparing a photoelectric conversion device; forming an insulating layer on a surface of the photoelectric conversion device; forming a wire-grid polarizer on a support base; bonding a forming surface of the wire-grid polarizer on the support base to the insulating layer on the surface of the photoelectric conversion device and removing the support base from the wire-grid polarizer.

Abstract: This bispectral detector comprises a plurality of unitary elements for detecting a first and a second electromagnetic radiation range, consisting of a stack of upper and lower semiconductor layers of a first conductivity type which are separated by an intermediate layer that forms a potential barrier between the upper and lower layers; and for each unitary detection element, two upper and lower semiconductor zones of a second conductivity type opposite to the first conductivity type, are arranged respectively so that they are in contact with the upper faces of the upper and lower layers so as to form PN junctions, the semiconductor zone being positioned, at least partially, in the bottom of an opening that passes through the upper and intermediate layers. The upper face of at least one of the upper and lower layers is entirely covered in a semiconductor layer of the second conductivity type.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodiode assembly includes a semiconductor substrate, a photodiode cell, a ground diffusion region, and a guard band. The photodiode cell includes a first volume of the substrate doped with a first type of dopant. The diffusion region includes a second volume of the substrate that is doped with a second, opposite type of dopant. The guard band is disposed in the substrate and at least partially extends around an outer periphery of the photodiode cell. The guard band includes a third volume of the substrate that is doped with the first type of dopant. At least one of the ground diffusion region or the guard band is conductively coupled with a ground reference to conduct one or more of electrons or holes that drift from the photodiode cell through the substrate. The guard band is disposed closer to the photodiode cell than the ground diffusion region.

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A thermopile sensor array is provided. The thermopile sensor array may include multiple pixels formed by multiple thermopiles arranged on a single common shared support membrane. A separation between the edge of the shared support membrane and the outermost thermopile(s) may be included to provide additional thermal isolation between the thermopile and an underlying silicon substrate.

Abstract: A resonator element for the absorption and/or conversion of electromagnetic waves having a predefined wavelength, in particular infrared radiation having a wavelength of 2 ?m to 200 ?m, into heat, has a three-layer structure formed of a first metal layer, a second metal layer and a dielectric layer interposed between the two metal layers. The maximum lateral dimension of the layers is in the range between one quarter and a half of the predefined wavelength.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A fuse of a semiconductor device comprises: a fuse pattern formed on a semiconductor substrate; an insulating film covering one side of the fuse pattern and including a trench; a conductive line disposed on the insulating film including the trench. The fuse of the semiconductor device prevents generation of cracks in a fuse box by thermal and physical stress, thereby improving reliability of the semiconductor device.

Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Abstract: A semiconductor package includes a semiconductor chip and a passive element. The semiconductor chip has a semiconductor chip body which possesses a first surface and a second surface facing away from the first surface, and a circuit section is formed in the semiconductor chip body. The passive element includes passive element bodies which are disposed in through-electrodes passing through the semiconductor chip body and connection members which are disposed on at least one of the first surface and the second surface of the semiconductor chip body and which electrically connect to at least one of the passive element bodies.

Abstract: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure.

Abstract: A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Abstract: Ferroelectric capacitors (42) are formed over a semiconductor substrate (10), then, a barrier film (46) directly covering the ferroelectric capacitors (42) is formed. Thereafter, wirings (56a etc.) connected to the ferroelectric capacitors (42) are formed. Further, a barrier film (58) is formed at a position higher than the wirings (56a etc.). In forming the barrier film (46), a film stack is formed, the film stack including at least two kinds of diffusion preventive films (46a and 46b) having different components and preventing diffusion of hydrogen or water.

Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.

Abstract: Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract: A semiconductor device includes an element forming region including at least one semiconductor element formed on at least one compound semiconductor layer formed on a substrate and a trench formed between an outer edge of the semiconductor device and the element forming region. The trench spatially separates the compound semiconductor layer, and the trench is formed at least to reach the substrate.

Abstract: An apparatus includes a crystalline substrate. A cleaving guide on the substrate is positioned over a cleave plane of the crystalline substrate and positioned in a known location with respect to a feature of an electronic device on the substrate. Cleaving of the substrate along the cleave plane changes a physical characteristic of the cleaving guide and measurement of the physical characteristic provides a parameter representative of the relative position of the cleave plane and the cleaving guide.

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and a metal layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

Abstract: A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies that incorporate the flexible film interposer, and methods of fabricating the devices and assemblies are provided. The incorporation of the flexible film interposer achieves densely packaged semiconductor devices, without the need for a redistribution layer (RDL).

Abstract: To improve manufacture of an electronic circuit, the electronic circuit is composed of modules of sub-circuits arranged on a common substrate, such as a cooling body, and that are electrically interconnected by a planar electrical contact element.

Abstract: A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.

Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Abstract: In some aspects of the invention, an insulating substrate fixed onto a metal base plate can include an insulating plate and metal foils. A semiconductor element can be disposed on each of the metal foils. External connection terminals can be fixed to a set of ends of terminal holders, respectively. The other ends of the terminal holders can be bonded to the metal foils, respectively. External connection terminals which are main terminals through which main current flows are disposed on a lid. By preparing a plurality of lids having different layouts of the external connection terminals, in which the external connection terminals are connected to the terminal holders in the resin case, respectively, and exchanging the lids, the positions of the external connection terminals can be easily changed.

Abstract: A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.

Abstract: A heat spreader package includes a substrate having a first surface, first traces on the first surface of the substrate, and an electronic component having an inactive surface mounted to the first surface of the substrate. The electronic component further includes an active surface having bond pads. Bond wires electrically connect the bond pads to the first traces. An inverted pyramid heat spreader includes a first heatsink, a first heatsink adhesive directly connecting the first heatsink to the active surface of the electronic component inward of the bond pads, a second heatsink having an absence of active circuitry, and a second heatsink adhesive directly connecting a first surface of the second heatsink to the first heatsink. The second heatsink adhesive is a dielectric directly between the bond wires and the second heatsink that prevents inadvertent shorting between the bond wires and the second heatsink.

Abstract: A manufacturing method of a package carrier is provided. A first opening communicating an upper surface and a lower surface of a substrate is formed. A heat-conducting element having a top surface and a bottom surface is configured in the first opening and fixed into the first opening via an insulation material. A first insulation layer and a first metal layer are laminated onto the upper surface. A second insulation layer and a second metal layer are laminated onto the lower surface. A second opening and a third opening respectively exposing portions of the top and the bottom surfaces are formed. At least one through via passing through the first metal layer, the first insulation layer, the substrate, the second insulation layer and the second metal layer is formed. A third metal layer covering the first and second metal layers and an inner wall of the through via is formed.

Abstract: A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.

Abstract: A semiconductor device has a first semiconductor die having at least one metal pillar formed along an inner perimeter and at least one bond pad formed along an outer perimeter. A second semiconductor die has at least one metal pillar. A conductive bump connects the at least one metal pillar of the first semiconductor die to the at least one metal pillar of the second semiconductor die. At least one metal dam is formed on the first semiconductor die between the at least one metal pillar of the first semiconductor die and the at least one bond pad.