Abstract: Light emitter packages and devices having improved wire bonding and related methods are disclosed. In one embodiment a light emitter package can include at least one light emitting diode (LED) chip electrically connected to an electrical element via a wire bond. The wire bond can be provided at improved wire bonding parameters such as a temperature of approximately 150° C. or less, a bonding time of approximately 100 ms or less, a power of approximately 1700 mW or less, and a force of approximately 100 grams force (gf) or less, or combinations thereof.

Abstract: An organic light emitting diode display includes a substrate, a white pixel and a color pixel, each including an emission area, a non-emission area, a thin film transistor on the substrate, and an organic light emitting element on the substrate and electrically connected to the thin film transistor and configured to emit light at the emission area, a color filter layer between the organic light emitting element of the color pixel and the substrate at the emission area of the color pixel, and an overcoat layer having an overcoat opening corresponding to the emission area of the white pixel, and covering the color filter layer between the organic light emitting element of the color pixel and the color filter layer.

Abstract: According to one embodiment, a light-emitting circuit includes: a plurality of substrates in which wiring pattern layers are formed, the substrates including light-emitting elements connected to and mounted on the wiring pattern layers; and a linear conductor having electric conductivity, the linear conductor including linear joining sections at both ends electrically connected to the wiring pattern layers of the substrates and a convex section formed to be bent in a convex shape in an intermediate section between the joining sections, and the joining sections being respectively joined to the wiring pattern layers among the plurality of substrates adjacent to one another.

Abstract: A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer located on at least one semiconductor light-emitting chip in order to emit various colored lights including white light. The semiconductor light-emitting device can include a casing having a cavity and a mounting surface, the chip mounted on the mounting surface, a transparent plate mounted on the wavelength converting layer within a top surface of the chip and a reflective layer located in the cavity so as to surround the transparent plate, the wavelength converting layer and the chip. The semiconductor light-emitting device can be configured to improve light-colored variability and light-emitting efficiency of the chip by using the reflective layer as a reflector, and therefore can emit a wavelength-converted light having a substantially uniform color tone and a high light-emitting efficiency from a smaller light-emitting surface than the top surface of the chip.

Abstract: A light-emitting device includes a substrate; a light-emitting element formed on the substrate; a seal member sealing the light-emitting element, the seal member formed of a transparent dry film resist laminated on the substrate with the light-emitting element interposed therebetween.

Abstract: A light emitting device includes a plurality of light emitting elements, a plurality of lead frames, and a package. The light emitting elements are mounted on the lead frames. The package is made of resin. The package has an opening. A part of the lead frames is embedded in an inner portion of the package and another part of the lead frames is exposed on a bottom surface of the opening. A resin bottom surface on which the resin is exposed is provided on the bottom surface of the opening of the package. The package includes a wall portion projecting from the bottom surface of the opening between the light emitting elements in the opening. The light emitting elements are connected by wire that straddles the wall portion.

Abstract: An array substrate includes a lower substrate, a switching element and a pixel electrode. In the lower substrate, unit pixel areas are each divided into a plurality of domains. The switching element is disposed on the lower substrate and transmits a pixel signal. The pixel electrode is disposed on the unit pixel area and is electrically connected to the switching element. The pixel electrode includes a plurality of slit portions disposed thereon. A portion of the slit portions is longitudinally extended in a zigzag shape along different directions in correspondence with the domains.

Abstract: A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a dam resin made of a resin having a low optical transmittance; a fluorescent-material-containing resin layer; and an anode-side electrode and a cathode-side electrode, (a) which are provided on a primary surface of the ceramic substrate so as to face each other along a first direction on the primary surface and (b) which are disposed below at least one of the dam resin and the fluorescent-material-containing resin layer. With the configuration in which a plurality of LEDs, which are connected in a series-parallel connection, are provided on a substrate, it is possible to provide a light emitting device which can achieve restraining of luminance unevenness and an improvement in luminous efficiency.

Abstract: An LED-based lighting assembly includes a heat sink having at least one pedestal with an upwardly facing, upper planar surface that is raised in a vertical direction relative to an upwardly facing, lower planar surface of the heat sink. A PCB forms an aperture corresponding to the pedestal, includes electrical conductors on an upper surface thereof, and is attached to the lower planar surface. The upper planar surface extends into the aperture, and one or more LED chips attach directly to the upper planar surface and connect to the conductors such that light emits upwardly. A method of integrating LEDs with a heat sink includes mounting a PCB to a planar surface of the heat sink, mounting one or more LED chips to a raised surface of the heat sink that is not covered by the PCB, and electrically connecting the LED chips to conductors on the PCB.

Abstract: Disclosed are a light emitting device, a light emitting device package and a light emitting module. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a support member under the light emitting structure; a reflective electrode layer between the second conductive semiconductor layer and the support member; and first to third connection electrodes spaced apart from each other in the support member. The second connection electrode is disposed between the first and third connection electrodes, the first and third connection electrodes are electrically connected with each other, and the support member is disposed at a peripheral portion of the first to third connection electrodes.

Abstract: A white LED assembly includes a blue LED die attached to a substrate. A first volume of a first luminescent material surrounds the blue LED die in a lateral dimension such that none of the first luminescent material is disposed directly over the blue LED die. The first luminescent material includes a relatively inefficient phosphor having a peak emission wavelength longer than 620 nm and includes substantially no phosphor having a peak emission wavelength shorter than 620 nm. A second volume of a second luminescent material is disposed over the first volume and the blue LED die. The second luminescent material includes a relatively efficient phosphor having a peak emission wavelength shorter than 620 nm and includes substantially no phosphor having a peak emission wavelength longer than 620 nm. Placement of the first and second luminescent materials in this way promotes removal of heat from the inefficient phosphor and reduces the likelihood of interabsorption.

Abstract: A method of forming a vertical III-nitride based light emitting diode structure and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-on-insulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based substrate of the light emitting structure.

Abstract: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.

Abstract: Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In some aspects, light emitter components can include a submount with a first side having a first surface area, first and second electrical contacts disposed on the first side of the submount, and at least one light emitter chip on the first side. In some aspects, the electrical contact area can be less than half of the first surface area of the first side of the submount. Components disclosed herein can include low profile parts or domes where a ratio between a dome height and a dome width is less than 0.5. A method of providing components can include providing a panel of material and LED chips, dispensing a liquid encapsulant material over the panel, and singulating the panel into individual submount based components after the encapsulant material has hardened.

Abstract: An optoelectronic component includes a semiconductor chip, and a phosphor at least partly surrounding the semiconductor chip, wherein 1) the semiconductor chip emits a primary radiation in a short-wave blue spectral range at a dominant wavelength of less than approximately 465 nm, and wherein the phosphor converts at least part of the primary radiation into a longer-wave secondary radiation in a green spectral range at a dominant wavelength of approximately 490 nm to approximately 550 nm, and 2) a mixed light composed of primary radiation and secondary radiation has a dominant wavelength at wavelengths of approximately 460 nm to approximately 480 nm such that luminous flux of the mixed light is up to 130% greater than luminous flux of an optoelectronic component without a phosphor having the same dominant wavelength of 460 nm to 460 nm.

Abstract: An optoelectronic component includes a protective layer including a material containing hydrophobic groups. Furthermore, a method is described, by means of which an optoelectronic component can be produced, and in which a protective layer including hydrophobic groups is applied.

Abstract: A III nitride semiconductor light emitting device with improved light emission efficiency achieved without significantly increasing forward voltage by achieving both good ohmic contact between an electrode and a semiconductor layer, and sufficient functionality of a reflective electrode layer, and a method for manufacturing the same. The III nitride semiconductor light emitting device has a III nitride semiconductor laminate including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer; an n-side electrode, a p-side electrode; and a composite layer having a reflective electrode portion and a contact portion made of AlxGa1-xN (0?x?0.05) on a second surface of the III nitride semiconductor laminate. The second surface is opposite to a first surface on the light extraction side.

Abstract: The invention relates to compounds of the general formula (I): Lu3-x-zAxAl5-y-zScyO12:MnzCaz,, where A stands for Y, Gd or Tb, x stands for a value from the range from 0 to 2.90, y stands for a value from the range from 0 to 0.50, z stands for a value from the range from 0.005 to 0.05, and to a process for the preparation of these phosphors and to the use thereof as conversion phosphors or in lamps.

Abstract: An object of the present invention is to reduce the thickness of a lighting device using an electroluminescent material. Another object of the present invention is to simplify the structure of a lighting device using an electroluminescent material to reduce cost. A light-emitting element having a stacked structure of a first electrode layer, an EL layer, and a second electrode layer is provided over a substrate having an opening in its center, and a first connecting portion and a second connecting portion for supplying electric power to the light-emitting element are provided in the center of the substrate (in the vicinity of the opening provided in the substrate).

Abstract: Provided is a light emitting element, a light emitting device including the same, and fabrication methods of the light emitting element and light emitting device. The light emitting device comprises a substrate, a light emitting structure including a first conductive layer of a first conductivity type, a light emitting layer, and a second conductive layer of a second conductivity type which are sequentially stacked, a first electrode which is electrically connected with the first conductive layer; and a second electrode which is electrically connected with the second conductive layer and separated apart from the first electrode, wherein at least a part of the second electrode is connected from a top of the light emitting structure, through a sidewall of the light emitting structure, and to a sidewall of the substrate.

Abstract: The invention relates to a method and a semifinished product for producing a light-emitting diode including: a flexible supporting material; a first and a second contact area, arranged on the supporting material, for producing electrical connections; a light-emitting diode chip or a holder for a light-emitting diode chip, arranged on the supporting material; a foldable flap, formed into the supporting material, the flap being arranged in such a way that it can be folded towards and/or onto the light-emitting diode chip. Arranged on the foldable flap is at least a first electrical connecting web, which is connected to the first contact area and can be connected to a first terminal of the light-emitting diode chip by folding of the flap.

Abstract: Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling.

Abstract: A method of producing a light emitting diode device includes preparing an encapsulating resin layer; embedding a light emitting diode element in the encapsulating resin layer; and heating while pressing with gas the encapsulating resin layer having the light emitting diode element being embedded therein.

Abstract: In a semiconductor light emitting element having a sapphire substrate, and a lower semiconductor layer and an upper semiconductor layer laminated on the sapphire substrate, the sapphire substrate includes a substrate top surface, a substrate bottom surface, first substrate side surfaces and second substrate side surfaces; plural first cutouts and plural second cutouts are provided at border portions between the first substrate side surface and the substrate top surface and between the second substrate side surface and the substrate top surface; the lower semiconductor layer includes a lower semiconductor bottom surface, a lower semiconductor top surface, first lower semiconductor side surfaces and second lower semiconductor side surfaces; plural first projecting portions and plural first depressing portions are provided on the first lower semiconductor side surface; and plural second protruding portions and second flat portions are provided on the second lower semiconductor side surface.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.

Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

Abstract: Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (?Ee) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si ?-doping layer to supply electron carriers to the III-V channel.

Abstract: MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.

Abstract: A device including at least one transistor on a substrate in a first semiconductor material, each transistor including a gate electrode as a gate, two conductor electrodes, an island in a second semiconductor material inlaid in the substrate, defining a region capable of forming a channel as a channel region, and an insulating layer separating the gate from the two electrodes and the channel region. The channel region is inside the island and is in direct electrical contact with at least one of the two conductor electrodes.

Abstract: An embodiment of a compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; a two-dimensional electron gas suppressing layer formed over the electron supply layer; an insulating film formed over the two-dimensional electron gas suppressing layer and the electron transit layer; and a gate electrode formed over the insulating film. The gate electrode is electrically connected with the two-dimensional electron gas suppressing layer.

Abstract: A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.

Abstract: A high electron mobility transistor comprising: an epitaxial substrate comprising a semi-insulating substrate, a buffer layer and a barrier layer sequentially stacked; a first and a second current conducting electrode formed on, and in ohmic contact with, the barrier layer; a control gate and one or more field plate electrode(s) formed on, and in contact with, the barrier layer between the first and second current conducting electrodes; and an electric circuit formed for electrically connecting each field plate electrode to an electric reference potential and comprising at least a rectifying contact and/or an electric resistor, wherein the rectifying contact is formed outside the channel area of the high electron mobility transistor and is distinguished from the rectifying contact formed by the corresponding field plate electrode.

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error.

Abstract: Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region

Abstract: An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.

Abstract: An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.

Abstract: In a semiconductor device including a transistor using an oxide semiconductor film, stable electric characteristics can be provided and high reliability can be achieved. A structure of the semiconductor device, which achieves high-speed response and high-speed operation, is provided. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in order and a sidewall insulating layer is provided on the side surface of the gate electrode layer, the sidewall insulating layer has an oxygen-excess regions, which is formed in such a manner that a first insulating film is formed and then is subjected to oxygen doping treatment, a second insulating is formed over the first insulating film, and a stacked layer of the first insulating film and the second insulating film are etched.

Abstract: The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern.

Abstract: According to an embodiment, a light-receiving circuit includes a MOSFET, a first light-receiving element and a second light-receiving element. The first light-receiving element controls a state of the MOSFET between ON state and OFF state by applying a voltage induced by a light signal between a gate of the MOSFET and a source of the MOSFET; and a second light-receiving element controls a threshold voltage of the MOSFET.

Abstract: In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.

Abstract: A photoelectric conversion apparatus includes: a first semiconductor region forming a part of a photoelectric conversion element; a second semiconductor region stacked on the first semiconductor region, and forming a part of the photoelectric conversion element; a third semiconductor region to which a signal charge transferred from the photoelectric conversion element; a fourth semiconductor region of the first conductivity type having an higher impurity concentration, between the first and third semiconductor region and between the second and third semiconductor regions, closer to a main surface than the first semiconductor region, and connected to the first semiconductor region; a first gate electrode over the fourth semiconductor region, an insulating film on the main surface and between the first gate electrode and the fourth semiconductor region; and a second gate electrode between the third and fourth semiconductor regions, and over the insulating film.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Abstract: A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a plurality of interconnects, and a plurality of gap control units. The substrate includes silicon. The plurality of interconnects is provided above the substrate. The plurality of gap control units is provided respectively on the plurality of interconnects to have width dimensions greater than width dimension of the plurality of interconnects. A gap is provided between adjacent interconnects of the plurality of interconnects. An apical portion of the gap is provided between adjacent gap control units of the plurality of gap control units and between a lower surface position and an upper surface position of each of the adjacent gap control units.