Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor within a trench in a workpiece, the capacitor comprising a bottom electrode, a dielectric layer disposed over the bottom electrode, and a top electrode disposed over the dielectric layer. A cap layer is formed over the capacitor. Forming the capacitor and forming the cap layer comprise optimizing at least one of: a width of the trench, a thickness of the bottom electrode, a thickness of the dielectric layer, a thickness of the top electrode, and a thickness of the cap layer, so that the cap layer completely covers the top electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.

Abstract: The invention relates to an electronic device with a bipolar transistor having an emitter, a base and a collector. The base has a first region of a first concentration of the first dopant for forming an electrically active region of the base and a second region of a second concentration of the first dopant close to the surface of the base region. The first region is separated from the second region by a region of a third concentration of the first dopant and the third concentration is lower than the first and the second concentration.

Abstract: The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process.

Abstract: A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.

Abstract: A semiconductor substrate having dot marks is provided. Particularly, a semiconductor substrate having dot marks having an improved reading rate is provided. In a semiconductor substrate having a plurality of dot marks formed of recess portions having an inverted frustum shape, the plurality of dot marks constitutes a two-dimensional code disposed in a rectangular region of 0.25 mm2 to 9 mm2, the diameter W of the recess portion on the surface of the semiconductor substrate is 20 ?m to 200 ?m, is larger than the diameter w of the bottom surface of the recess portion, and is smaller than the thickness of the semiconductor substrate, the side surface of the recess portion has four or more trapezoidal flat taper surfaces, and the taper angle of the taper surface is in a range of 44° to 65° with respect to the surface of the semiconductor substrate.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

Abstract: A method of forming a semiconductor structure includes forming a photoresist layer over a substrate. The photoresist layer includes a first material removable by a removal process. The first material at a guard band portion of the photoresist layer along an edge portion of the photoresist layer is converted to a second material. The second material is not removable by the removal process. Also, the first material at the edge portion of the photoresist layer is not converted to the second material. The guard band portion is farther from a periphery of the substrate than the edge portion. The removal process is performed to remove the first material after the conversion of the guard band portion.

Abstract: Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.

Abstract: An integrated circuit shielding film and a manufacturing method thereof. The manufacturing method provides a plate. A stripping glue is coated on the plate. An integrated circuit is disposed on the stripping glue and the stripping glue is deposited on the surface of the integrated circuit. A shielding film is then formed on the integrated circuit by coating operations.

Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.

Abstract: A plurality of terminal plates are arranged in a row in the interior of a box body. Neighboring terminal plates are electrically connected by a diode. The diode is provided with a first terminal part that is laid on, soldered to, and electrically connected to the first terminal plate. A slit is provided formed along the outer perimeter of a region on which the first terminal part is laid on the first terminal plate.

Abstract: Integrated circuit dies and methods of fabricating the dies are disclosed. An embodiment of a method includes providing a die having a redistribution layer fabricated thereon. The redistribution layer has a surface located thereon that is free of any seed layers. An under bump metal layer is fabricated directly to the surface.

Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.

Abstract: A fabrication method of a semiconductor package includes: disposing a first wafer on a substrate having at least a conductive pad; stacking a second wafer on the first wafer, wherein the second wafer has a pre-open area corresponding in position to the conductive pad of the substrate; forming a protection layer on the second wafer; embrittling the protection layer on the pre-open area of the second wafer; and removing the embrittled portion of the protection layer and portions of the second and first wafers so as to form an opening to expose the conductive pad, thereby preventing an adhesive layer from being attached to a cutting tool as in the prior art.

Abstract: In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure.

Abstract: A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.

Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Abstract: A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

Abstract: A method of manufacturing a semiconductor device comprises a mounting step of mounting a semiconductor element having an Au—Sn layer on a substrate, wherein the mounting step includes a paste supplying step of supplying an Ag paste having an Ag nanoparticle onto the substrate, a device mounting step of mounting a side of the Au—Sn layer of the semiconductor element on the Ag paste, and a bonding step of alloying the Au—Sn layer and the Ag paste to bond the semiconductor element to the substrate, wherein the Au—Sn layer has a content rate of Au of 50 at % to 85 at %.

Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.

Abstract: A method, system and apparatus for connecting multiple memory device dies 51-54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52-54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop.

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

Abstract: A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower.

Abstract: There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

Abstract: A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer.

Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Abstract: A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.

Abstract: A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.

Abstract: A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement.

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract: A gas flow bubbler system for delivering a precursor gas to a production chamber, the bubbler system comprising: a bubbler for containing precursor molecules in a liquid phase; a cyclone separator for removing aerosol particles from the precursor gas; and a tube through which precursor gas generated in the bubbler flows to the cyclone separator.

Abstract: The invention concerns a beverage dispenser comprising: a frame (1) for supporting the components of the dispenser, a whipper assembly (2) comprising a whipper 9b housing (21), a whipper device (22) and a back wall (23), the whipper housing and the back wall forming a whipper chamber (24) in which is lodged the whipper device, a drive shaft (3) for driving the whipper device (22), said drive shaft being supported by the frame (1), detachable connection means (4a, 4b) for attaching the back wall to the whipper housing, wherein it further comprises detachable connection means (5) for attaching the whipper housing to the frame.

Abstract: A method and a device for producing a lens wafer which has a plurality of microlenses, as well as microlenses produced from the lens wafer.

Abstract: A reflector molding apparatus includes two pressure rollers with pressure surfaces of the rollers comprising convex teeth and concave teeth in mesh. The reflection film is put on the aluminum sheet as the unmolded material. The unmolded material goes to the pressure surfaces in mesh and is molded to be a reflector. The surface of the resulting reflector is corrugated shaped because of the pressure of the rollers. The shape of the reflector changes with the pressure surface of the rollers.

Abstract: The process comprises delivering a spray solution comprising at least one solute in a solvent to a spray-drying apparatus, using a flash nozzle to atomize the spray solution into droplets within the spray-drying apparatus to remove at least a portion of the solvent from the droplets to form a plurality of particles, and collecting the particles. The spray solution is directed to a heat exchanger, thereby increasing the temperature of the spray solution to a temperature T2, wherein T2 is greater than T1. The flash nozzle comprises a central tube through which the spray solution is delivered and an outer tube through which a sweep gas is delivered. The central tube may have a first outer diameter at an inlet and a second outer diameter at an outlet, wherein the first outer diameter is greater than the second outer diameter.

Abstract: Embodiments provide a dual action gyratory thermoforming press. The dual action gyratory thermoforming press can include a multiposition gyratory head. The multiposition gyratory head can include multiple forming vessels that can include a mold platform. The multiposition gyratory head can also be connected to a bottom platform. The dual action gyratory thermoforming press can be brought into configuration for forming by rotating the multiposition gyratory head such that a forming vessel is in a forming position, displacing the bottom platform to bring the multiposition gyratory head into a forming position, and displacing the mold platform into a forming position.

Abstract: Phosphor that can provide white LED that uses a blue LED or an ultraviolet LED as a light source and that has superior luminous efficiency. This phosphor includes, as a main component, ?-type sialon represented by a general expression: (M1)x(M2)y(Si,Al)12(O,N)16 (where M1 is one or more types of elements selected from a group consisting of Li, Mg, Ca, Y, and lanthanide element (except for La and Ce) and M2 is one or more types of elements selected from a group consisting of Ce, Pr, Eu, Tb, Yb, and Er, and 0.3?X+Y?1.5 and 0<y?0.7 are established and the sialon phosphor consists of a powder having a specific surface area of 0.2 to 0.5 m2/g.

Abstract: A blow molding system having a blow molding station with at least one mold assembly and method for forming a filled container therewith. The blow molding station including at least one blow nozzle coupled to a source of blowing medium and configured to discharge the blowing medium into the preform to simultaneously form and fill a container with the blowing medium, wherein the blowing medium is the product to be contained within the container. A blow-off nozzle is provided and oriented in a direction to discharge a stream of cleaning medium at the blow nozzle causing residual blowing medium to be removed from the blow nozzle.

Abstract: An imprint apparatus cures an imprint material, while a pattern formed on a mold is kept in contact with the imprint material, thereby transferring the pattern onto the imprint material. The apparatus includes a measurement unit which performs, in parallel, alignment measurement in which a relative position between the mold and a shot region on the substrate, to which the pattern is to be transferred, is measured so as to align the mold and the shot region, and overlay measurement in which a relative position between a first pattern already formed in another shot region on the substrate using the mold, and a second pattern underlying the first patter is measured.

Abstract: A foreign substance inspection apparatus includes: an irradiation unit configured to irradiate a surface of an object to be inspected with inspection light; a detector configured to detect light scattered by the surface irradiated with the inspection light; a determination unit configured to determine, using data of a surface roughness of the object, and data of a size of the foreign substance, an irradiated region of the inspection light on the surface, that allows light scattered by the foreign substance to be discriminated from light scattered by the object due to the surface roughness of the object; and a controller configured to control the irradiation unit so as to irradiate the irradiated region determined by the determination unit with the inspection light.

Abstract: A rigid insulating phenolic foam body (8) has at least one perforated facing (1). The facing (1) is preferably perforated before the facing (1) is adhered to the foam body. The facing (1) may be a gas impermeable material such as a metallic foil. The perforations (5) in the gas impermeable material reduce the drying and curing time, for phenolic foam bodies when compared with phenolic foam bodies with gas permeable facings.