Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.

Abstract: Disclosed is a light emitting device. The light emitting device includes a light emitting structure layer including a first semiconductor layer, an active layer, and a second semiconductor layer, an electrode electrically connected to the first semiconductor layer, an electrode layer under the light emitting structure layer, and a conductive support member under the electrode layer. The conductive support member includes a protrusion projecting from at least one edge.

Abstract: A semiconductor light-emitting device capable of improving current distribution, and a method for manufacturing the same is disclosed, wherein the semiconductor light-emitting device comprises a substrate; an N-type nitride semiconductor layer on the substrate; an active layer on the N-type nitride semiconductor layer; a P-type nitride semiconductor layer on the active layer; a groove in the P-type nitride semiconductor layer to form a predetermined pattern in the P-type nitride semiconductor layer; a light guide of transparent non-conductive material in the groove; and a transparent electrode layer on the P-type nitride semiconductor layer with the light guide.

Abstract: A light emitting diode (LED) package comprising a carrier, an LED chip, a lens, and a phosphor layer is provided. The LED chip disposed on the carrier. The lens encapsulating the LED chip has a plurality of fins surrounding the LED chip and a conical indentation. The fins extending backward the LED chip radially. Each of the fins has at least one light-emitting surface and at least one reflection surface adjoining the light-emitting surface. A bottom surface of the conical indentation is served as an total reflection surface. The phosphor layer is disposed on the light-emitting surfaces of the lens. An LED package and an LED module are also provided.

Abstract: An LED module comprises at least one LED chip emitting monochromatic light having a first spectrum, a platform on which the LED chip is mounted, a reflecting wall that is separate from or integrated into the platform and surrounds the LED chip on all sides, and a dispensed layer applied above the LED chip. The dispensed layer extends in a dome-shaped manner beyond the reflecting wall such that the following equation is satisfied: 0.1*b?h?0.5*b where h is the height of the dome-shaped dispensed layer, measured from the topmost point of the reflecting wall to the apex of the dome, and b is the diameter of the depression formed by the reflecting wall, measured as the distance from the central axis of the wall.

Abstract: An optoelectronic component (1) is provided, having at least two connecters (2) for electrical contacting of the component (1), a housing body (3), in which the connecters (2) are embedded in places, a heat sink (4), which is connected to at least one connecter (2), wherein the housing body (3) is formed of a plastics material, the housing body (3) comprises an opening (30), in which the heat sink (4) is freely accessible in places, at least one optoelectronic semiconductor chip (5) is arranged in the opening (30) on the heat sink (4), and at least two of the connecters (2) each comprise a chip-end portion (2c), which faces the at least one optoelectronic semiconductor chip (5), wherein the chip-end portions (2c) of the at least two connecters (2) are arranged in a common plane.

Abstract: A light emitting device package includes a body, a first reflective cup and a second reflective cup disposed in a top surface of the body spaced from each other, a connection pad disposed in the top surface of the body spaced apart from the first reflective cup and the second reflective cup, a recess formed in the top surface of the body spaced apart from the first reflective cup, the second reflective cup, and the connection pad, a first semiconductor light emitting device disposed in the first reflective cup, a second semiconductor light emitting device disposed in the second reflective cup, and a Zener diode disposed in the recess, wherein the first reflective cup and the second reflective cup are recessed from the top surface of the body.

Abstract: Disclosed is a group III nitride semiconductor light-emitting device which suppresses electric current concentration in a light-transmitting electrode and a semiconductor layer directly below an electrode to enhance light emission efficiency, suppresses light absorption in the electrode or light loss due to multiple reflection therein to enhance light extraction efficiency, and has superior external quantum efficiency and electric characteristics. A semiconductor layer (20), in which an n-type semiconductor layer (4), a light-emitting layer (5) and a p-type semiconductor layer (6) are sequentially layered, is formed on a single-crystal underlayer (3) which is formed on a substrate (11). A light-transmitting electrode (7) is formed on the p-type semiconductor layer (6). An insulation layer (15) is formed on at least a part of the p-type semiconductor layer (6), and the light-transmitting electrode (7) is formed to cover the insulation layer (15).

Abstract: An LED includes a seat and an LED chip. The seat includes a main body, a first electrode protruding upwardly from the main body, and a second electrode formed on the main body. The LED chip includes a substrate, a first semiconductor layer disposed on the substrate, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, and a third electrode fixed on the second semiconductor layer. The first electrode extends through the substrate and electrically connects with the first semiconductor layer, and the third electrode electrically connects with the second electrode via a wire.

Abstract: Disclosed is a light emitting device. The light emitting device includes a substrate, a semiconductor layer on the substrate, and an electrode on the semiconductor layer, wherein the substrate has at least one side surface having a predetermined tilt angle with respect to a bottom surface of the substrate, wherein the predetermined tilt angle is an obtuse angle, and wherein a side surface of the semiconductor layer disposes vertically.

Abstract: A light-emitting diode package is provided. The light-emitting diode package comprises a substrate and a first metal layer disposed over the substrate. A solder layer is disposed on the first metal layer and a light-emitting diode chip is disposed on the solder layer, wherein the light-emitting diode chip comprises a conductive substrate and a multilayered epitaxial structure formed on the conductive substrate, and wherein the conductive substrate is adjacent to the solder layer.

Abstract: A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.

Abstract: A light emitting device including a light emitting chip and a magnetic material is provided. The light emitting chip includes a first doped semiconductor layer, a second doped semiconductor layer, and a light emitting semiconductor layer disposed between the first doped semiconductor layer and the second doped semiconductor layer. The magnetic material is disposed beside the light emitting chip, wherein the magnetic material is not disposed on a conducting path of a current causing the light emitting chip to emit light.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a film covering a side face of the first metal pillar and a side face of the second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The film has a solder wettability poorer than a solder wettability of the first metal pillar and a solder wettability of the second metal pillar. The resin layer covers at least part of the film.

Abstract: Side-mountable semiconductor light emitting device packages include an electrically insulating substrate having a front face and a back face and a side face extending therebetween. The side face is configured for mounting on an underlying surface. An electrically conductive contact is provided proximate an edge of the substrate on the back face of the substrate and/or on a recessed region on the side face of the substrate. The contact is positioned to be positioned proximate an electrical connection region of the underlying surface when the semiconductor light emitting device package is side mounted on the underlying surface. A conductive trace extends along the front face of the substrate and is electrically connected to the contact. A semiconductor light emitting device is mounted on the front face of the substrate and electrically connected to the conductive trace.

Abstract: A lighting device (1;15) comprising at least one flexible printed circuit board (3) which is populated with at least one semiconductor light source, comprising a potting material overlaid on at least one populated side of the printed circuit board so as to leave at least one emission surface of the semiconductor light source (2) exposed; an adhesive element at least partially covering a top side of the semiconductor light source, wherein the adhesive element (7) protrudes partially from the potting compound (10), is enclosed around its sides by the potting compound (10) in an adhesive manner and has better adhesion to the potting compound (10) than does the semiconductor light source.

Abstract: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.

Abstract: A composite substrate (1) comprising a substrate body (2) and a utility layer (31) fixed on the substrate body (2). A planarization layer (4) is arranged between the utility layer (31) and the substrate body (2). A method for producing a composite substrate (1) applies a planarization layer (4) on a provided utility substrate (3). The utility substrate (3) is fixed on a substrate body (2) for the composite substrate (1). The utility substrate (3) is subsequently separated, wherein a utility layer (31) of the utility substrate (3) remains for the composite substrate (1) on the substrate body (2).

Abstract: A light emitting device includes: an active layer including a multi-quantum well having a well layer and a barrier layer, the active layer including a non-emitting region and an emitting region formed around the non-emitting region; a first cladding layer provided on a first major surface of the active layer; a pad electrode provided above the first cladding layer so that its center is located near a center of the non-emitting region as viewed in a direction perpendicular to the first major surface; and a second cladding layer provided below a second major surface of the active layer opposite to the first major surface. A bandgap of the well layer in the non-emitting region is wider than a bandgap of the well layer in the emitting region and narrower than a bandgap of the first cladding layer.

Abstract: A nitride semiconductor light emitting device includes n-type and p-type nitride semiconductor layers, and an active layer disposed between the n-type and p-type nitride semiconductor layers and having a stack structure in which a plurality of quantum barrier layers and one or more quantum well layers are alternately stacked. A net polarization of the quantum barrier layer is smaller than or equal to a net polarization of the quantum well layer. A nitride semiconductor light emitting device can be provided, which can realize high efficiency even at high currents by minimizing the net polarization mismatch between the quantum barrier layer and the quantum well layer. Also, a high-efficiency nitride semiconductor light emitting device can be achieved by reducing the degree of energy-level bending of the quantum well layer.

Abstract: An optoelectronic semiconductor component includes an active layer that emits radiation, the active layer surrounded by cladding layers, wherein the cladding layers and/or the active layer include(s) an indium-containing phosphide compound semiconductor material and the phosphide compound semiconductor material contains at least one of elements Bi or Sb as an additional element of main group V.

Abstract: A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage.

Abstract: A first first-conductivity-type diffusion layer, a first second-conductivity-type diffusion layer, a second first-conductivity-type diffusion layer, and a second second-conductivity-type diffusion layer are arranged in this order. In a region where the second second-conductivity-type diffusion layer and the first-conductivity-type layer are in contact with each other, impurity concentrations thereof are higher in a part in contact with a side face of the second second-conductivity-type diffusion layer than in a part at a bottom surface of the second second-conductivity-type diffusion layer.

Abstract: A compound semiconductor device including: a substrate; an electron transit layer formed on and above the substrate; and an electron supply layer formed on and above the electron transit layer, wherein a first region or regions having a smaller thermal expansion coefficient than the electron transit layer and a second region or regions having a larger thermal expansion coefficient than the electron transit layer are mixedly present on a surface of the substrate.

Abstract: A barrier-type photo-detector is provided with a Barrier between first and second layers. One of the layers is delineated into pixels without fully removing the non-pixel portions of the delineated layer. Delineation may be accomplished through material modification techniques such as ion damage, selective doping, ion induced disordering or layer material growth. Some variations may employ partial material removal techniques.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Abstract: A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided. It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises: an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; and a gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.

Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.

Abstract: This thin-film transistor includes a drain electrode film and a source electrode film, each of which includes a composite copper alloy film including a copper alloy underlayer that is formed so as to come into contact with a barrier film and a Cu layer that is formed on the copper alloy underlayer. One aspect of the copper alloy underlayer includes a concentrated layer including 2 mol % to 30 mol % of Ca, 20 mol % to 50 mol % of oxygen, and Cu and inevitable impurities as the balance. Another aspect of the copper alloy underlayer includes a concentrated layer including 2 mol % to 30 mol % of Ca, 1 mol % to 10 mol % in total of one or more selected from the group consisting of Al, Sn, and Sb, 20 mol % to 50 mol % of oxygen, and Cu and inevitable impurities as the balance.

Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

Abstract: Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract: The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.

Abstract: Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A semiconductor device with a novel structure is provided, which can hold stored data even when no power is supplied and which has no limitations on the number of writing operations. A semiconductor device is formed using a material which enables off-state current of a transistor to be reduced significantly; e.g., an oxide semiconductor material which is a wide-gap semiconductor. With use of a semiconductor material which enables off-state current of a transistor to be reduced significantly, the semiconductor device can hold data for a long period. In a semiconductor device with a memory cell array, parasitic capacitances generated in the nodes of the first to the m-th memory cells connected in series are substantially equal, whereby the semiconductor device can operate stably.

Abstract: A capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the first metal plate. A portion of the first metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A second metal plate is disposed on and conformal with the second dielectric layer. A portion of the second metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A third dielectric layer is disposed above the first metal plate, the second dielectric layer, and the second metal plate, and disposed between the first metal plate and the second dielectric layer and between the second metal plate and the second dielectric layer.

Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.

Abstract: A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors.

Abstract: A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.

Abstract: A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.