Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract: The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along a first direction. The semiconductor modules are grouped into upper arm semiconductor modules and lower arm semiconductor modules each connected to a corresponding one of the upper arm semiconductor module. Upper arm terminal rows as the terminal rows of the upper arm semiconductor modules and lower arm terminal rows as the terminal rows of the lower arm semiconductor modules are arranged in a staggered manner along a second direction perpendicular to the first direction and to a third direction in which the signal terminals of the semiconductor modules project, the first, second and third directions being perpendicular to one another.

Abstract: A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract: A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating.

Abstract: A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors.

Abstract: A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible.

Abstract: A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.

Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.

Abstract: Metal-insulator metal (MIM) capacitors are formed by providing a substrate having a first surface, forming thereon a first electrode having conductive and insulating regions wherein the conductive regions desirably have an area density DA less than 100%. A first dielectric is formed over the first electrode. A cavity is formed in the first dielectric, having a sidewall extending to the first electrode and exposing thereon some of the first electrode conductive and insulating regions. An electrically conductive barrier layer is formed covering the sidewall and the some of the first electrode conductive and insulating regions. A capacitor dielectric layer is formed in the cavity covering the barrier layer. A counter electrode is formed in the cavity covering the capacitor dielectric layer. External connections are formed to a portion of the first electrode laterally outside the cavity and to the counter electrode within the cavity.

Abstract: To provide a semiconductor device including a capacitor which includes a cylindrical or columnar lower electrode, a support film in contact with the upper portion of the lower electrode for supporting the lower electrode, a dielectric film covering the lower electrode and the support film, and an upper electrode facing the lower electrode with the dielectric film interposed therebetween, wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode, and thereby the mechanical strength of the support film is increased.

Abstract: The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.

Abstract: Embodiments of the present invention provide a component-built-in wiring board capable of preventing a defect, such as a crack, resulting from stress concentration at a corner, when a component is accommodated in a housing portion of a core material with resin filler filled therebetween. The component-built-in wiring board can include a component accommodated in the housing portion of a core material, and a laminate portion in which insulating layers and conductor layers are laminated alternately on the core material. A gap between the housing portion of the core material and the component can be filled with a resin filler. In an inner circumferential portion of the housing portion of the core material a first straight chamfered portion is formed at each corner of a rectangle, and in an outer circumferential portion of the component a second straight chamfered portion is formed at each corner of a rectangle.

Abstract: A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

Abstract: A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.

Abstract: A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier.

Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Abstract: An epitaxial structure is provided. The epitaxial structure includes an epitaxial layer and a graphene layer. The epitaxial layer has a patterned surface. The graphene layer is located on the patterned surface of the epitaxial layer. The patterned graphene layers are a continuous structure defining the plurality of apertures. The sizes of the apertures are in a range from about 10 nanometers to about 120 micrometers. The dutyfactor of the graphene layer is in a range from about 1:4 to about 4:1.

Abstract: An epitaxial structure includes a patterned epitaxial growth surface defining a plurality of grooves. A graphene layer covers the patterned epitaxial growth surface. An epitaxial layer is formed on the patterned epitaxial growth surface, wherein a first part of the graphene layer is sandwiched between the substrate, and a second part of the graphene layer is embedded into the epitaxial layer.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract: A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer.

Abstract: The invention provides a substrate treating method which can favorably prevent damages to a substrate when the substrate is separated from a support, thus achieving a high yield. The substrate treating method includes, in the sequence set forth, a step 1 of temporarily fixing a substrate onto a support via a temporary fixing material to form a stack, the temporary fixing material including at least a temporary fixing material (I) containing a cycloolefin polymer (A) and a compound (B) having a structure (b1) such as a dialkyl silicone structure, and a structure (b2) such as a polyoxyalkylene structure, a step 2 of processing the substrate and/or transporting the stack, and a step 3 of applying a force to the substrate or the support in a direction substantially perpendicular to the plane of substrate to separate the substrate from the support.

Abstract: Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.

Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.

Abstract: A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.

Abstract: A semiconductor device has a heat dissipating base; a patterned insulating substrate attached to the heat dissipating base with a solder therebetween; a semiconductor chip attached to a conductive pattern of the patterned insulating substrate with a solder therebetween; a first conductor attached to the semiconductor chip with a solder therebetween; a resin case attached to the heat dissipating base with an adhesive; and a second conductor attached to the first conductor by laser welding. The second conductor formed by rolling has stripe-shaped rolling traces formed on a surface thereof in a rolling direction and is disposed on the first conductor such that the rolling traces are arranged in a same direction.

Abstract: A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant.

Abstract: A support structure includes a support cell with a support substrate, junction sacrificial portions surrounding the support substrate, and pin blocks extending from the junction sacrificial portion toward the support substrate. A semiconductor chip is mounted to the support substrate and electrically wire bonded to the pin blocks. An encapsulating body covers the chip, with the pin blocks extending from the body. A transversal groove is formed in each pin block. Surfaces of the pin block and groove are electroplated with solder material. Each pin block is sectioned at the groove to define a pin having a first end corresponding to a portion of the groove surface of the groove and a second end corresponding to the sectioned portion of the pin block that is not electroplated with solder material. Sectioning causes the separation of the chip-insulating body assembly from the junction sacrificial portions.

Abstract: A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire.

Abstract: A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

Abstract: An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink.

Abstract: A power device includes a chip of semiconductor material and a further chip of semiconductor material on each of which at least one power transistor is integrated; each chip comprises a first conduction terminal on a first surface, and a second conduction terminal and a control terminal on a second surface opposite the first surface, and an insulating body embedding said chip and said further chip. In the solution according to one or more embodiments of the present disclosure, the first surface of said chip faces the second surface of said further chip, and the power device further comprises a first heat-sink arranged between said chip and said further chip and electrically coupled with the first conduction terminal of said chip and with the second conduction terminal of said further chip, the control terminal of said further chip being electrically insulated from the first heat-sink.

Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.

Abstract: Disclosed herein is a semiconductor package module, including: a circuit board having connection pads formed on one surface thereof; a semiconductor package including lead terminals protruded out of a housing; and an interposer positioned between the circuit board and the semiconductor package, the interposer including a body allowing the circuit board and the semiconductor package to be spaced apart from each other and elastic members contacted with the connection pads and the lead terminals.

Abstract: At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die.

Abstract: A power module includes a substrate having an electrically insulative member with opposing first and second metallized sides and one or more semiconductor die attached to the first metallized side of the substrate. A plurality of thermally conductive structures are laterally spaced apart from one another and individually attached directly to the second metallized side of the substrate so that the plurality of thermally conductive structures extend outward from the second metallized side.

Abstract: A semiconductor device includes: a first heat spreader; a second heat spreader separated from the first heat spreader; a first semiconductor element on the first heat spreader and having a back face jointed to the first heat spreader; a second semiconductor element on the second heat spreader and having a back face jointed to the second heat spreader; a resin coating the first and second heat spreaders and the first and second semiconductor elements; and a reinforcing member provided across a region between the first and second heat spreaders in the resin, and having rigidity higher than rigidity of the resin.

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

Abstract: An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate.

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

Abstract: A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a number of second bonding pads, and each second bonding pad corresponds to a respective first bonding pad. The two soldering balls of each first bonding pad are electrically connected to a corresponding second bonding pad via two bonding wires, and the bonding wires are bonded to the second corresponding bonding pad by a wedge bonding manner.