Patents Issued in October 31, 2013
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Publication number: 20130285690Abstract: A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include a main body and a plurality of mounting points, wherein at least one of the mounting points is flexibly connected to the main body by one or more laterally extending beams that has a section modulus normal to the lateral direction significantly greater than in the lateral direction. The stiffener assembly allows for differential thermal expansion of various components of the microelectronic contactor assembly while minimizing accompanying dimensional distortion that could interfere with contacting the terminals of semiconductor devices.Type: ApplicationFiled: January 18, 2011Publication date: October 31, 2013Applicant: Advantest (Singapore) Pte LtdInventor: John Andberg
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Publication number: 20130285691Abstract: A high-frequency test probe device comprising a contact section (18) which forms an inner contact (40) and an outer contact (44), which is designed to interact with a contact partner (30) that is to be contacted for testing purposes, and which is provided on an inner housing (16) at one end and can be contacted at a pickup end (20) for signal pickup at the other end. The inner housing is guided at least along some sections in an outer housing (10) and in an axially movable manner relative to same.Type: ApplicationFiled: January 18, 2012Publication date: October 31, 2013Applicant: Ingun Pruefmittelbau GMBHInventor: Peter Breul
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Publication number: 20130285692Abstract: The test socket includes: an elastic conductive sheet including a conductive portion and an insulating supporting portion; a sheet type connector including an electrode portion that is disposed on the conductive portion and is formed of a metal, and a sheet member that supports the electrode portion, wherein the sheet member comprises a cut portion formed by cutting at least a portion of the sheet member between adjacent electrode portions; and an electrode supporting portion including an upper supporting portion that contacts an upper edge of the electrode portion to support the electrode portion and exposes an upper center portion of the electrode portion to be open and an electrode supporting portion including a connection supporting portion that connects the upper supporting portion and the insulating supporting portion.Type: ApplicationFiled: April 29, 2013Publication date: October 31, 2013Applicant: ISC CO., LTD.Inventor: Jae Hak Lee
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Publication number: 20130285693Abstract: A detecting method of abnormality of a differential signal receiving terminal of a liquid crystal displaying module, including: inputting high level signals to LVDS0+, LVDS0?, LVDS1+, LVDS? in order, in which only one high level signal is inputted to one of the differential signal lines and the other differential signal lines are kept in high impedance states simultaneously; and receiving feedback signals from all the differential signal lines and determining whether the differential signal lines of detecting units are abnormal or not according to the received feedback signals. The abnormality of the differential signal lines includes terminal resistive opens of the differential signal lines, a short circuit between two adjacent groups of differential signal lines, and short circuits of the differential signal lines to ground or to a power supply caused by abnormal power supplying sequence.Type: ApplicationFiled: May 25, 2012Publication date: October 31, 2013Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTDInventors: Xiaoping Tan, Nianmao Wang
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Publication number: 20130285694Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
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Publication number: 20130285695Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.Type: ApplicationFiled: July 1, 2013Publication date: October 31, 2013Inventors: Gaurav Verma, Tony P. Chiang, Imran Hashim, Sandra G. Malhotra, Prashant B. Phatak, Kurt H. Weiner
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Publication number: 20130285696Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Lew Chua-Eoan, Boris Andreev, Yuancheng Christopher Pan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
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Publication number: 20130285697Abstract: An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule.Type: ApplicationFiled: April 17, 2013Publication date: October 31, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yoshiyuki Kurokawa
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Publication number: 20130285698Abstract: A semiconductor device including a PLD which can increase the execution speed of an application with low power consumption is provided. The semiconductor device includes a programmable logic device and a processor which is not dynamically reconfigured. A memory element of the programmable logic device stores a plurality of pieces of configuration data determined to have high frequency of use by a memory module among configuration data corresponding to a thread. The memory element includes a storage element and a switch in each of a plurality of memory cells. The switch is used for supplying charge whose amount is determined by the plurality of pieces of stored configuration data to the storage element, retaining the charge in the storage element, and discharging the charge from the storage element.Type: ApplicationFiled: April 29, 2013Publication date: October 31, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Takahiro Fukutome
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Publication number: 20130285699Abstract: A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state; a plurality of logic elements forming a logic block; and a programming circuit for turning the CeRAM switching elements OFF and ON to connect the logic elements to form the FPGA.Type: ApplicationFiled: April 26, 2013Publication date: October 31, 2013Applicant: SYMETRIX CORPORATIONInventors: Christopher Randolph McWilliams, Carlos A. Paz de Araujo, Jolanta Celinska
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Publication number: 20130285700Abstract: A non-volatile logic operation device includes an operation unit that is connected to a first input terminal, a second input terminal, and an output terminal, includes an operation layer, a first non-magnetic layer, and a reference layer, and outputs from the output terminal a result of a logic operation on signals applied at the first input terminal and the second input terminal, and a control unit that is connected to a third input terminal, and includes a control layer. The control unit is arranged in the vicinity of the operation unit.Type: ApplicationFiled: January 5, 2012Publication date: October 31, 2013Inventors: Shunsuke Fukami, Nobuyuki Ishiwata
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Publication number: 20130285701Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.Type: ApplicationFiled: May 9, 2013Publication date: October 31, 2013Inventor: Lee D. Whetsel
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Publication number: 20130285702Abstract: A multipoint low-voltage differential signaling (mLVDS)receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated.Type: ApplicationFiled: July 1, 2013Publication date: October 31, 2013Applicant: MAGNACHIP SEMICONDUCTOR LTD.Inventor: Jung-hyun KIM
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Publication number: 20130285703Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Inventor: John Douglas McGinn
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Publication number: 20130285704Abstract: A bridge integrated circuit adapted for being coupled between a gate driver and a tester is provided. The bridge integrated circuit comprises a plurality of first detection units and a logic unit. Each first detection unit determines whether a corresponding gate driving signal satisfies a first standard according to one of the gate driving signals provided by the gate driver and accordingly generates a first detection signal according to the determination result. The logic unit is coupled to the first detection units and generates a test result signal in response to the first detection signal provided by each first detection unit. The test result signal is adapted for the tester.Type: ApplicationFiled: November 15, 2012Publication date: October 31, 2013Applicant: NOVATEK MICROELECTRONICS CORP.Inventor: Chiu-Huang Huang
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Publication number: 20130285705Abstract: A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Mohammad Nizam U. Kabir, Douglas A. Garrity, Rakesh Shiwale
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Publication number: 20130285706Abstract: An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes.Type: ApplicationFiled: January 31, 2013Publication date: October 31, 2013Applicant: FUJITSU LIMITEDInventor: Yoshiyasu DOI
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Publication number: 20130285707Abstract: Apparatus for a wireless tachometer receiver. The wireless tachometer receiver includes a receiver and a signal conditioner that drives a conventional tachometer. Conventional tachometers require an input consisting of pulses at the operating voltage of the vehicle, which is typically 12 Vdc. Conventional receivers have an alternating current output that is substantially less than the operating voltage of the vehicle, which is insufficient to trigger the tachometer reliably. The signal conditioner converts the receiver output to a signal that allows for reliable operation of the conventional tachometer. In one embodiment, the signal conditioner is an amplifier that has a gain to drive the amplifier output between zero and the operating voltage of the vehicle. In another embodiment, the signal conditioner is a step-up transformer that has a ratio sufficient to produce an output at the operating voltage of the vehicle.Type: ApplicationFiled: April 29, 2013Publication date: October 31, 2013Inventor: Terry Pennisi
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Publication number: 20130285708Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Applicant: STMicroelectronics International N.V.Inventor: Vinod KUMAR
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Publication number: 20130285709Abstract: A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.Type: ApplicationFiled: July 12, 2012Publication date: October 31, 2013Inventors: Sang-Mook OH, Tae-Sik YUN
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Publication number: 20130285710Abstract: The present document discloses a driver circuit for the high side switch of a half bridge at ultra-high voltage. The half bridge comprises the high side switch coupled to an input voltage Vin and to a midpoint of a low side switch. The driver circuit comprises a control signal generation unit generating a stream of control pulses and a control logic generating a gate voltage for the high side switch using a supply voltage Vcc based on the control pulses, a supply voltage capacitor generating the supply voltage Vcc, and a decoupling capacitor coupled on a first side to the control signal generation unit and on a second side to the control logic, to the midpoint of the half bridge via a first charging switch, and to the supply voltage capacitor via a second charging switch.Type: ApplicationFiled: July 30, 2012Publication date: October 31, 2013Applicant: DIALOG SEMICONDUCTOR GMBHInventor: Horst Knoedgen
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Publication number: 20130285711Abstract: To achieve low power consumption of a semiconductor device including a plurality of function blocks capable of being in either an operating state or a not-operating state, by effective use of electric charge discharged from a not-operating function block. In a semiconductor device including a plurality of function blocks, a capacitor is electrically connected to the plurality of function blocks so that electric charge discharged from a not-operating function block is accumulated in the capacitor. Then, the electric charge accumulated in the capacitor is supplied to a function block to be in an operating state, and then power is supplied from a power source to the function block.Type: ApplicationFiled: April 23, 2013Publication date: October 31, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hiroyuki Miyake
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Publication number: 20130285712Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.Type: ApplicationFiled: April 26, 2013Publication date: October 31, 2013Inventors: Peter Kanschat, Andre Arens, Hartmut Jasberg, Ulrich Michael Georg Schwarzer
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Publication number: 20130285713Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.Type: ApplicationFiled: October 26, 2012Publication date: October 31, 2013Inventor: NXP B.V.
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Publication number: 20130285714Abstract: A center frequency F0 of an IF filter is effectively adjusted. The IF filter filters a down-converted signal centering around the center frequency F0. A pseudo sine wave generation circuit generates a pseudo sine wave having a level change of at least two steps respectively on both positive and negative sides. The pseudo sine wave is made to pass through the IF filter by a switch circuit, and in the state, an F0 adjustment circuit adjusts the center frequency F0 in the IF filter 14 by comparing a phase of the pseudo sine wave with a phase of a signal after passing through the IF filter.Type: ApplicationFiled: April 23, 2013Publication date: October 31, 2013Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tomoya Kanzawa, Shinji Kurihara, Katu Horikoshi
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Publication number: 20130285715Abstract: A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.Type: ApplicationFiled: May 29, 2012Publication date: October 31, 2013Applicant: Southeast UniversityInventors: Jianhui Wu, Xiao Shi, Chao Chen, Zhilin Liu, Qiang Zhao, Junfeng Wen, Xudong Wang, Chunfeng Bai, Qian Tian
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Publication number: 20130285716Abstract: A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal.Type: ApplicationFiled: May 30, 2012Publication date: October 31, 2013Inventor: Richard T. Dickens
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Publication number: 20130285717Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Ping Xiao, Weiyding Ding, Leo Min Maung
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Publication number: 20130285718Abstract: A semiconductor apparatus includes a control unit configured to generate a first pumping enable signal and a second pumping enable signal which are alternately enabled, in response to an active signal; a first pumping voltage generation unit configured to perform a pumping operation during an enable period of the first pumping enable signal and generate a first pumping voltage; and a second pumping voltage generation unit configured to perform a pumping operation during an enable period of the second pumping enable signal and generate a second pumping voltage.Type: ApplicationFiled: September 5, 2012Publication date: October 31, 2013Applicant: SK HYNIX INC.Inventor: Jong Hwan KIM
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Publication number: 20130285719Abstract: A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal.Type: ApplicationFiled: May 30, 2012Publication date: October 31, 2013Inventors: Anthony J. Ranson, Adriano McAvoy
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Publication number: 20130285720Abstract: A signal processing device to utilize multiple channel phase detection includes a first phase detector for a first Phase Locked Loop (PLL) of a first channel, the first phase detector to generate phase error information from an input of the first channel. The device also includes a second phase detector of a second PLL of a second channel, the second phase detector to generate phase error information from an input of the second channel. Both the first PLL and the second PLL are to receive phase error information from both the first phase detector and the second phase detector.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Inventor: Rafel Jibry
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Publication number: 20130285721Abstract: Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Inventor: Heiko KOERNER
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Publication number: 20130285722Abstract: A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.Type: ApplicationFiled: August 8, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Mao-Hsuan CHOU
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Publication number: 20130285723Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.Type: ApplicationFiled: April 22, 2013Publication date: October 31, 2013Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Global Unichip Corp.Inventor: Chun-Chi CHANG
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Publication number: 20130285724Abstract: A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Inventors: Robert Bogdan Staszewski, Chi-Hsueh Wang
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Publication number: 20130285725Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: John Henry Bui, Lay Hock Khoo, Khai Nguyen, Chiakang Sung, Ket Chiew Sia
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Publication number: 20130285726Abstract: In some embodiments, a differential amplifier with duty cycle correction is provided.Type: ApplicationFiled: December 30, 2011Publication date: October 31, 2013Inventors: Eduard Roytman, Mahalingam Nagarajan, Pradeep R. Vempada
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Publication number: 20130285727Abstract: The present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges.Type: ApplicationFiled: January 31, 2013Publication date: October 31, 2013Inventors: Andrew Pickering, Vipul Raithatha, Peter Hunt
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Publication number: 20130285728Abstract: A pulse generator comprising: an input for receiving a trigger; an output node for outputting a signal; a delay line comprising one or more delay units and a plurality of taps; one or more pull-up devices each connected to the output node for increasing the output voltage on the output node; and/or one or more pull-down devices each connected to the output node for decreasing the output voltage on the output node; wherein the taps of the delay line are operably connected to the pull-up and/or pull-down devices such that a trigger passing along the delay line activates one or more of the pull-up and/or one or more of the pull-down devices more than once. Re-use of the pull-up and/or pull-down devices enables longer and more complex pulse shapes, such as high-order Gaussian pulse shapes to be produced while keeping the number of components low, thus reducing chip area, power requirements and parasitic capacitance.Type: ApplicationFiled: September 20, 2011Publication date: October 31, 2013Applicant: NOVELDA ASInventors: Kristian Granhaug, Hakon Andre Hjortland
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Publication number: 20130285729Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.Type: ApplicationFiled: September 9, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Xiuqiang Xu, Jie Jin, Yizhong Zhang
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Publication number: 20130285730Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.Type: ApplicationFiled: March 15, 2013Publication date: October 31, 2013Applicant: Fairchild Semiconductor CorporationInventors: Lei Huang, Eric Li
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Publication number: 20130285731Abstract: Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventor: Thomas H. Friddell
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Publication number: 20130285732Abstract: Aspects of the invention include a constant current source that generates a constant current, apart from a constant current circuit, and a temperature detection zener diode (a temperature detection element). The input side of the constant current source can be connected to a power source. The output side of the constant current source can be connected to the anode of the temperature detection diode. The anode of the temperature detection zener diode can also be connected to one end of a resistor provided in the constant current circuit. Further, the cathode of the temperature detection zener diode can be connected to a GND. Further, the temperature detection zener diode can be incorporated in the same semiconductor substrate as a semiconductor substrate into which an IGBT is built.Type: ApplicationFiled: April 10, 2013Publication date: October 31, 2013Inventor: Takahiro MORI
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Publication number: 20130285733Abstract: A charging circuit includes a first current mirror for receiving an input voltage, a second current mirror including a first branch circuit and a second branch circuit for receiving the input voltage, a switch transistor coupled to the first current mirror and the first branch circuit for determining a conduction condition of the switch transistor according to a switch signal, a first resistor including a first resistance and one end coupled to the switch transistor, and a second resistor including a second resistance and one end coupled the second branch circuit of the second current mirror, wherein the first current mirror and the second current mirror perform a charging operation of a loading circuit according to the first resistance and the second resistance.Type: ApplicationFiled: April 30, 2013Publication date: October 31, 2013Applicant: Anpec Electronics CorporationInventors: Chih-Ning Chen, Yen-Ming Chen
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Publication number: 20130285734Abstract: A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ivan Carlos Ribeiro NASCIMENTO, Andre Luis VILAS BOAS
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Publication number: 20130285735Abstract: A control assembly adapted for automotive applications provides operator inputs and displays and includes a uniface ornamental escutcheon defining a central display area and a plurality of operator input devices at least partially circumscribing the display area. Each operator input device includes a faux control member integrally formed within the escutcheon and having beveled circumferential contours mimicking a discrete displacable control element. At least one substrate extends rearwardly from and closely conforms with a rear surface of the escutcheon, and is positioned to transect a plurality of adjacent faux control members. At least one capacitance sensor is associated with each faux control member and is carried on a forward facing edge of the substrate. As a result, each operator input device is touch sensitive to manual operator selection of input devices by touching the exposed face of the escutcheon to effect a desired switching function.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: DELPHI TECHNOLOGIES, INC.Inventors: Chris R. Snider, Bradley S. Coon
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Publication number: 20130285736Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to he operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Marc LOINAZ, Stefanos Sidiropoulos, Whay Sing Lee
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Publication number: 20130285737Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: Macronix International Co., Ltd.Inventors: Yung Feng Lin, Chun-Jen Huang, Tzeng-Huei Shiau, Chun-Hsiung Hung, Caiyun Wu, Qifang Wang
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Publication number: 20130285738Abstract: A charging circuit includes a first current mirror including a first branch circuit, a second branch circuit and a third branch circuit for generating a first conduction current, a second conduction current and a third conduction current according to the input voltage, a second current mirror including a fourth branch circuit coupled to the first branch circuit and including a first channel width, and a fifth branch circuit coupled to the second branch circuit and including a second channel width, wherein a load circuit is coupled between the first current mirror and the second current mirror, and the first current mirror as well as the second current mirror correspondingly adjust values of the first conduction current, the second conduction current and the third conduction current according to the first channel width as well as the second channel width, so as to process a charging operation of the load circuit.Type: ApplicationFiled: April 29, 2013Publication date: October 31, 2013Applicant: Anpec Electronics CorporationInventors: Chih-Ning Chen, Yen-Ming Chen
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Publication number: 20130285739Abstract: The present invention relates to technologies for integrated circuits and Large Area Integrated Circuits (LAICs), which are integrated circuits made from photo-repetition of one or several reticle image fields, stitched together on at least one lithographic process layer. It also relates to a specific class of LAIC that can connect to the contacts of other ICs placed on its surface, where specific contact detection algorithms means are disclosed.Type: ApplicationFiled: March 1, 2013Publication date: October 31, 2013Inventors: CORPORATION DE L ' ECOLE POLYTECHNIQUE DE MONTREAL, UNIVERSITÉ DU QUEBEC À MONTREAL