Abstract: A photovoltaic cell including a first semiconductor layer that includes a III-V compound semiconductor, the first semiconductor layer positioned over a transparent conductive layer, and a second semiconductor layer that includes a II-VI compound semiconductor, the second semiconductor layer positioned between the first semiconductor layer and a back metal contact. The photovoltaic cell further includes an interfacial layer between the first and second semiconductor layers that enhances a rectifying junction formed between the III-V and II-VI compound semiconductor materials.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

Abstract: A semiconductor device (100) includes a substrate (1) having a semiconductor layer (102); a trench (12) in the semiconductor layer (102); a gate insulating film (11) covering a periphery and an inner surface of the trench (12); a gate electrode (8) including a portion filling the trench (12) and a portion around the trench (12), and provided on the gate insulating film (11); an interlayer insulating film (13) on the gate electrode (8); and a hollow (50) above and around the trench (12), and between the gate electrode (8) and the gate insulating film (11). Above the trench (12), the hollow (50) protrudes inside the trench (12) from a plane extending from an upper surface of the gate insulating film (11) at a portion covering the side surface of the trench (12) with a flat shape.

Abstract: A method of manufacturing a semiconductor light emitting device having a multi-cell array, including: sequentially forming a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on a substrate; etching and removing portions of the second conductive semiconductor layer and the active layer so as to expose portions of an upper surface of the first conductive semiconductor layer corresponding to respective regions of the second conductive semiconductor layer spaced apart from one another; and separating light emitting cells by partially etching the exposed portions of the first conductive semiconductor layer, wherein the separating of the light emitting cells is not performed at an edge portion of the substrate.

Abstract: A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain elec

Abstract: A high-resolution, Active Matrix (AM) programmed monolithic Light Emitting Diode (LED) micro-array is fabricated using flip-chip technology. The fabrication process includes fabrications of an LED micro-array and an AM panel, and combining the resulting LED micro-array and AM panel using the flip-chip technology. The LED micro-array is grown and fabricated on a sapphire substrate and the AM panel can be fabricated using CMOS process. LED pixels in a same row share a common N-bus line that is connected to the ground of AM panel while p-electrodes of the LED pixels are electrically separated such that each p-electrode is independently connected to an output of drive circuits mounted on the AM panel. The LED micro-array is flip-chip bonded to the AM panel so that the AM panel controls the LED pixels individually and the LED pixels exhibit excellent emission uniformity. According to this constitution, incompatibility between the LED process and the CMOS process can be eliminated.

Abstract: To provide a method for fabricating a light-emitting device using flexible glass which is capable of withstanding a process temperature higher than or equal to 500° C., and the light-emitting device. A second substrate is attached to a support substrate using an adsorption layer. The second substrate is bonded to a backplane substrate provided with a transistor and a light-emitting element. The backplane substrate includes a separation layer and a buffer layer. A first substrate is separated from the backplane substrate by separation between the separation layer and the buffer layer. A flexible third substrate is bonded, using a second adhesive layer, to a surface of the buffer layer exposed by the separation. The support substrate is separated from the second substrate by separation between the second substrate and the adsorption layer.

Abstract: Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.

Abstract: A TFT array substrate includes a gate wiring for driving a pixel electrode constituting a pixel on an insulating substrate, a source wiring intersecting with the gate wiring through an insulating film, a source electrode connected to the source wiring, and a drain electrode provided opposite to the source electrode and connected to the pixel electrode. A semiconductor layer to be connected to the source electrode and the drain electrode is provided under the source electrode and the drain electrode. An end face of the semiconductor layer does not intersect with an end face of the source wiring, an end face of the source electrode and an end face of the drain electrode over the gate wiring, and a portion of the semiconductor layer which is positioned under the drain electrode has an end face to be included in the gate wiring as seen in a planar view.

Abstract: Exemplary embodiments of the present invention relate to a light emitting device including a first light emitting cell including a lower light emitting diode and an upper light emitting diode vertically stacked on a substrate and at least three electrodes arranged on the first light emitting cell. Each of the lower light emitting diode and the upper light emitting diode includes an active layer disposed between a lower semiconductor layer and an upper semiconductor layer, the lower semiconductor layer being disposed between the substrate and the upper semiconductor layer.

Abstract: A light emitting device, having: a first light emitting element and a second light emitting element; and a resin package equipped with an opening having a reflective wall that widens toward the upper face, the opening comprises at least first and second curved parts having different radiuses at the resin package upper face, and the radius of the first curved part disposed near the first light emitting element is greater than the radius of the second curved part disposed near the second light emitting element.

Abstract: Provided are a light emitting apparatus and a surface light source apparatus having the same. The light emitting apparatus comprises a package body, a first color light emitting part in a first cavity of the package body, and a second color light emitting part in a second cavity of the package body. The package body comprises a plurality of cavities.

Abstract: A mounting substrate includes: a wiring substrate; and a plurality of optical elements mounted on a mounting surface of the wiring substrate, and each having a first electrode and a second electrode. The wiring substrate includes a support substrate, a plurality of first wires, and a plurality of second wires. The first wires and the second wires are provided within a layer between the support substrate and the mounting surface. The first wires are electrically connected with the first electrodes. The second wires are electrically connected with the second electrodes, and each have cross-sectional area larger than cross-sectional area of each of the first wires.

Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.

Abstract: Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling.

Abstract: A light emitting diode includes a source layer, a metallic plasma generating layer, a first optical symmetric layer, a first electrode, and a second electrode. The source layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in series. The first semiconductor layer includes a first surface and a second surface opposite to the first surface. The first electrode covers and contacts the first surface. The second electrode is electrically connected with the second semiconductor layer. The metallic plasma generating layer is disposed on a surface of the source layer away from the first semiconductor layer. The first optical symmetric layer is disposed on a surface of the metallic plasma generating layer away from the first semiconductor layer. A refractive index difference between the source layer and the first optical symmetric layer is less than or equal to 0.3.

Abstract: A light emitting diode device includes a substrate, a light emitting diode chip, an optical lens and an adhesive interface layer. The light emitting diode chip is electrically connected with the substrate. The optical lens has an accommodation cavity to enclose the light emitting diode chip on the substrate, wherein the accommodation cavity includes a micro diffusion structure on an inner wall thereof. The adhesive interface layer is filled within the accommodation cavity of the optical lens.

Abstract: An opening is provided corresponding to an installation area of a semiconductor element in an insulating resin layer for a base material. A first insulating resin layer is provided on a part of one main surface of the insulating resin layer outside the opening to surround the opening. In addition, a second insulating resin layer coats in a continuous manner: the edge portion of the opening on the one main surface of the insulating resin layer; the end face of the opening passing through the insulating resin layer; and the edge portion of the opening on the other main surface of the insulating resin layer. The upper end portion of the end face of the second insulating resin layer in contact with the one main surface of the insulating resin layer protrudes toward the first insulating resin layer.

Abstract: A method for producing a sialon phosphor is provided. The method includes mixing a silicon precursor and an aluminum precursor and sintering the mixture to form a first sintered body. The first sintered body and a precursor for an active material are mixed and the mixture is heat-treated to form a second sintered body. That is, the exemplary method for producing a sialon phosphor involves firstly forming the first sintered body serving as a host material to stably ensure a crystal structure, and then mixing the active material and the first sintered body so as to preserve the role of the active material without sacrificing the crystal structure of the first sintered body.

Abstract: A method for manufacturing an LED (light emitting diode) is disclosed wherein a metal substrate is provided. A chip fastening area with a depression and two wire fixing areas on the first metal substrate are defined on the metal substrate. The chip fastening area and the wire fixing areas are separated by a plurality of first grooves. An LED chip is provided in the depression of the chip fastening area and electrically connected to the wire fixing areas by wires. An encapsulant is formed to cover and connect the chip fastening area and the wire fixing areas. Portions of the metal substrate except the chip fastening area and the wire fixing areas are removed.

Abstract: An LED device with improved LED efficiency is presented. An LED die is positioned within a pocket formed by a substrate and an opening in a supporting layer arranged thereon. The increase in the LED efficiency is achieved by providing a device where at least a portion of the pocket surface is reflective. This portion of the pocket surface is reflective because it is covered by either a reflective layer of foil or film, or a reflective coating, or it is polished.

Abstract: A method is provided for producing a radiation-emitting semiconductor chip, in which a first wavelength-converting layer is applied over the radiation exit face of a semiconductor body. The application method is selected from the following group: sedimentation, electrophoresis. In addition, a second wavelength-converting layer is applied over the radiation exit face of the semiconductor body. The second wavelength-converting layer is either produced in a separate method step and then applied or the application method is sedimentation, electrophoresis or printing. Furthermore, a radiation-emitting semiconductor chip and a radiation-emitting component are provided.

Abstract: The invention relates to an illumination system comprising 1) a light source arranged to emit primary radiation, 2) a radiation converting element arranged to convert at least part of the primary radiation into secondary radiation, and 3) a filter arranged to block radiation generated in the illumination system having a wavelength shorter than a certain cut-off wavelength. According to the invention, the filter is designed to block a part of the secondary radiation by having arranged the cut-off wavelength of the filter in the emission spectrum of the radiation converting element. Illumination devices according to this design show emission spectra with small bandwidth.

Abstract: LED dies are mounted a single submount tile (or wafer). The LED dies have a light emitting top surface. A uniformly thick layer of UV sensitive silicone infused with phosphor is then deposited over the tile, including over the tops and sides of the LED dies. Only the silicone/phosphor over the top and sides of the LED dies is desired, so the silicone/phosphor directly on the tile needs to be removed. The silicone/phosphor layer is then masked to expose the areas that are to remain to UV light, which creates a cross-linked silicone. The unexposed silicone/phosphor layer is then dissolved with a solvent and removed from the tile surface. The silicone/phosphor layer may be defined to expose a wire bond electrode on the LED dies. The tile is ultimately singulated to produce individual phosphor-converted LEDs.

Abstract: Provided are curable resin compositions capable of giving cured articles that have high light reflectivity, are satisfactorily resistant to heat and light, are tough, and less suffer from light reflectivity reduction with time. A curable resin composition for light reflection includes an alicyclic epoxy compound (A), rubber particles (B), a white pigment (C), a curing agent (D), and a curing accelerator (E). Another curable resin composition for light reflection includes an alicyclic epoxy compound (A), rubber particles (B), a white pigment (C), and a curing catalyst (F).

Abstract: Disclosed are a light emitting device package and a lighting system. The light emitting device package includes a body including a cavity and formed in a transmittive material; a plurality of lead electrodes in the cavity; an isolation member disposed between the lead electrodes; a light emitting device electrically connected to the lead electrodes in the cavity; and a molding member on the light emitting device.

Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.

Abstract: Provided is a package of a light emitting diode. The package according to an embodiment includes a package of a light emitting diode, the package comprising: a base layer including an entire top surface that is substantially flat; a light emitting diode chip on the base layer; a lead frame electrically connected to the light emitting diode chip; and a reflective coating layer comprising titanium oxide, wherein a top surface of the reflective coating layer is substantially parallel to a top surface of the base layer, and wherein ends of the reflective coating layer and base layer are aligned with each other.

Abstract: A phosphor for light emitting device of an embodiment includes: a phosphor particle composed of at least one selected from an alkaline earth silicate phosphor, a lanthanum oxysulfide phosphor, and a zinc sulfide phosphor; and a surface treatment agent, provided to cover a surface of the phosphor particle, of at least one selected from a silane coupling agent and an acrylic emulsion. A luminance maintenance ratio of the phosphor represented by a formula: luminance B/luminance A×100(%) , is 98% or more, wherein the luminance A is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40%, and the luminance B is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40% after leaving the phosphor under a condition of temperature: 60° C., humidity: 90% for 12 hours.

Abstract: A device includes: a substrate; and a functional element mounted, the functional element including electrodes. The substrate includes a support substrate, and includes a first seed metal, a second seed metal, and a resin component on the support substrate, the first seed metal being disposed in a section opposed to part or all of a first electrode among the electrodes, and being connected to the first electrode by plating, the second seed metal being disposed in a section opposed to part or all of a second electrode among the electrodes, and being connected to the second electrode by plating, and the resin component being disposed in a layer between the functional element and the support substrate, and fixing the functional element to the support substrate, and being provided avoiding a neighborhood of an end of the functional element among opposed side sections of the first and second seed metals.

Abstract: A molded package, comprising: a molded resin having a recess for accommodating a light emitting element; a ceramic substrate disposed in a bottom of the recess, the ceramic substrate having one surface exposed from the bottom of the recess and the other surface exposed from a rear surface of the molded resin; and a lead disposed at a lower part of the molded resin, the light emitting element being mounted on the one surface of the ceramic substrate, the lead being in contact with at least one side surface of the ceramic substrate to hold the ceramic substrate.

Abstract: A light-emitting device in one embodiment comprises a lead frame, an adhesive, and a light-emitting element. The lead frame comprises two conductive members. The two conductive members are separated by a gap. Each conductive member comprises an upper surface and a lower surface. The upper surface and the lower surface are opposite to each other. The adhesive fills the gap and partially covers the upper and lower surfaces of each conductive member. The light-emitting element is disposed on the upper surface of one conductive member. The light-emitting element electrically connects the two conductive members.

Abstract: A light emitting device that includes a substrate, a light emitting element and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions and a groove portion between the plurality of wiring portions. The flexible base extends in a first direction corresponding to a longitudinal direction of the substrate and the plurality of wiring portions are arranged on the base. The light emitting element is disposed on the substrate and electrically connected to the plurality of wiring portions. The sealing resin member seals the light emitting element and a part of the substrate. The sealing resin member is spaced apart from a first groove portion of the groove portion, the first groove portion extending in a second direction intersecting the first direction.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: Disclosed is a light emitting device package. The light emitting device package includes a substrate comprising a recess, a light emitting chip on the substrate and a first conductive layer electrically connected to the light emitting chip. And the first conductive layer includes at least one metal layer electrically connected to the light emitting chip on an outer circumference of the substrate.

Abstract: A composition includes an organopolysiloxane component (A) comprising at least one of a disiloxane, a trisiloxane, and a tetrasiloxane, and has an average of at least two alkenyl groups per molecule. The composition further includes an organohydrogensiloxane component (B) having an average of at least two silicon-bonded hydrogen atoms per molecule. Components (A) and (B) each independently have at least one of an alkyl group and an aryl group and each independently have a number average molecular weight less than or equal to 1500 (g/mole). The composition yet further includes a catalytic amount of a hydrosilylation catalyst component (C), and titanium dioxide (TiO2) nanoparticles (D). The composition has a molar ratio of alkyl groups to aryl groups ranging from 1:0.25 to 1:3.0. A product of the present invention is the reaction product of the composition, which may be used to make a light emitting diode.

Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.

Abstract: semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.

Abstract: There is provided a linear sensor including a plurality of sensor elements that are disposed in line, each including a light sensing part that senses light, generates an electric charge according to an amount of the sensed light, and accumulates the electric charge, a readout gate used to read out the electric charge accumulated in the light sensing part, and a reset gate used to discharge the electric charge accumulated in the light sensing part so as to be reset, wherein a region having a highest concentration of an impurity included in the light sensing part is formed in a position similarly away from the readout gate and the reset gate in the light sensing part.

Abstract: A semiconductor device includes field regions formed in a substrate, and n-type impurity regions disposed between the field regions. At least one of the side surfaces of the field regions has a {100}, {310}, or {311} plane.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.

Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.

Abstract: A CMOS image sensor includes a substrate, a gate electrode formed over the substrate, a photodiode formed over the substrate to be substantially aligned with one side of the gate electrode, a floating diffusion region formed over the substrate to be substantially aligned with the other side of the gate electrode, and a blooming pass region formed below the photodiode.

Abstract: A CMOS image sensor includes a substrate, a punch-through prevention layer formed over the substrate, an epitaxial layer formed over the punch-through prevention layer, a gate electrode formed over the epitaxial layer; a photodiode formed in the epitaxial layer to be substantially aligned with one side of the gate electrode, a floating diffusion region formed in the epitaxial layer to be substantially aligned with the other side of the gate electrode, and an extended photodiode region formed below the photodiode to be coupled with the punch-through prevention layer.

Abstract: A metal-semiconductor-compound thin film is disclosed, which is formed between a semiconductor layer and a polycrystalline semiconductor layer, the metal-semiconductor-compound thin film having a thickness of about 2˜5 nm, so as to improve a contact between the semiconductor layer and the polycrystalline semiconductor layer. A DRAM storage cell is also disclosed. A metal-semiconductor-compound thin film having a thickness of about 2-5 nm is added between a drain region of a MOS transistor and a polycrystalline semiconductor buffer layer in the DRAM storage cell, so as to enhance read/write speed of the transistor of the DRAM storage cell while preventing excessive increase in leakage current between the drain region and a semiconductor substrate. A method for making a DRAM storage cell is also disclosed.

Abstract: A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.