Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.

Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.

Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor body and a source metallization which is arranged on the semiconductor body. The semiconductor body includes in a cross-section a drift region of a first conductivity type, a first body region of a second conductivity type which adjoins the drift region, a first compensation region of the second conductivity type which adjoins the first body region, has a lower maximum doping concentration than the first body region and forms a first pn-junction with the drift region, and a first charge trap. The first charge trap adjoins the first compensation region and includes a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate. The source metallization is arranged in resistive electric connection with the first body region. Further, a method for producing a semiconductor device is provided.

Abstract: A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.

Abstract: A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.

Abstract: A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.

Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.

Abstract: An embodiment of a vertical-gate transistor disposed on a die includes a first substrate portion of a first conductivity and a second substrate portion of a second conductivity. The die includes front and rear surfaces, the first portion extending from the front surface and the second portion extending from the rear surface to the first portion, at least one drain region of the second conductivity extending from the rear surface, and at least one cell. Each cell includes a source region of the second conductivity extending from the front surface, a conductive gate region extending from the front surface to a gate depth, a conductive field-plate region extending from the front surface to a field depth, a gate-insulating layer that insulates the gate region, and a plate-insulating layer that insulates the field-plate region. An intermediate insulating layer insulates the gate region from the field-plate region.

Abstract: A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.

Abstract: A MOS transistor comprises a substrate of a first conductivity, a first region of the first conductivity formed over the substrate, a second region of the first conductivity formed in the first region, a first drain/source region of a second conductivity formed in the second region, a second drain/source region of the second conductivity and a body contact region of the first conductivity, wherein the body contact region and the first drain/source region are formed in an alternating manner from a top view.

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate, a gate formed on the substrate, a source region and a drain region formed in the substrate at respective sides of the gate, and a first isolation structure formed under the gate. The first isolation structure is overlapped by the entire gate.

Abstract: A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface.

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract: A semiconductor device includes: a semiconductor substrate having a hexagonal crystalline structure with a c-axis and c-planes; and transistors on a c plane of the semiconductor substrate. Source electrodes of the transistors are connected to each other. Drain electrodes of the transistors are connected to each other. Gate electrodes of the transistors are connected to each other. The gate electrodes of the transistors extend along directions that form angles with each other that are 60 degrees or 120 degrees, in a plan view seen from a direction perpendicular to the c plane of the semiconductor substrate.

Abstract: A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer.

Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Abstract: Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.

Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.

Abstract: A disclosed semiconductor device includes a semiconductor substrate including a first area, a gate electrode formed over the first area of the semiconductor substrate, a first active region formed in the first area of the semiconductor substrate at a lateral side of the gate electrode, a first silicide layer formed at least on a sidewall surface of the gate electrode in the first area, the first silicide layer is electrically connected to the first active region.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: A packaged sensor MEMS (100) has a semiconductor chip (101) with a protected cavity (102) including a sensor (105), the cavity surrounded by solder bumps (130) attached to the chip terminals; further a leadframe with elongated and radially positioned leads (131), the central lead ends (131a) attached to the bumps. Insulating material (120) encapsulates chip and central lead ends, leaving the chip surface (101a) opposite the cavity and the peripheral lead ends (131b) un-encapsulated. The un-encapsulated peripheral lead ends are bent into cantilevers for attachment to a horizontal substrate (160), the cantilevers having a geometry to accommodate, under a force lying in the plane of the substrate, elastic bending and stretching beyond the limit of simple elongation based upon inherent material characteristics, especially when supported by lead portions with curved, toroidal, or multiple-bendings geometries.

Abstract: The present subject matter relates to systems and methods for sealing one or more MEMS devices within an encapsulated cavity. A first material layer can be positioned on a substrate, the first material layer comprising a first cavity and a second cavity that each have one or more openings out of the first material layer. At least the first cavity can be exposed to a first atmosphere and sealed while it is exposed to the first atmosphere while not sealing the second cavity. The second cavity can then be exposed to a second atmosphere that is different than the first atmosphere, and the second cavity can be sealed while it is exposed to the second atmosphere.

Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).

Abstract: The present invention relates to a MEMS microphone and a method of manufacturing the same, the MEMS microphone comprising: a monolithic silicon chip incorporating an acoustic sensing element and one or more conditioning CMOS integrated circuits; a silicon-based carrier chip having an acoustic cavity; a substrate for surface mounting the assembly of the monolithic chip and the silicon-based carrier chip thereon; a conductive cover attached and electrically connected to the substrate to accommodates the assembly of the monolithic chip and the silicon-based carrier chip; and an acoustic port formed on either the conductive cover or the substrate for an external acoustic wave to reach the acoustic sensing element, wherein the monolithic silicon chip, the silicon-based carrier chip and the acoustic port are configured in such a way that the diaphragm of the acoustic sensing element can be vibrated by the external sound wave from one side thereof.

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam.

Abstract: In one embodiment, a magnetic element for a semiconductor device includes a reference layer, a free layer, and a nonmagnetic spacer layer disposed between the reference layer and the free layer. The nonmagnetic spacer layer includes a binary, ternary, or multi-nary alloy oxide material. The binary, ternary, or multi-nary alloy oxide material includes MgO having one or more additional elements selected from the group consisting of: Ru, Al, Ta, Tb, Cu, V, Hf, Zr, W, Ag, Au, Fe, Co, Ni, Nb, Cr, Mo, and Rh.

Abstract: A spin-current switched magnetic memory element includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers. The plurality of magnetic layers includes at least one composite layer.

Abstract: A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL.

Abstract: There is provided a solid-state imaging device including a pixel substrate in which a wire layer and a semiconductor element are formed using a wire material which can endure temperature at a time of forming a photoelectric conversion layer, and a logic substrate in which a semiconductor element is formed. The wire layer side of the pixel substrate is joined to a rear side of the logic substrate, and, after the photoelectric conversion layer is formed on a rear side of the pixel substrate, a wire layer is formed in the logic substrate such that the wire layers are disposed on a front side of the pixel substrate and the photoelectric conversion layer is disposed on the rear side of the pixel substrate.

Abstract: The invention illustrates an innovative way to fabricate low cost, efficient, rigid or flexible mesoscopic optoelectronic devices such as photovoltaic (PV) solar cells or photo sensors (b) comprising three-dimensional arrays of semi-conductive micro- or nano-pillars (3b) deposited from suspensions e.g. by inkjet printing. Said pillars additionally increase the surface area of the device composed of an interpenetrating network of semiconductor particles of mesoscopic (2-50 nm) size forming junctions. In the present invention the active surface area is significantly increased when compared to previous flat structures (a, 3a), being fabricated preferably by inkjet patterning. Additionally, the invention allows for production of much more functional devices when compared with conventional mesoscopic PV cells due to smaller structure density what makes the layer more resistive to mechanical failure when bending.

Abstract: An organic photoelectric conversion device can be easily produced by a method of producing an organic photoelectric conversion device, comprising forming an anode, forming an active layer on the anode, then, forming a cathode on the active layer by a coating method.

Abstract: A method for manufacturing a solid-state image pickup device that includes a pixel portion and a peripheral circuit portion, includes: forming a first insulating film in the pixel portion and the peripheral circuit portion, forming a second insulating film above the first insulating film, etching the second insulating film in photoelectric conversion elements, forming a metal film on the etched second insulating film in the photoelectric conversion elements and on the second insulating film in the peripheral circuit portion, and removing the metal film in the peripheral circuit portion and forming light-shielding films from the metal film in the photoelectric conversion elements.

Abstract: A method of manufacturing a radiation detection apparatus is provided. On a sensor substrate on which a pixel array is formed, a scintillator layer that covers the pixel array, a sealing layer that covers a side face of the scintillator layer, and a protection layer that covers an upper face of the scintillator layer and an upper face of the sealing layer are formed. The sensor substrate, the sealing layer, and the protection layer along a side of the pixel array are cut such that a cut surface of the sensor substrate, a cut surface of the sealing layer, and a cut surface of the protection layer are arranged on the same plane.

Abstract: Described are embodiments of apparatuses and systems including photonic devices having a conductive shunt layer, and methods for making such apparatuses and systems. A photonic device may include a device substrate, a photo-active region disposed on a first region of the device substrate, an isolation region in the device substrate, a contact disposed on a second region of the substrate such that the isolation region is located between the contact and the photo-active region, and a conductive material overlying the isolation region to shunt the first region with the second region. Other embodiments may be described and/or claimed.

Abstract: A polymer containing a triazine ring-containing repeating unit structure represented by, for example, formula (23) or (24), which alone can achieve high heat resistance, high transparency, high refraction index, high solubility, and low volume shrinkage, without adding a metal oxide.

Abstract: An embodiment relates to image sensor comprising one or more nanowires on a substrate of a cavity, the nanowire being configured to transmit a first portion of an electromagnetic radiation beam incident on the sensor, and the substrate that absorbs a second portion of the electromagnetic radiation beam incident on the sensor, wherein the first portion is substantially different from the second portion. The substrate could have a anti-reflective material. The ratio of a diameter of the cavity to a diameter of the nanowire could be at less than about 10.

Abstract: A method of manufacturing a semiconductor device including a first member including a chip mounting region and a peripheral region, a semiconductor chip mounted in the chip mounting region, and a second member fixed to the first member to cover the semiconductor chip, includes adhering, to the second member, the peripheral region of the first member in a state that the semiconductor chip is mounted in the chip mounting region, using an adhesive, and generating a stress between the first member and the second member, after the adhesive starts to cure, to locally form a gap in at least one of a portion between the first member and the adhesive, and a portion between the second member and the adhesive.

Abstract: A first semiconductor substrate 1 and a second semiconductor substrate 2 are different in material, and therefore have sensitivities to incident light of mutually different wavelength bands. Respective photodiodes of photodiode arrays are connected to amplifiers of the first semiconductor substrate 1. According to this method, the second semiconductor substrate 2 is separated from the wafer by etching the second semiconductor substrate 2 and then dicing a deepest portion of the etched groove. The density of crystal defects in a side surface produced by etching is smaller than the density of crystal defects in a side surface produced by dicing. Because a photodiode located in an end portion of the second semiconductor substrate 2 does not need to be removed, a reduction in the number of photodiodes can be suppressed.

Abstract: According to one embodiment, in a semiconductor device, a semiconductor substrate has a first surface and a second surface which is opposed to the first surface. An insulating layer is provided on the first surface of the semiconductor substrate. A metal wiring is provided within the insulating layer. A support substrate is bonded to the insulating layer. A poly silicon electrode is connected to the metal wiring through a contact. A pad is provided on the second surface of the semiconductor substrate and is connected to the poly silicon electrode through a metal film deposited in a via-hole to penetrate the semiconductor substrate and extend to the poly silicon electrode.

Abstract: A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

Abstract: A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

Abstract: An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

Abstract: A fuse of a semiconductor device and a method for forming the same are disclosed. The fuse includes a first metal line formed over a semiconductor substrate, a second metal line spaced apart from the first metal line, and a contact fuses formed of a metal contact coupled to the first metal line and the second metal line. Upper parts of the contact fuses overlap with each other, and lower parts are spaced apart from each other. Since the fuse is formed of a metal contact, fuse oxidation and fuse movement can be prevented. A conventional metal-contact fabrication process can be used, so that mass production of semiconductor devices is possible. In addition, the fuse region is reduced in size, reducing production costs.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: The present invention generally relates to a capacitor. By utilizing a semiconductor material between two electrodes, the storage capacity of the capacitor is increased as compared to a metal-insulator-metal capacitor.