Abstract: In an embodiment, a device comprises a circuit with at least one circuit element; measurement circuitry capable to test a state of the at least one circuit element during an operation of the circuit, the measurement circuitry comprising a first terminal configured to be coupled to a first node of the circuit via a first capacitor, a second terminal configured to be coupled to a second node of the circuit, wherein the measurement circuitry is configured to determine in situ an operating state of the at least one circuit element based on signals applied by the measurement circuitry to the circuit during the operation of the circuit.

Abstract: An apparatus for testing an arc fault detector comprises a housing (30) having an ac power input plug (32) and an ac power output socket (34), the plug being connected to supply ac power to the socket via electrical supply conductors (L, N) inside the housing. The socket (34) allows connection of an external appliance (36) to the housing for receiving power from the plug (32) through the internal supply conductors. An arc generator (100) inside the housing is connected between the plug (32) and the socket (34). The arc generator comprises at least one pair of contacts and means to vibrate the contacts alternately open and closed.

Abstract: A battery sensing section measures a voltage across a secondary battery. A current sensing section measures a current flowing through the secondary battery. A control section holds the value of an external impedance present in a discharge path outside the secondary battery, discharges the secondary battery from a first time to a second time at which an integrated discharge capacity based on a measured discharge current becomes equal to a predetermined discharge capacity reference value, calculates the internal impedance present in the secondary battery at the second time based on the measured voltage, calculates the second open voltage at the second time by multiplying the sum of the external impedance and the internal impedance by the measured discharge current, and calculates the recovered capacity of the secondary battery based on the first open voltage at the first time, the second open voltage and the discharge capacity reference value.

Abstract: A voltage measurement device that measures battery voltages of a plurality of single batteries connected in series has: a first voltage detection unit that detects the battery voltages; a storage unit that stores error information relating to a detection error between a voltage detected by the first voltage detection unit and a voltage detected by a second voltage detection unit of higher detection precision but lower detection speed than the first voltage detection unit; and a correction unit that, on the basis of the error information stored in the storage unit, corrects the battery voltages detected by the first voltage detection unit.

Abstract: A method can be used for monitoring a processing circuit. The processing circuit generates a response to a request and the response is compared with an expected response. A pass pulse is generated when the response matches the expected response. The causing, comparing and generating steps are repeated a number of times A frequency at which pass pulses occur is evaluated.

Abstract: An earth device is an earth device for earthing an object to be earthed. The earth device includes an earth-side wire, a detection-side wire which is normally out of conduction with the earth-side wire, an attachment member provided on one end portion of each of the earth-side wire and the detection-side wire and attached to the object to be earthed to provide conduction between the earth-side wire and the detection-side wire, an earth member for earthing provided on the other end portion of each of the earth-side wire and the detection-side wire, and a detection means connected to the detection-side wire to detect conduction in the detection-side wire.

Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.

Abstract: A method and a device for detecting defects in a packaging laminate having at least one conductive layer are provided. The method comprises the steps of grounding the conductive layer of the packaging laminate, arranging an electrode adjacent to the packaging laminate, applying a high voltage to the electrode by ramping the voltage from an initial value towards an upper predetermined value, and detecting a defect in the packaging material by registering dielectric breakdown between the electrode and the conductive layer of the packaging laminate.

Abstract: A method of obtaining a material property of a pavement material from a microwave field generally includes generating a microwave frequency electromagnetic field of a first mode about the pavement material. The frequency response of the pavement material in the electromagnetic field can be measured, such as by a network analyzer. The measurement of the frequency response permits correlating the frequency response to a material property of the pavement material sample, such as the density. A method of correcting for the roughness of a pavement material divides the pavement into a shallow layer and a deep layer. Two planar microwave circuits measure the permittivity of the shallow and deep layer. The permittivities are correlated to correct for roughness. An apparatus for obtaining the density of a pavement sample includes a microwave circuit and a network analyzer. The network analyzer measures the frequency response to determine the density of the pavement material.

Abstract: For proximity detection, capacitance of a sensing element to ground is measured as one or more objects move into or out of proximity to the sensing element.

Abstract: Methods and devices for detecting a hand in proximity to an electronic device are described. The electronic device includes a near field communications (NFC) antenna. In one aspect, the method includes: monitoring an induced voltage at the NFC antenna; and determining whether a hand is in proximity to the electronic device based on the induced voltage.

Abstract: An apparatus for determining an initiation point of cement curing, with a vessel for containing at least a portion of freshly mixed cement, means for passing an electric signal through the cement, means for detecting an abrupt change in a dielectric or electric property of the cement as a result of the electric signal and a display unit for displaying the initiation point of polymerization of the cement from the abrupt change in the dielectric or electric property detected, the change in the dielectric or electric property being a phase shift in the electric signal passed through the cement or a change in capacitive properties of the cement or a change in resistivity of the cement.

Abstract: A wood monitoring system and method is disclosed for monitoring lumber characteristics (e.g., lumber moisture) in environments of extremely high and prolonged temperature and moisture, e.g., a kiln. The monitoring system and method includes: (a) Sensors (provided within lumber stacks), wherein such sensors are battery powered and wirelessly communicate measurements indicative of moisture content of the wood adjacent to and/or between metal plates provided in an electrical circuit with the sensors and the wood between the plates; (b) Computer implemented methods and systems for wireless communication that conserve sensor battery power such that the sensors can operate for, e.g., six months within extremely adverse temperature and moisture environmental variations; and (c) Computer implemented methods and systems for estimating moisture content with a wood/lumber stack, and for predicting such moisture content (e.g., as a substantially steady state within the wood) after drying completion.

Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.

Abstract: A resistor having a known resistance is coupled in series with a device under test (DUT) having an unknown capacitance. An ac signal source having a known fundamental frequency is coupled to drive the resistor to thereby produce a first ac signal. A phase controllable signal generator produces a second ac signal. The first and second ac signals are fed to a mixer. An output of the mixer is low pass filtered. A peak detector monitors the low pass filtered output while sweeping the phase controllable signal generator, until a peak is detected. The set phase corresponding to the detected peak is then used to obtain an estimate of the unknown DUT capacitance. Other embodiments are also described and claimed.

Abstract: A device and method of determining a capacitance of a device is provided, which in one embodiment includes connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device, applying an AC voltage to the first terminal of the device and the first terminal of the capacitor, measuring a current through the capacitor, measuring a current through the device, determining a first voltage across the device as a function of time, computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of the current through the device to the current through the capacitor, determining a capacitance of the device as a function of voltage based on the capacitance as a function of time and the first voltage across the device as a function of time, and outputting data of the first capacitance of the device as a function of voltage.

Abstract: An impedance measuring device for an electronic component includes a constant voltage source, a load supplying circuit, a voltage detection circuit, and a controller. The constant voltage source outputs an input voltage. The load supplying circuit supplies a load resistor that is electronically connected in series with the electronic component between the constant voltage source and ground. The voltage detection circuit detects a voltage across the load resistor. The controller receives the voltage across the load resistor from the voltage detection circuit, and calculates an equivalent impedance of the electronic component according to the input voltage, the voltage across the load resistor, and the resistance of the load resistor.

Abstract: A testing device including a first connector, a control unit, a first detecting circuit and a memory controller is provided. The first connector is electrically connected to a first bus. The control unit generates a plurality of first control signals according to a first enable signal from the first connector. The first detecting circuit is electrically connected to a plurality of first transmission lines in the first bus, and sequentially conducts the first transmission lines to a ground according to the first control signals. The memory controller detects states of the signals transmitted by the first transmission lines and determines whether to generate a first abnormal indication signal according to a detecting result. The control unit controls a plurality of indication lights according to the first abnormal indication signal.

Abstract: A touch testing system for a capacitive touch device and a method thereof are provided. The system includes a test fixture, at least one magnetization component, at least one magnetic induction component and a driving unit. The fixture is disposed on the touch device and has at least one chute on a position corresponding to the touching area. The magnetization component is disposed on the fixture and enabled by a driving signal to produce a magnetic force. The magnetic induction component is slidably disposed in the chute and inducts the magnetic force to slide along the chute, such that the sensing unit produces a touch testing information. The driving unit is coupled to the magnetization component and the sensing unit, provides the driving signal to enable the magnetization component and receives the touch testing information to feed back a testing result on the capacitive touch device accordingly.

Abstract: A system and a method for capacitive testing a component (including a packaged component) are disclosed. An embodiment of a test head comprises a holding unit configured to pick-up, hold and release the component, an electrode configured to receive a capacitive signal from the component and a preamplifier configured to amplify the capacitive signal.

Abstract: An electrical contactor has a contact portion that is pressed onto a terminal of an electronic device and is electrically connected. When the dimension of the contact portion is S1, the contact dimension of the contact portion and the terminal of the electronic device is V, the amount of sliding of the contact portion is W, and the additional element including at least positional accuracy of the contact portion is X, the dimension of the contact portion S1 satisfies S1>V+W+X. In a contact method for the electrical contactor, when the sum of a clearance on the front end side in the sliding direction in starting contact and a clearance on the back end side in the sliding direction in ending contact is X3, the crushed area S2 of the terminal is set to satisfy a relationship of S2<S1?X3.

Abstract: A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.

Abstract: A semiconductor chip test method used in a semiconductor chip test apparatus including an electric energy measurement unit defining multiple conducting pin holes in a recess of an electric energy test table for holding contact pins of a semiconductor chip for testing electric properties, a functional tester disposed adjacent to the electric energy measurement unit for testing predetermined functions of the semiconductor chip in a functional test table thereof and transmitting tested data to an external display screen through a display card, and a conveyer unit controllable to deliver the test semiconductor chip to the electric energy test table for electric energy measurement and to the functional test table of the functional tester for functional test.

Abstract: Provided is a semiconductor device capable of performing fault detection on a circuit executing an AD conversion operation during the AD conversion operation. The semiconductor device includes an analog to digital conversion unit that converts a second analog signal into a first digital signal, in which the second analog signal is obtained by adding a first analog signal and an offset signal with a signal band different from the first analog signal, a signal extraction unit that extracts from the first digital signal a second digital signal corresponding to the signal band of the offset signal, and a fault detection unit that detects a fault in the analog to digital conversion unit based on the second digital signal and a setting value that is set upon generating the offset signal.

Abstract: A method of determining the magnetization level of permanent magnets of an electric machine, whereby a probe winding is placed in an electric machine having a stator with a plurality of stator winding, and a rotor with a plurality of permanent magnets; the probe winding is fixed with respect to the stator and links a magnetic flux produced by the permanent magnets; the rotor is rotated at an angular speed; an induced electric quantity is determined at terminals of the probe winding in response to passage of the permanent magnets; and the magnetization level of the permanent magnets is determined on the basis of the induced electric quantity detected.

Abstract: An integrated circuit includes an outputting unit in which a CMOS inverter configured from a first MOS transistor and a second MOS transistor for outputting a second signal using a first signal as an input thereto and a third MOS transistor that includes a gate terminal to which a control signal for controlling the outputting of the second signal is inputted and that is in an off state when the control signal indicates inhibition of the outputting of the second signal are cascade-connected to each other, and a fixing unit that fixes a value of the first signal based on the control signal. When the control signal indicates inhibition of the outputting of the second signal, the fixing unit fixes the value of the first signal to a value with which the first or second MOS transistor is placed in an off state.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: According to an embodiment, a solid-state bidirectional switch includes a first and a second power field-effect transistor electrically connected anti-serial with each other. Each of the first and second power field-effect transistors includes a source region, a drain region, a body region forming a pn-junction with the source region and having an inversion channel region, a gate terminal, a drift region between the body region and the drain region and having an accumulation channel region, and a drift control region adjacent to the accumulation channel region. The accumulation channel region is controllable through the drift control region. The solid-state bidirectional switch further includes a controller connected with the gate terminals of the first and second power field-effect transistors.

Abstract: A current providing circuit, for providing an output current at an output terminal, comprising: a current providing module, coupled to a first predetermined voltage level, for providing the output current according to the first predetermined voltage level and a control voltage transmitted to the current providing module; and a control voltage generating module, for generating the control voltage corresponding to the first predetermined voltage level and a threshold voltage of the current providing module.

Abstract: An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.

Abstract: A PLL generates an output clock obtained by multiplying a reference clock by an odd number. An odd-number frequency divider divides the output clock by the odd number to generate a first clock. A frequency divider divides the first clock by a predetermined number to generate a second clock. An even-number frequency divider divides the output clock by an even number to generate a third clock. A frequency divider divides the third clock at such a frequency division ratio that makes the frequency division ratio of the odd-number frequency divider and the frequency divider match the frequency division ratio of the even-number frequency divider and the frequency divider to generate a fourth clock. A control unit lowers an oscillation frequency of the PLL when the result of comparing the second clock and the fourth clock represents a mismatch.

Abstract: An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Abstract: In one embodiment, a phase locked loop (PLL) circuit in a device includes selectable feedback paths and a multiplexer. An internal feedback path is adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of the device and an external feedback path is adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device. The multiplexer is provided for selecting between the internal and external feedback paths.

Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects.

Abstract: A novel semiconductor device and a method of driving the semiconductor device. A (volatile) node in which data that is rewritten as appropriate by arithmetic processing is held and a node in which the data is stored are electrically connected to each other via a source and a drain of a transistor in which a channel is formed in an oxide semiconductor layer. Then, data and data obtained by inverting the data (inverted data) are stored before supply of power source voltage is stopped, and the two inputs (data) are compared after restart of supply of the power source voltage, so that data obtained by arithmetic processing just before the supply of the power source voltage is stopped is restored.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

Abstract: A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: Radio-frequency (RF) switch circuits providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a source, drain, gate, and body. A compensation circuit is connected to the respective source of the at least one FET. The compensation circuit may be configured to compensate a non-linearity effect generated by the at least one FET.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a respective gate and body. A resonance circuit connects the body of each of the at least one FET to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, wherein the approximately closed circuit allows removal of surface charge from the body to the reference node.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: Radio-frequency (RF) switch circuits are disclosed having adjustable resistance to provide improved switching performance. RF switch circuits include at least one field-effect transistor (FET) disposed between first and second nodes, each of the FET having a respective gate and body. An adjustable-resistance circuit is connected to either or both of the respective gate and body of the FET(s).

Abstract: Radio-frequency (RF) switch circuits having switchable transistor coupling for improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between first and second nodes, each FET having a gate and body. A switchable resistive coupling circuit is connected to each of the respective gates. A switchable resistive grounding circuit is connected to each of the respective bodies.

Abstract: Transmit modules typically constitute passive matching circuitry, harmonic trap filters and an antenna switch to provide isolation between the transmit bands as well as between transmit and receive functions. In complementary metal-oxide semiconductor (CMOS) processes the switch function is difficult to implement as a large voltage swing may result in breakdown of the MOS oxide, drain diode, source diode as well as substrate diodes. Therefore a switching function is provided at a node that has low impedance during transmit that limits the voltage swing that the MOS switches experience. The approach is particularly useful, but not limited to, half duplex transmissions such as those used in global system for mobile (GSM) communication, enhanced data for GSM Evolution (EDGE), and time division synchronous code division multiple access (TDSCDMA).

Abstract: Radio-frequency (RF) switch circuits having switchable transistor coupling for providing improved switching performance. An RF switch system includes at least one first field-effect transistor (FET) disposed between first and second nodes, each FET having a body and gate. A coupling circuit couples the respective body and gate of the at least one first FET. The coupling circuit may be configured to be switchable between a resistive-coupling mode and a body-floating mode.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each having a respective source, drain, gate, and body. The system includes a coupling circuit including a first path and a second path, the first path being between the respective source or the respective drain and the respective gate of the at least one FET, the second path being between the respective source or the respective drain and the respective body of the at least one FET. The coupling circuit may be configured to allow discharge of interface charge from either or both of the coupled gate and body.

Abstract: Radio-frequency (RF) switch circuits are disclosed having transistor gate voltage compensation to provide improved switching performance. RF switch circuits include a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate. A compensation network including a coupling circuit couples the gates of each pair of neighboring FETs.