Abstract: The invention relates to a method for diagnosing a disease state mediated by pathogenic cells. The method comprises the steps of combining with an ex vivo patient sample a composition comprising a conjugate or complex of the general formula Ab-X, wherein the group Ab comprises a ligand that binds to the pathogenic cells and the group X comprises an imaging agent, and detecting the pathogenic cells that express a receptor for the ligand using flow cytometry.

Abstract: Methods are provided for detecting and optionally quantitating multiple analytes, including nucleic acid and/or polypeptide analytes, in particle-based assays that can be highly multiplexed. Compositions, systems, and kits related to the methods are also featured.

Abstract: Droplet actuator devices and methods for immunoassays and washing are provided. According to one embodiment, a method of providing a droplet in contact with a surface of a super paramagnetic bead with a reduced concentration of a substance is provided and includes: (a) providing a super paramagnetic bead in contact with a droplet comprising a starting concentration and starting quantity of the substance and having a starting volume; (b) conducting one or more droplet operations to merge a wash droplet with the droplet provided in step (a) to yield a combined droplet; and (c) conducting one or more droplet operations to divide the combined droplet to yield a set of droplets. The set of droplets includes: (i) a droplet in contact with the super paramagnetic bead having a decreased concentration of the substance relative to the starting concentration; and (ii) a droplet which is separated from the super paramagnetic bead.

Abstract: A new fractionation device shows desirable features for exploratory screening and biomarker discovery. The constituent MSCs may be tailored for desired pore sizes and surface properties and for the sequestration and enrichment of extremely low abundant protein and peptides in desired ranges of the mass/charge spectrum. The MSCs are effective in yielding reproducible extracts from complex biological samples as small as 10 ?l in a time as short as 30 minutes. They are inexpensive to manufacture, and allow for scaled up production to attain the simultaneous processing of a large number of samples. The MSCs are multiplexed, label-free diagnostic tools with the potential of biological recognition moiety modification for enhanced specificity. The MSCs may store, protect and stabilize biological fluids, enabling the simplified and cost-effective collection and transportation of clinical samples.

Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

Abstract: A method for fabricating a magnetic tunnel junction element includes forming a magneto resistance layer including a first magnetic layer, an insulation layer and a second magnetic layer on a substrate, forming a magnetic loss area by doping a magnetic loss impurity into a region of the magneto resistance layer to cause a magnetic loss, and etching the magnetic loss area to form a magnetic tunnel junction element.

Abstract: A thermoelectric conversion module includes a pair of heat transfer plates, p-type semiconductor blocks and n-type semiconductor blocks arranged between the heat transfer plates, and terminal electrodes formed respectively on inner surfaces of the heat transfer plates and connecting the semiconductor blocks in series. The heat transfer plates include holes reaching from an outer surface to the terminal electrodes, and grooves each formed between the terminal electrodes and communicating between the adjacent holes. If a disconnection occurs, for example, a pin of a tester is brought into contact with the terminal electrode via the hole to specify a disconnected portion, and the terminal electrodes are electrically connected by injecting conductive paste into the holes in the disconnected portion as well as the groove.

Abstract: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.

Abstract: A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits.

Abstract: A method of making an electronic device with a redistribution layer includes providing an electronic device having a first pattern of contact areas, and forming a redistribution layer on a temporary substrate. The temporary substrate has a second pattern of contact areas matching the first pattern of contact areas, and a third pattern of contact areas different than the second pattern of contact areas. The second pattern of contact areas is coupled to the third pattern of contact areas through a plurality of stacked conductive and insulating layers. The first pattern of contact areas is coupled to the second pattern of contact areas on the transferrable redistribution layer. The temporary substrate is then removed to thereby form a redistributed electronic device.

Abstract: A light emitting device comprises: an LED chip having a quantum well structure and a light emitting layer made of a gallium nitride compound semiconductor; a first transparent material covering the LED chip; a second transparent material for protecting the LED chip and the first transparent material; and a phosphor for absorbing a part of the light from the LED chip and emitting a light having a wavelength different from the light from the LED chip; wherein the phosphor is included in second transparent material, and the light from the LED chip and the light from said phosphor are mixed to make a white light.

Abstract: A method of manufacturing a nozzle plate includes: a mask pattern layer forming step of, with respect to a laminated substrate constituted of a first silicon substrate having a (111) surface orientation and a second silicon substrate having a (100) surface orientation, forming a frame-shaped mask pattern layer on the second silicon substrate; a non-through hole forming step of forming a straight section of the nozzle in the first silicon substrate; a protective film forming step of forming a protective film over a first portion on the second silicon substrate that is not covered with the mask pattern layer, and over inner surfaces of the first and second silicon substrates defining the non-through hole; and an anisotropic etching step of anisotropically etching the second silicon substrate so as to form a tapered section of the nozzle defined with {111} surfaces exposed in the second silicon substrate by the anisotropic etching.

Abstract: Techniques for fabricating contacts on inverted configuration surfaces of GaN layers of semiconductor devices are provided. An n-doped GaN layer may be formed with a surface exposed by removing a substrate on which the n-doped GaN layer was formed. The crystal structure of such a surface may have a significantly different configuration than the surface of an as-deposited p-doped GaN layer.

Abstract: A method of making a solid element device that includes a solid element, an element mount part on which the solid element is mounted and which has a thermal conductivity of not less than 100 W/mK, an external terminal provided separately from the element mount part and electrically connected to the solid element, and a glass sealing part directly contacting and covering the solid element for sealing the solid element, includes pressing a glass material at a temperature higher than a yield point of the glass material for forming the glass sealing part.

Abstract: A double-metallic deposition process is used whereby adjacent layers of different metals are deposited on a substrate. The surface plasmon frequency of a base layer of a first metal is tuned by the surface plasmon frequency of a second layer of a second metal formed thereon. The amount of tuning is dependent upon the thickness of the metallic layers, and thus tuning can be achieved by varying the thicknesses of one or both of the metallic layers. In a preferred embodiment directed to enhanced LED technology in the green spectrum regime, a double-metallic Au/Ag layer comprising a base layer of gold (Au) followed by a second layer of silver (Ag) formed thereon is deposited on top of InGaN/GaN quantum wells (QWs) on a sapphire/GaN substrate.

Abstract: The inventive concept provides organic light emitting diodes and methods of manufacturing an organic light emitting diode. The organic light emitting diode includes a substrate, a first electrode layer and a second electrode layer formed on the substrate, an organic light emitting layer disposed between the first electrode layer and the second electrode layer and generating light, and a scattering layer between the first electrode layer and the substrate or between the first electrode layer and the organic light emitting layer. The scattering layer scatters the light.

Abstract: A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and using an external device to develop charge in the material.

Abstract: A manufacturing method of a thin film transistor array panel includes forming a gate line on a substrate and a gate insulating layer on the gate line, forming a semiconductor on the gate insulating layer, forming a first data line and a first drain electrode on the semiconductor, forming a lower passivation layer on the first data line and the first drain electrode, forming an upper passivation layer on the lower passivation layer and a metal layer on the upper passivation layer, etching the metal layer by using a photosensitive film as a mask to form a reflecting electrode and to expose the lower passivation layer, etching the exposed lower passivation layer to form a first contact hole exposing the first drain electrode, and forming a connection assistance member connecting the first drain electrode and the reflecting electrode through the first contact hole after removing the photosensitive film.

Abstract: The present invention relates to a process for fabricating light-emitting device. More particularly, the aim of the invention is to allow the fabricating of light emitters with improved efficiency by using artificial materials, enabling antireflection or high-reflectivity treatments to be carried out. For this purpose, subwavelength structures are etched on one of the ends of an emissive cavity, enabling external face to be controlled. The invention applies to any light emitter, and therefore notably to lasers and more particularly still to QCLs (quantum cascade lasers). Moreover, the fabrication process according to the invention is preferably a wafer-scale process.

Abstract: There is provided a method of manufacturing a light emitting diode and a light emitting diode manufactured by the same. The method includes growing a first conductivity type nitride semiconductor layer and an undoped nitride semiconductor layer on a substrate sequentially in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the undoped nitride semiconductor layer grown thereon to a second reaction chamber; growing an additional first conductivity type nitride semiconductor layer on the undoped nitride semiconductor layer in the second reaction chamber; growing an active layer on the additional first conductivity type nitride semiconductor layer; and growing a second conductivity type nitride semiconductor layer on the active layer.

Abstract: A method for making a semiconductor epitaxial structure is provided. The method includes growing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, epitaxially growing a doped semiconductor epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be suspended above the epitaxial growth surface.

Abstract: A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.

Abstract: On a light-emitting layer, a p cladding layer of AlGaInN doped with Mg is formed at a temperature of 800° C. to 950° C. Subsequently, on the p cladding layer, a capping layer of undoped GaN having a thickness of 5 ? to 100 ? is formed at the same temperature as employed for a p cladding layer. Next, the temperature is increased to the growth temperature contact layer in the subsequent process. Since the capping layer is formed, and the surface of the p cladding layer is not exposed during heating, excessive doping of Mg or mixture of impurities into the p cladding layer is suppressed. The deterioration of characteristics of the p cladding layer is prevented. Then, on the capping layer, a p contact layer is formed at a temperature of 950° C. to 1100° C.

Abstract: An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped.

Abstract: The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.

Abstract: A method is provided for forming a Group VA-doped solution-processed metal chalcogenide. The method forms a first solution including a first material group, dissolved in solvent. A Group VA-containing material is added to the first solution. The Group VA-containing material may include arsenic (As), antimony (Sb), bismuth (Bi), or combinations thereof. The first solution is deposited on a conductive substrate, and a Group VA-doped first intermediate film is formed comprising metal precursors from corresponding members of the first material group. Thermal annealing is performed in an environment of selenium (Se), Se and hydrogen (H2), hydrogen selenide (H2Se), sulfur (S), S and H2, hydrogen sulfide (H2S), or combinations thereof. As a result, the metal precursors in the Group VA-doped first intermediate film are transformed, forming a Group VA-doped metal chalcogenide layer. In one aspect, an antimony-doped Cu—In—Ga—Se chalcogenide (CIGS) is formed.

Abstract: The present invention provides a method for an organic thin film solar cell and an organic thin film solar cell manufactured by the same, which can reduce manufacturing cost by simplifying manufacturing process, ensure long-lasting durability and stability, and improve energy conversion efficiency of the solar cell.

Abstract: A method of forming an optoelectronic device. The method includes providing a deposition surface and contacting the deposition surface with a ligand exchange chemical and contacting the deposition surface with a quantum dot (QD) colloid. This initial process is repeated over one or more cycles to form an initial QD film on the deposition surface. The method further includes subsequently contacting the QD film with a secondary treatment chemical and optionally contacting the surface with additional QDs to form an enhanced QD layer exhibiting multiple exciton generation (MEG) upon absorption of high energy photons by the QD active layer. Devices having an enhanced QD active layer as described above are also disclosed.

Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.

Abstract: An electrically conductive ribbon, which is soldered on an electrically conductive busbar of a photovoltaic panel, includes a cooper core and a tin based solder. The tin based solder fully wraps an outer surface of the cooper core, and has a convex solder surface, which has a first curvature to be fitted with a second curvature of a concave solder surface of the electrically conductive busbar.

Abstract: A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.

Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.

Abstract: One object is to have stable electrical characteristics and high reliability and to manufacture a semiconductor device including a semi-conductive oxide film. Film formation is performed by a sputtering method using a target in which gallium oxide is added to a material that is easy to volatilize compared to gallium when the material is heated at 400° C. to 700° C. like zinc, and a formed film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film and the oxide is crystallized. Further, a semi-conductive oxide film is deposited thereover, whereby a semi-conductive oxide having a crystal which succeeds a crystal structure of the oxide that is crystallized by heat treatment is formed.

Abstract: The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.

Abstract: A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test.

Abstract: A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

Abstract: A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test.

Abstract: An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation and the cavity; and mounting an electrical component over the second interposer.

Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A flank wettable semiconductor device is assembled from a lead frame or substrate panel by at least partially undercutting the lead frame or substrate panel with a first cutting tool to expose a flank of the lead frame and applying a coating of tin or tin alloy to the exposed flank prior to singulating the lead frame or substrate panel into individual semiconductor devices. The method includes electrically interconnecting lead frame flanks associated with adjacent semiconductor devices before applying the coating of tin or tin alloy. The lead frame flanks may be electrically interconnected during wire bonding.

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.

Abstract: Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: Mirror-polished CZ wafer and FZ wafer are prepared. A first impurity region which will be a first isolation region is formed in a surface layer of a first main surface of the CZ wafer. The first main surface of the CZ wafer and a first main surface of the FZ wafer are bonded to each other by an inter-molecular bond. A second impurity region which will be a second isolation region is formed in a surface layer of a second main surface of the FZ wafer. A heat treatment is performed to diffuse the first impurity region and the second impurity region such that the first impurity region and the second impurity region are continuous, thereby forming a through silicon isolation region.

Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.

Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.