Abstract: A computer readable medium storing a computer program for execution by at least one processor is disclosed. The computer program is for determining that a first identified location is too close to an edge of a window of a graphical user interface to display a radial display area. The computer program is also for identifying a second location far enough from the edge to fully display the radial display area within the window. The computer program is also for displaying the radial display area at the second location.

Abstract: An approach is provided for generating a multi-dimensional input. A user interface platform causes, at least in part, a mapping of one or more parameters, one or more representations of the one or more parameters, or a combination thereof onto one or more respective surface segments of at least one three-dimensional icon. The user interface platform then causes, at least in part, a rendering of the at least one three-dimensional icon in a user interface. The user interface platform then determines one or more manipulations of the at least one three-dimensional icon in the user interface, and processes and/or facilitates a processing of the one or more manipulations to determine one or more weighting values for the one or more parameters.

Abstract: In one embodiment, dynamic menu reordering of a menu is effected by presenting a plurality of menus; receiving a menu selection; in response to the menu selection, presenting a plurality of menu options, each of which menu options occupies a respective menu position; receiving reordering information; and in response to the reordering information, reordering at least one menu position occupied by a respective memory option. In an additional embodiment, menu-option position information is retained in accordance with reordering information; and upon a subsequent menu selection, menu options are presented so that at least one menu option occupies a user-defined position.

Abstract: A mobile terminal and a method of controlling an image display thereof are disclosed. A display module for a mobile terminal as disclosed herein may include a display for displaying an image that includes one or more objects, a user input interface to receive an input to change the image between a 2D display and a 3D display, and a controller configured to change the displayed image between the 2D display and the 3D display based on the received input. The controller may control the display to sequentially display one or more intermediate images in order to gradually change an extent in which at least one of the one or more objects is perceived to protrude or recede into the display during the change in the displayed image.

Abstract: The uniqueness of the screen name for each screen of a system to be evaluated is evaluated simply and with high precision.

Abstract: A method for executing a user command in a display device including receiving, from an input device, a signal that indicates a movement direction of the input device, determining the movement direction of the input device based on the received signal, determining one of a plurality of functions of the display device that corresponds to the movement direction from among the plurality of functions of the display device, and executing the determined function.

Abstract: A finger pointer is used for moving a cursor and selecting objects on a touchscreen. The finger pointer includes a cursor indicator and a finger contact area. The cursor indicator points to a location on the touchscreen that would be activated when the finger pointer is selected. The finger contact area indicates the location on the touchscreen where a user may touch the screen to activate or move the finger pointer. The finger pointer may be used to select objects such as hyperlinks on a browser web page, and items from an application of menu. The user touches the touchscreen within the finger contact area. The user then contacts the touchscreen at a different location to move the finger pointer to the different location such that the cursor indicator is positioned on an object is to be selected.

Abstract: The subject matter disclosed herein relates to proximity sensors to measure distance from a surface, and more particularly, calibrating proximity sensors to adjust for various reflecting surfaces.

Abstract: A display method for controlling a display state of an image regardless of a motion direction, includes displaying an image in a screen; and when an inward or outward motion having a center, is input onto the screen, the motion moving in a direction toward or away from the center, controlling a display state of the image according to the direction of the motion.

Abstract: In general, this disclosure describes techniques for moving a graphical selector. In one example, a method includes activating, by a computing device, a graphical key that is displayed with a presence-sensitive interface of the computing device. Upon activation of the graphical key, the method also includes receiving gesture input corresponding to a directional gesture using the presence-sensitive interface of the computing device and moving a graphical selector displayed with the presence-sensitive interface from a first graphical location to a second graphical location by at least one selected increment based on a property of the gesture input.

Abstract: A computer-implemented method includes identifying a bit-mapped image of a line or polygon shape; mapping the image to a texture map that is slightly large in at least one dimension than the bit-mapped image; overlaying the bit-mapped image and the texture map; computing pixel shading for pixels between an outer edge of the bit-mapped image and the texture map by measuring a distance from particular ones of the pixels to an idealized line near an edge of the bit-mapped image; and displaying the bit-mapped image with pixels at its edge shaded according to the computed pixel shading.

Abstract: Disclosed are methods and apparatuses for receiving the input of parameter ranges into computing devices. In one embodiment, a method is disclosed for accepting user input of a time range into a computing device equipped with a touchscreen. The method includes displaying a time bar on the touchscreen and receiving a touch input ending at a first location and a second touch input ending at a second location. The computing device displays time markers at the first and second locations. The method further includes identifying first and second times corresponding to the first and second locations and a time range including the first and second times. The method further includes receiving a third touch input commencing at one of the time markers and terminating at a third location. The method further includes updating the time marker at the position of the third location and updating the time range.

Abstract: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Abstract: According to one embodiment, a pattern data generating apparatus comprises a storage unit that stores a table defining direct self assembly information that combines a direct self assembly material, a film thickness of the direct self assembly material, and a process condition for the direct self assembly material according to a pattern dimension, a division unit that divides layout data of a device based on the pattern dimension to generate divided layouts, an extraction unit that extracts the direct self assembly information corresponding to the pattern dimension of the divided layout from the table, and a generation unit that generates pattern data by allocating the direct self assembly information extracted by the extraction unit to the divided layouts.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: Aspects of the invention relate to techniques for integrating optical proximity correction and mask data preparation. First mask writer instructions for a layout design are simulated to generate a mask contour. Based on the generated mask contour, first layout data for the layout design are adjusted for optical proximity correction to generate second layout data. Using the generated second layout data as mask target, the first mask writer instructions are adjusted to generate second mask writer instructions. The above process may be iterated until an end condition is met.

Abstract: Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such as optical proximity correction.

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: Methods, systems, and computer readable medium for developing a system architecture that involves defining resource constraints for kinds of resources and constraint values for optimization parameters, and defining a design space as variants, where each variant is a vector. Satisfying sets of variants are determined for optimization parameters by assigning membership values to each variant of a universe of discourse set and performing a fuzzy search of a universe of discourse set using the corresponding membership values. A set of variants is determined based on an intersection of the satisfying sets of variants. An ordered list of variants is generated by sorting the set of variants and a variant is selected based on a position of the variant in the ordered list for use in developing the system architecture.

Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.

Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

Abstract: A system for functional verification of a chip design includes the chip design, a test generator, a test bench, a verification tool, and a coverage tool. The coverage tool is configured to receive chip design, user input, and coverage files from the verification tool to generate information for the test generator to improve the test coverage of the verification tool. The method includes receiving a chip design, functionally testing the chip design, generating coverage files, receiving user options, including a coverage basis, a report basis, and a defined coverage, calculating coverage impact and new overall coverage using the defined coverage and coverage files, and ranking each report basis according to coverage impact of each coverage basis.

Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.

Abstract: A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.

Abstract: An aspect includes a computer program product for implementing a model of an electrical circuit including a first region and a second region, the first region including simulated logic and a simulated latch circuit. The computer program product includes a tangible storage medium readable by a processing circuit for performing a method. The method includes receiving, as simulated logical inputs to the simulated logic a simulated power supply voltage state of the first region, a simulated data input signal and a simulated clock signal. The method also includes generating, based on determining that the simulated power supply voltage state of the first region corresponds to an inactive state of the first region, a pseudo-random number as an output of the simulated latch circuit, the pseudo-random number generated based on the simulated data input signal and the simulated data output signal from the simulated latch circuit.

Abstract: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.

Abstract: Some embodiments include a method for identifying high-temperature regions in a microchip. In some embodiments, the method includes selecting grids on the microchip, wherein each grid includes devices and interconnects connecting the devices. The method can also include determining, for each grid, a temperature factor value based on geometric area of the grid, geometric area occupied by the devices, switching factor of the of the interconnects, and length of the interconnects connecting the devices. The method can also include determining, for each grid, thermal sensitivity for the grid by generating a plot based on a Guassian equation.

Abstract: Defect characterization is a useful tool for analyzing and improving fabrication for semiconductor chips. By using layout and netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, performance, and other characteristics.

Abstract: A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to receive a current waveform of a communication between a plurality of participants. Additionally, the programming instructions are operable to create a voiceprint from the current waveform if the current waveform is of a human voice. Furthermore, the programming instructions are operable to determine one of whether a match exists between the voiceprint and one library waveform of one or more library waveforms, whether a correlation exists between the voiceprint and a number of library waveforms of the one or more library waveforms and whether the voiceprint is unique.

Abstract: In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.

Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.

Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.

Abstract: A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.

Abstract: Method of placing and routing circuit components including: dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability.

Abstract: A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function, which includes the penalty function, can be computed to enable the use of a conjugate-gradient-based numerical solver.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function.

Abstract: Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.

Abstract: The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first keep out layer, and a reference layer are determined based on the stack-up parameters. The first keep-out layer is placed between the radio frequency layer having a first signal trace disposed thereon and the reference layer. A first keep-out region on the first keep-out layer is formed in corresponding to the first signal trace. Circuit layouts disposed inside the first keep-out region are removed. Consequently, the corresponding keep-out region may be automatically generated in accordance to the signal requirements of the signal trace while designing the circuit layout thereby increase circuit layout quality and efficiency thereof.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: Methods, systems, and computer program products may provide pre-merge conflict avoidance in a revision-control system. A pre-merge conflict avoidance method may include identifying by a computer system a portion of interest of a revision-controlled base source code stored in a source-code repository, the base source code being developed by a plurality of developers. The computer system may determine whether at least one of the plurality of developers has made a change to a portion of a first copy of the base source code corresponding to the portion of interest prior to commitment of the first copy of the base source code to the source-code repository. In response to a determination that the at least one developer has made a change to the portion of interest, a notification may be produced about the change to the portion of interest by the at least one developer.

Abstract: Techniques for quantifying and improving consumability of software bundles are provided. In one aspect, a method for quantifying a consumability of a software bundle is provided which includes the following steps. Constituent software products of the bundle are identified. Software components an installation of which is a pre-requirement for an installation of the software products are identified. Software units an installation of which is a pre-requirement for an installation of the software components are identified. Dependency graphs are created for the software components. The dependency graphs for the components are merged to create dependency graphs for the products. The dependency graphs for the products are merged to create a dependency graph for the bundle. The dependency graph for the bundle is used to quantify the consumability of the bundle.

Abstract: In a model editing apparatus, a model transformation function transforms SM (source model) 0 into TM (target model) 0, and generates TDM (transformation dependency model) 0. Moreover, when an SM editor generates SM1 by updating SM0, the model transformation function transforms SM1 into TM1 and generates TDM1. When a TM editor generates TM0_n by editing TM0 independently of the change in SM0, a Change element registration function registers a difference ?2 between TM0 and TM0_n in TDM0, thereby generating TDM0_n. Then, in response to a call, a merge function merges a difference ?1 between TDM0 and TDM1 extracted by a ?1 extraction function, and a difference ?2 extracted from TDM0_n, according to prestored processing patterns.

Abstract: The invention concerns a model transformation unit adapted to transform a first source model in a source domain into a target model in a target domain, the first source model being a tree of source elements and the target model being a tree of target elements representing a project to be implemented in computer code, the model transformation unit including at least one memory adapted to store the first source model (104, 106), a source meta-model (204) representing the source domain, a target meta-model (206) representing the target domain, and a transformation model (210) indicating rules for transforming between the source meta-model and the target meta-model; and a transformation engine (102) adapted to determine, based on the transformation model, a parent element of each target element of the target model to be generated and to construct the target model by generating, for each source element in the source model to be transformed, a target element based on the transformation model, and by positioning eac

Abstract: Systems, methods, and apparatuses including computer program products for generating a custom language model. In one implementation, a method is provided. The method includes receiving a collection of documents; clustering the documents into one or more clusters; generating a cluster vector for each cluster of the one or more clusters; generating a target vector associated with a target profile; comparing the target vector with each of the cluster vectors; selecting one or more of the one or more clusters based on the comparison; and generating a language model using documents from the one or more selected clusters.

Abstract: A method, system and apparatus for visualization of versions of a BOM. In accordance with an embodiment of the invention, at least two different versions of a BOM can be loaded into a versioning data processing system of a modeling tool executing in memory of a computer. The data from both versions of the BOM can be loaded into a single table in which each row of the table can include columns for a class name of a corresponding class specified by one of the versions of the BOM, a version of the corresponding class and at least one characteristic of the corresponding class such as a member name, type, date, argument, or other annotations such as vocabulary, comments, date. Subsequently, the single table can be visualized in at least two different treemaps for at least two different attributes of the versions of the BOM set forth in the single table.

Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.

Abstract: In an embodiment, a class definition of a class may provide an indication whether a property, which is part of the class, is immutable. The indication may be made implicitly or explicitly. A value of the property may be established (e.g., set) during a creation of an instance of the class. An attempt to set the value of the property after the instance is created may be disallowed. Further, an error (e.g., an error message, exception condition) may be reported in response to disallowing the attempt.

Abstract: Various techniques for interacting with a test case via a graphical model are disclosed. For example, one method involves displaying a first icon, which represents a first testing activity within a test case; displaying a second icon, which represents a second testing activity within the test case; and displaying a connector, which couples the first icon and the second icon. An assertion (e.g., against test results obtained by performing the first testing activity) is associated with the connector.