Abstract: The beam measuring apparatus of the present invention includes a detection device including a shield member that has an edge, and a detector configured to detect the beam of which at least a part is not shielded by the shield member; a relative movement mechanism configured to cause a relative movement between the shield member and the beam; and a controller configured to control the detection device and the relative movement mechanism so as to cause one of the edge and the beam to traverse the other with respect to each of a plurality of points on the edge, to sum a plurality of signals, respectively obtained by the detection device with respect to the plurality of points and with respect to relative positions of the relative movement corresponding to one another, so as to obtain a signal sequence, and to obtain the characteristic based on the signal sequence.

Abstract: An example particle accelerator includes the following: a resonant cavity in which particles are accelerated, where the resonant cavity has a background magnetic field having a first shape; and an extraction channel for receiving particles output from the resonant cavity. The extraction channel comprises a series of focusing regions to focus a beam of received particles. At least one of the focusing regions is a focusing element configured to alter a shape of the background magnetic field to a second shape that is substantially opposite to the first shape in the presence of a magnetic field gradient resulting from reduction of the background magnetic field from the resonant cavity to the extraction channel.

Abstract: A target supply device may include a tank having a nozzle, a first electrode provided with a first through-hole, a second electrode provided with a second through-hole, a third electrode disposed within the tank, an anchoring portion configured to anchor the first electrode and the second electrode to the tank so that insulation among the nozzle, the first electrode, and the second electrode is maintained, and so that a center axis of the nozzle is positioned within the first through-hole and the second through-hole, a first projecting portion that is an integrated part of at least one of the first electrode and the second electrode and that is configured to project toward the nozzle, and a second projecting portion that is an integrated part of at least the second electrode and that is configured to project so as to be positioned between the first electrode and the second electrode.

Abstract: Techniques for generating EUV light include directing a first pulse of radiation toward a target material droplet to form a modified droplet, the first pulse of radiation having an energy sufficient to alter a shape of the target material droplet; directing a second pulse of radiation toward the modified droplet to form an absorption material, the second pulse of radiation having an energy sufficient to change a property of the modified droplet, the property being related to absorption of radiation; and directing an amplified light beam toward the absorption material, the amplified light beam having an energy sufficient to convert at least a portion of the absorption material into extreme ultraviolet (EUV) light.

Abstract: A window lighting system may include a frame (1071, 1171, 1271, 1471) defining a perimeter of a window (1070, 1170, 1270, 1470). The frame may have a hollow interior. A driver (30), which may be located within the hollow interior or external to the window lighting system, may be configured to drive one or more light sources (1076, 1176, 1276, 1486). A lens (46) may be disposed along the hollow interior to focus light emitted by the one or more light sources across a surface of the window or into an interior of a building.

Abstract: A packaging device for the transport and/or storage of a radioactive medium generating flammable gases and/or explosives via radiolysis, comprising a plurality of canisters intended to contain the radioactive medium, each canister defining an inner storage space accessible via an opening for filling the medium, on which plug-forming means are mounted. According to the invention, the device also comprises a structure forming a chamber, and means for placing in communication allowing a fluid communication to be set up between the inner storage space and the chamber.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.

Abstract: A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.

Abstract: A light-emitting device includes a carrier; a first light-emitting element formed on a first portion of the carrier, including: a first MQW structure configured to emit a first light with a first dominant wavelength; a second MQW structure configured to emit a second light with a second dominant wavelength on the first MQW structure; wherein the first MQW structure and the second MQW structure both comprise InxGa1-xP or InxGa1-xAs, wherein 0<x<1; and a second light-emitting element, formed on a second portion on of the carrier, including a light-emitting stacked layer configured to emit a third light with a third dominant wavelength, wherein the third light is blue, wherein a difference between the first dominant wavelength and the second dominant wavelength is 5 nm to 30 nm.

Abstract: A light emitting diode is provided, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.

Abstract: A light emitting device including a substrate, a first conductive type semiconductor layer on the substrate, at least one InxGa1?xN layer (0<x<0.2) on the first conductive type semiconductor layer, at least one GaN layer directly on the at least one InxGa1?N layer (0<x<0.2), an active layer on the at least one GaN layer, a second conductive type semiconductor layer on the active layer, and a transparent ITO (Indium-Tin-Oxide) layer on the second conductive type semiconductor layer.

Abstract: Disclosed is a semiconductor light emitting device including a first conductive semiconductor layer including an n-type dopant, an active layer, and a second to sixth conductive semiconductor layers including a p-type dopant. The third to sixth conductive semiconductor layers includes an AlGaN-based semiconductor on the active layer, and the second conductive semiconductor layer includes a GaN-based semiconductor layer on the sixth conductive semiconductor layer. The active layer includes plurality of quantum barrier layers and plurality of quantum well layers and includes a cycle of 2 to 10. The plurality of quantum well layers include an InGaN semiconductor and at least one of the plurality of quantum barrier layers includes a GaN-based semiconductor. The sixth conductive semiconductor layer has a thickness of about 5 nm to about 100 nm.

Abstract: A group III nitride semiconductor optical device 11a has a group III nitride semiconductor substrate 13 having a main surface 13a forming a finite angle with a reference plane Sc orthogonal to a reference axis Cx extending in a c-axis direction of the group III nitride semiconductor and an active layer 17 of a quantum-well structure, disposed on the main surface 13a of the group III nitride semiconductor substrate 13, including a well layer 28 made of a group III nitride semiconductor and a plurality of barrier layers 29 made of a group III nitride semiconductor. The main surface 13a exhibits semipolarity. The active layer 17 has an oxygen content of at least 1×1017 cm?3 but not exceeding 8×1017 cm?3. The plurality of barrier layers 29 contain an n-type impurity other than oxygen by at least 1×1017 cm?3 but not exceeding 1×1019 cm?3 in an upper near-interface area 29u in contact with a lower interface 28Sd of the well layer 28 on the group III nitride semiconductor substrate side.

Abstract: A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.

Abstract: Apparatus and methods are provided. A first apparatus includes: a semiconductor film; and at least one semiconductor nanostructure, including a heterojunction, configured to modulate the conductivity of the semiconductor film by causing photo-generated carriers to transfer into the semiconductor film from the at least one semiconductor nanostructure. A second apparatus includes: a semimetal film; and at least one semiconductor nanostructure, including a heterojunction, configured to generate carrier pairs in the semimetal film via resonant energy transfer, and configured to generate an external electric field for separating the generated carrier pairs in the semimetal film.

Abstract: A light-receiving element includes a III-V group compound semiconductor substrate, a light-receiving layer having a type II multi-quantum well structure disposed on the substrate, and a type I wavelength region reduction means for reducing light in a wavelength region of type I absorption in the type II multi-quantum well structure disposed on a light incident surface or between the light incident surface and the light-receiving layer.

Abstract: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.

Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: An organic electroluminescence device and a method for manufacturing the same are disclosed. The organic electroluminescence device includes a transparent substrate, a semiconductor layer including a source region, a channel region and a drain region, a gate insulating film having first contact holes on the source and drain regions and formed on the substrate including the semiconductor layer, a gate electrode formed on the gate insulating film above the channel region, an interlayer insulating film having second contact holes on the source and drain regions and formed on an entire surface of the gate insulating film including the gate electrode, and a source electrode and a drain electrode formed on the interlayer insulating film to be electrically connected to the source and drain regions through the first and second contact holes, wherein at least one of the source electrode and the drain electrode is formed to cover the semiconductor layer.

Abstract: Disclosed are semiconducting compounds having one or more phthalimide units and/or one or more head-to-head (H-H) substituted biheteroaryl units. Such compounds can be monomeric, oligomeric, or polymeric, and can exhibit desirable electronic properties and possess processing advantages including solution?processability and/or good stability at ambient conditions.

Abstract: A current-amplifying transistor device is provided, between an emitter electrode and a collector electrode, with two organic semiconductor layers and a sheet-shaped base electrode. One of the organic semiconductor layers is arranged between the emitter electrode and the base collector electrode, and has a diode structure of a p-type organic semiconductor layer and an n-type p-type organic semiconductor layer. A current-amplifying, light-emitting transistor device including the current-amplifying transistor device and an organic EL device portion formed in the current-amplifying transistor device is also disclosed.

Abstract: A first light-emitting layer of a first organic electroluminescent element is disposed in common to a second organic electroluminescent element, a second light-emitting layer of the second organic electroluminescent element is disposed in contact with the first light-emitting layer and in the cathode side, and the first light-emitting layer is a light-emitting layer having an electron trapping property.

Abstract: Organic light-emitting elements each have the following structure: a transparent anode, a functional layer including a charge injection layer and an organic light-emitting layer, and a transparent cathode are layered on a substrate in the stated order; a bank defines a formation area of the organic light-emitting layer; the charge injection layer is a metal oxide layer formed by oxidizing an upper surface portion of the anode composed of the metal layer, and a portion of the charge injection layer that is positioned under the area is depressed so as to form a recess; and the upper peripheral edge of the recess is covered with a covering portion of the bank.

Abstract: An organic EL element includes a hole injection layer yielding excellent hole conduction efficiency, and comprises: an anode; a cathode; a functional layer disposed between the anode and the cathode, and including a light-emitting layer containing organic material; the hole injection layer disposed between the anode and the functional layer; and a bank defining an area in which the light-emitting layer is to be formed, wherein the hole injection layer includes tungsten oxide, tungsten atoms constituting the tungsten oxide include both tungsten atoms with a valence of six and tungsten atoms with a valence less than six, the hole injection layer includes a crystal of the tungsten oxide, a particle diameter of the crystal being on an order of nanometers, an inner portion of the hole injection layer is depressed to define a recess, and an upper peripheral edge of the recess is covered with a part of the bank.

Abstract: An organic semiconductor thin film including an organic semiconductor material that is easily synthesized, and is chemically and physically stable, and shows a high carrier mobility, an organic semiconductor device and an organic field effect transistor including the organic semiconductor thin film are provided. An organic semiconductor thin film of the invention includes a compound represented by the following formula 1: wherein, in formula (1), X is oxygen, sulfur or selenium.

Abstract: An object of the invention is to provide an organic electroluminescence (EL) element formed using a relatively stable new electron injection material in an atmosphere of approximately ordinary pressure. An organic EL element of a preferable embodiment is an organic EL element including a supporting substrate, an anode, a light-emitting layer, an electron injection layer, and a cathode in this order, in which the electron injection layer is formed by applying an ink including an ionic polymer so as to form a film, and the cathode is formed by applying an ink including a material which forms the cathode so as to form a film or transferring a conductive thin film which forms the cathode.

Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.

Abstract: An organic electroluminescence display device includes a p-doped layer doped with a P-type dopant on an anode electrode, a P-type dopant diffusion blocking layer on the p-doped layer, a first hole transport layer on the P-type dopant diffusion blocking layer, a light emitting layer on the first hole transport layer, an electron transport layer on light emitting layer, and a cathode electrode on the electron transport layer, the p-doped layer, the P-type dopant diffusion blocking layer, the hole transport layer, and the light emitting layer being stacked in the stated order on the anode.

Abstract: The drain voltage of a transistor is determined depending on the driving voltage of an element connected to the transistor. With downsizing of a transistor, intensity of the electric field concentrated in the drain region is increased, and hot carriers are easily generated. An object is to provide a transistor in which the electric field hardly concentrates in the drain region. Another object is to provide a display device including such a transistor. End portions of first and second wiring layers having high electrical conductivity do not overlap with a gate electrode layer, whereby concentration of an electric field in the vicinity of a first electrode layer and a second electrode layer is reduced; thus, generation of hot carriers is suppressed. In addition, one of the first and second electrode layers having higher resistivity than the first and second wiring layers is used as a drain electrode layer.

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region. By providing a microvoid in the source region and the drain region formed in an oxide semiconductor film, hydrogen contained in the channel region of an oxide semiconductor film can be captured in the microvoid.

Abstract: Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole. Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.

Abstract: A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al2O3 or a ZnO or a Group-III Nitride-based material, and a first structure disposed on a first side of the substrate comprising of AlInGaN-based and/or ZnMgO based semiconducting materials. The first structure further includes an intentional current-conducting sidewall channel or facet whereupon additional semiconductor layers, dielectric layers and electrode layers are disposed and upon which the field effect of the dielectric and electrode layers occurs thus allowing for a high density monolithic integration of a multiplicity of discrete devices on a common substrate thereby enabling a higher power density than in conventional lateral power MOSFET devices.

Abstract: A semiconductor device includes first and second conductive layers over an insulating surface, a first insulating layer over the first and second conductive layers, first and second oxide semiconductor layers over the first insulating layer, third and fourth conductive layers over the first oxide semiconductor layer, a second insulating layer over the third and fourth conductive layers, and a fifth conductive layer over the second insulating layer. In the semiconductor device, the third conductive layer is electrically connected to the second conductive layer, the fifth conductive layer is electrically connected to the fourth conductive layer, the first oxide semiconductor layer has a region overlapping with the first conductive layer, the second oxide semiconductor layer has a region overlapping with the fifth conductive layer, and the second oxide semiconductor layer has a region intersecting with the second conductive layer.

Abstract: The disclosure provides a p-type metal oxide semiconductor material. The p-type metal oxide semiconductor material has the following formula: In1?xGa1?yMx+yZnO4+m, wherein M is Ca, Mg, or Cu, 0<x+y?0.1, 0?m?3, and 0<x, 0?y, or 0?x, 0<y, and wherein a hole carrier concentration of the p-type metal oxide semiconductor material is in a range of 1×1015˜6×1019 cm?3.

Abstract: A semiconductor device according to one embodiment of this invention includes: a semiconductor chip; a plurality of external connection pads and a plurality of first test pads, both of which are formed in a central region of a top surface of the semiconductor chip; a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.

Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.

Abstract: An OLED display includes a first polysilicon layer pattern on a substrate having a first gate electrode, a second gate electrode, and a first capacitor electrode, a gate insulating layer pattern, a second polysilicon layer pattern including a first active layer, a second active layer, and a capacitor polycrystalline dummy layer, a third amorphous silicon layer pattern including first source and drain resistant contact layers on a predetermined region of the first active layer, second source and drain resistant contact layers on a predetermined region of the second active layer, and a capacitor amorphous dummy layer on the capacitor polycrystalline dummy layer, and a data metal layer pattern including first source/drain electrodes, second source/drain electrodes, and a second capacitor electrode.

Abstract: A display apparatus includes a backlight module, a panel module, and a plurality of double-sided adhesive tapes. The backlight module includes a bezel. The frame has a supporting surface. The panel module includes a glass substrate and a plurality of chips. The glass substrate is disposed on the supporting surface. An edge of the glass substrate has a bonding region. The chips are disposed at the bonding region. The chips and the supporting surface are respectively located at two opposite sides of the glass substrate. The double-sided adhesive tapes are disposed between the supporting surface and the bonding region. Each of the double-sided adhesive tapes is located at a gap between two adjacent chips.

Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness

Abstract: Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Abstract: A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of the semiconductor pattern portion and a second contact hole exposing a second region of the semiconductor pattern portion. A gate electrode is disposed on the first insulating layer. A second insulating layer covers the gate electrode and has a third contact hole exposing the first region and a fourth contact hole exposing the second region. A source electrode is formed on the second insulating layer and connected to the first region, and a drain electrode is formed on the second insulating layer and connected to the second region.

Abstract: An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved.

Abstract: A substrate includes a thin film transistor (TFT) which includes an active layer, a gate electrode, a source electrode, and a drain electrode; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed on the second insulating layer, and including a first region for opening the second insulating layer and a second region for opening one of the source and drain electrodes, the first region and the second region being integrally connected; and a first electrode connected to one of the source and drain electrodes, and disposed so as to cover the first region and the second region.

Abstract: An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer.

Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.