Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

Abstract: A group III nitride compound semiconductor light emitting device that inhibits occurrence of dislocation in a strain relaxation layer in forming a group III nitride compound semiconductor layer on a thin GaN substrate, and a method for producing the same are provided. A light emitting device 100 comprises a support substrate 10, a GaN substrate 20, an n-type contact layer 30, a strain relaxation layer 40 (n-type InGaN layer), a light emitting layer 50, a p-type clad layer 60, and a p-type contact layer 70. The GaN substrate 20 has a thickness in a range of from 10 nm to 10 ?m. The strain relaxation layer 40 (n-type InGaN layer) has an In composition ratio X in a range of from larger than 0 to 3%.

Abstract: To provide a semiconductor device which allows a plurality of semiconductor chips to let a current flow uniformly therethrough and a method of manufacturing the same. The semiconductor device in accordance with one embodiment comprises a plurality of first semiconductor chips and a circuit board, mounted with the plurality of the first semiconductor chips, having first and second wiring conductors electrically connected to the plurality of first semiconductor chips. The plurality of first semiconductor chips are connected in parallel together with the first and second wiring conductors so as to construct a first parallel circuit. The plurality of first semiconductor chips are arranged on the circuit board according to an on-resistance of the plurality of first semiconductor chips so that a uniform current flows through the plurality of first semiconductor chips.

Abstract: The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode.

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: A semiconductor light-emitting device that is high in luminous efficiency and that emits light which is high in color rendering property includes a semiconductor light-emitting element that emits blue light; a green fluorescent substance that absorbs the blue light and emits green light; and an orange fluorescent substance that absorbs the blue light and emits orange light, fluorescence emitted by the green fluorescent substance and the orange fluorescent substance having an emission spectrum that has a peak wavelength of not less than 540 nm and not more than 565 nm and that satisfies the relation of 0.70>PI(90)/PI(MAX)>0.55, where PI(MAX) represents an emission intensity at the peak wavelength, and PI(90) represents an emission intensity at a wavelength 90 nm longer than the peak wavelength.

Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.

Abstract: An electro-optical device includes: a pixel region that is formed on a substrate and in which a light emitting element that has a first electrode, a second electrode and a light emitting layer formed between the first electrode and the second electrode is arranged; a partition wall portion that is formed above the substrate and located on an outer side of the pixel region; a connecting line that is formed above the substrate and located on an outer side of the partition wall portion; and a connecting section that is formed above the substrate and electrically connects the second electrode to the connecting line, wherein the second electrode covers and extends over the pixel region and the partition wall portion and does not overlap the connecting line in a planar view.

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: A light emitting device includes: one or plural light emitting elements having plural electrodes; a chip-like insulator surrounding the one or plural light emitting elements from a side surface side of the one or plural light emitting elements; and plural terminal electrodes electrically connected one-to-one with the plural electrodes, and having protrusions each protruding from a peripheral edge of the chip-like insulator.

Abstract: A display device includes a pixel area including pixels arranged in a matrix and having a horizontal resolution of 350 ppi or more and a color filter layer overlapping with the pixel area. The pixels each include a first transistor whose gate is electrically connected to a scan line and whose one of a source and a drain is electrically connected to a signal line; a second transistor whose gate is electrically connected to the other of the source and the drain of the first transistor and whose one of a source and a drain is electrically connected to a current-supplying line; and a light-emitting element electrically connected to the other of the source and the drain of the second transistor. The first and second transistors each have a channel formation region including a single crystal semiconductor.

Abstract: A highly reliable light-emitting device or lighting device is provided. Further, a light-emitting device or lighting device with a high manufacturing yield is provided. Provided is a light-emitting device having a contact structure which includes a separation layer having a shape typified by a reverse tapered shape in which an outline of the bottom portion is inside an outline of an upper portion and which utilizes the difference between an amount of a light-emitting layer extending inside the outline and that of an upper electrode extending inside the outline. Further, when the outline of the separation layer which forms the contact portion has a depression and a projection, the length of the contact portion can be increased, and thus, contact resistance can be reduced.

Abstract: The present invention relates to a plurality of light emitting diodes connected in series to elevate the working voltage and to enable the devices to be connected directly to the AC voltage sources. The LED device has five pluralities of series-connected diodes. Four pluralities of series-connected diodes are arranged to at as a rectifier bridge so the fifth plurality of diodes is always forward biased and energized. The light emitting diodes in the device are arranged to accommodate various AC line voltages, diode operating voltages, and diode reverse breakdown voltages. The plurality of diodes was manufactured by first etching epitaxial layer to the insulating substrate to isolate individual diodes, and then use metal lines to interconnect them according to the layout design. The number of die-attach and wire-bonding steps used in the subsequent chip array and lamp manufacturing process is therefore greatly reduced or eliminated.

Abstract: An organic electroluminescence device includes a first electrode, a second electrode located on a light extraction side and having a metal film, and an organic compound layer provided between the first electrode and the second electrode and including an emission layer. In addition, a first inorganic protective layer is in direct contact with the second electrode and has a specified thickness.

Abstract: In accordance with certain embodiments, an electric device includes a flexible substrate having first and second conductive traces on a first surface thereof and separated by a gap therebetween, an electronic component spanning the gap, and a stiffener configured to substantially prevent flexing of the substrate proximate the gap during flexing of the substrate.

Abstract: A light emitting device including a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, a second conductive type semiconductor layer on the active layer, an electrode layer on the second conductive type semiconductor layer, a first electrode on the first conductive type semiconductor layer, and a second electrode on the second conductive type semiconductor layer and in an opening, the opening being in the electrode layer, wherein the second electrode has a first portion in the opening and a second portion extending from the first portion and overlapping at least a portion of the first electrode.

Abstract: A light emitting device includes a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a light extraction structure that extracts light from the light emitting structure. The light extraction structure includes at least a first light extraction zone and a second light extraction zone, where a period and/or size of first concave and/or convex structures of the first light extraction zone is different from a period and/or size of second concave and/or convex structures of the second light extraction zone.

Abstract: Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.

Abstract: In a light-emitting device, an insulating separation layer whose upper portion protrudes more than a bottom portion in a direction parallel to a substrate is provided on and in contact with a common wiring provided over the substrate. An EL layer provided over the separation layer on the common wiring is physically divided by the separation layer. An upper electrode layer formed in the same position is also physically divided by the separation layer and is in contact with the common wiring in a region overlapped with the most protruding portion of the separation layer. Such a common wiring may be used as an auxiliary wiring. Further, such a light-emitting device may be applied to a lighting device and a display device.

Abstract: There is herein described a phosphor for use in LED applications and particularly in phosphor-conversion LEDs (pc-LEDs). The phosphor has a composition represented by (Y1-xCex)3(Al1-yScy)5O12 wherein 0<x?0.04 and 0<y?0.6 and can be as applied to an LED as a transparent sintered ceramic or used in a powder form. By adjusting the composition of the phosphor, the phosphor can be made to emit light in the green to yellow regions of the visible spectrum upon excitation by a blue-emitting InGaN LED.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a p-side electrode; an n-side electrode; and a fluorescent body layer. The p-side electrode is provided on a second surface side of the semiconductor layer. The n-side electrode is provided on the second surface side of the semiconductor layer. The fluorescent body layer is provided on a first surface side of the semiconductor layer and contains a plurality of fluorescent bodies configured to be excited by emission light of the light emitting layer and emit light of a different wavelength from the emission light and a bonding material integrating the plurality of fluorescent bodies and configured to transmit the emission light. An average spacing between adjacent ones of the fluorescent bodies is narrower than a peak wavelength of emission light of the light emitting layer.

Abstract: A light emitting device and method of manufacture are described. In an embodiment, the light emitting device includes a micro LED device, a light pipe around the micro LED device to cause internal reflection of incident light from the micro LED device within the light pipe, and a wavelength conversion layer comprising phosphor particles over the light pipe. Exemplary phosphor particles include quantum dots that exhibit luminescence due to their size, or particles that exhibit luminescence due to their composition.

Abstract: A light-emitting device comprising: a light-emitting stacked layer having a first conductivity type semiconductor layer; a light-emitting layer formed on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer formed on the light-emitting layer; a transparent conductive oxide layer formed on the second conductivity type semiconductor layer wherein the transparent conductive oxide layer having a first portion and a second portion and the upper surface of the transparent conductive oxide layer is a textured surface; a first electrode formed on the second portion of the transparent conductive oxide layer, and a second electrode formed on the first conductivity type semiconductor layer; a planarization layer formed on the first portion of the transparent conductive oxide layer, and the second electrode; and a reflective layer formed on the planarization layer that is devoid of the first electrode and the second electrode.

Abstract: Arrangements of solid state light sources for color-mixing, and light sources including the same, are provided. A substrate has a plurality of different color LED chips coupled thereto. The emitted light is mixed to produce a white light output. The LED chips are arranged on the substrate in a manner that improves color-mixing, for example, by forming LED sets including one or more LED chips of different colors, by skewing the LED chips, and/or by forming a non-rectangular array or a circular array of LED sets and/or chips. The color-mixing LED arrangement may be used in a lamp or other light source together with collimating optics to collimate and further mix the color-mixed light output from the LED arrangement. The color-mixing LED arrangement may be provided as a single package with multiple LED chips or as multiple packages of one or more LED chips.

Abstract: The present invention provides an optical device, and the optical device comprises a luminous element and a gradient-index nanoparticle layer and scattering particles composed by particles stack with different refractive indexes and particle sizes. The luminous element has a light emitting surface. The refractive indexes of the nanoparticle layers decrease bottom up. The nanoparticles based gradient-index nanoparticle layer comprises a plurality of dielectric layers with different refractive index, and the dielectric scattering particle layers are stacked upward from the light emitting surface to let the gradient-index nanoparticle layer and scattering particles cover the light emitting surface. The method for manufacturing the abovementioned optical device is also disclosed.

Abstract: Disclosed is a LED lighting apparatus with one or more swivel connections. The LED lighting apparatus includes a housing with at least one end, at least one light emitting diode extending along the housing and at least one end cap. The end cap has an opening with a sidewall to cap the end of the housing and a surface opposite the opening and spanning the sidewall. At least two pin connectors extend from the surface and are connectable to a standard fluorescent or incandescent light fixture. Various configurations are described such that the housing will rotate within the end caps with application of a rotational force after connection of the pin connectors to the light fixture to adjust the light output direction of the LED lighting apparatus.

Abstract: An optoelectronic device comprises a semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer, a first electrode electrically connecting with the first semiconductor layer, a second electrode electrically connecting with the second semiconductor layer, wherein there is a smallest distance D1 between the first electrode and the second electrode, a third electrode formed on a portion of the first electrode and electrically connecting with the first electrode and a fourth electrode formed on a portion of the first electrode and on a portion of the second electrode, and electrically connecting with the second electrode, wherein there is a smallest distance D2 between the third electrode and the fourth electrode, and the smallest distance D2 is smaller than the smallest distance D1.

Abstract: A semiconductor light emitting device includes: a first conductive semiconductor layer including first and second areas; an active layer disposed on the second area; a second conductive semiconductor layer disposed on the active layer; first and second electrode branches disposed on the first and second conductive semiconductor layers, respectively; a first electrode pad electrically connected to the first electrode branch and disposed on the first electrode branch; and a second electrode pad electrically connected to the second electrode branch and disposed on the second electrode branch.

Abstract: It is an object of the present invention to provide an organic electroluminescence element which can be easily produced and has a good light-emitting property and a good lifetime property, and a method for producing the same. That is, the present invention provides the organic electroluminescence element comprising an anode, a light-emitting layer and a cathode, and further comprising a metal doped molybdenum oxide layer provided between the anode and the light-emitting layer; and the method for producing the organic electroluminescence element including a stacking step to obtain a metal doped molybdenum oxide layer by simultaneously depositing molybdenum oxide and a dopant metal on another layer which constitutes the element.

Abstract: Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed.

Abstract: An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n? drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n? drift region and a p collector region, and extends between the n? drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.

Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer.

Abstract: A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is formed at a front surface of the epitaxy semiconductor layer. After the LIGBT is formed, a backside thinning is performed to remove the semiconductor substrate. An implantation is performed from a backside of the epitaxy semiconductor layer to form a heavily doped semiconductor layer. The heavily doped semiconductor layer is of a second conductivity type opposite the first conductivity type.

Abstract: A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction, a plurality of interconnection lines extending on the substrate in a second direction, a pad electrically connected to the plurality of interconnection lines and configured to apply an external voltage, a plurality of metal contacts electrically connecting the interconnection lines and the plurality of bit lines, and a plurality of bit line contacts that are in contact with the active region and electrically connect the plurality of bit lines and the active region, wherein a size of at least some of the bit line contacts and/or at least some of the metal contacts vary based on a distance of the respective bit line contact or the metal contact from the pad.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.

Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).

Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

Abstract: A structure having a plurality of conductive regions insulated electrically from each other comprises a movable piece supported movably above the upper face of the conductive region, the movable piece having an electrode in opposition to the conductive region, the structure being constructed to be capable of emitting and receiving electric signals through the lower face of the conductive region, the plural conductive regions being insulated by sequentially connected oxidized regions formed from an oxide of a material having through-holes or grooves.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.

Abstract: A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction.

Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.