Abstract: The present application disclosed various embodiments of improved performance optically coated semiconductor devices and the methods for the manufacture thereof and includes at least one semiconductor wafer having at least a first surface, a first layer of low density, low index of refraction optical material applied to at least the first surface of the semiconductor wafer, and a multi-layer optical coating applied to the first layer of low density, low index of refraction material, the multi-layer optical coating comprising alternating layers of low density, low index of refraction materials and high density, high index of refraction materials.

Abstract: A solid-state imaging element including a semiconductor substrate that has a light reception portion performing a photoelectric conversion of an incident light; an oxide layer that is formed on a surface of the semiconductor substrate; a light shielding layer that is formed on an upper layer further than the oxide layer via an adhesion layer; and an oxygen supply layer that is disposed between the oxide layer and the adhesion layer and is formed of a material which shows an oxidation enthalpy smaller than that of a material forming the oxide layer.

Abstract: An image sensor packaging structure with a low transmittance encapsulant is provided. The image sensor packaging structure includes a substrate, a chip, a transparent lid, and the low transmittance encapsulant. The chip is combined with the substrate. The transparent lid is adhered to the chip and cover above a sensitization area of the chip to form an air cavity. The low transmittance encapsulant is formed on the substrate and encapsulates the chip and the transparent lid so as to accomplish the package of the image sensor packaging structure. Due to the feature of prohibiting from light passing through the low transmittance encapsulant, the arrangement of the low transmittance encapsulant can avoid the light from outside interfere the image sensing effect of the image sensor. Therefore, the quality of the image sensing can be ensured.

Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).

Abstract: An electroconductive element includes a substrate having a first wavy surface and a second wavy surface, and an electroconductive layer formed on the first wavy surface, wherein the electroconductive layer forms an electroconductive pattern, and the first wavy surface and the second wavy surface satisfy the following relationship: 0?(Am1/?m1)<(Am2/?m2)?1.8. Am1 is a mean amplitude of vibrations of the first wavy surface, Am2 is a mean amplitude of vibrations of the second wavy surface, ?m1 is a mean wavelength of the first wavy surface, and ?m2 is a mean wavelength of the second wavy surface.

Abstract: Provided are light detection devices and methods of manufacturing the same. The light detection device includes a first conductive pattern on a surface of a substrate, an insulating pattern on the substrate and having an opening exposing at least a portion of the first conductive pattern, a light absorbing layer filling the opening of the insulating pattern and having a top surface disposed at a level substantially higher than a top surface of the insulating pattern, a second conductive pattern on the light absorbing layer, and connecting terminals electrically connected to the first and second conductive patterns, respectively.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad.

Abstract: A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C1 and C2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C1, C2 and C is about 5%-20% of the predetermined region A.

Abstract: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolation (STI) structures, which are formed by dielectric material filling trenches formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels. The mandrels are removed, leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the STI structures. The substrate is doped, forming source, drain and channel regions. A gate is formed over the channel region. In some embodiments, the STI structures and the strips of material facilitate the formation of transistors having a high breakdown voltage.

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.

Abstract: On a wiring conversion part connected to a first conductive film and a second conductive film each functioning as a wiring, a hollow portion is formed inside the second conductive film. A first transparent conductive film provided on the second conductive film is formed so as to cover an upper surface of the second conductive film and an end surface thereof exposed on the hollow portion, and so as not to cover an outer peripheral end surface of the second conductive film. A second transparent conductive film which is a layer above the first transparent conductive film is connected to the second conductive film and the first conductive film, so that the first conductive film and the second conductive film are electrically connected.

Abstract: A substrate has a first surface and a second surface opposed to each other. A blind hole is formed in the substrate extending from the first surface at a location for each through via. Each blind hole is filled with a conductive filler; a deepest part of each filler forming a bump portion made of a solder material. Part of the substrate extending from the second surface is removed to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding solder bump.

Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract: A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.

Abstract: A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Abstract: The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer.

Abstract: A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.

Abstract: An apparatus comprising a first substrate and a second substrate. The first substrate has disposed thereon a first feature. The second substrate has disposed thereon a second feature. The first feature is configured to interlock with the second feature such that the first substrate and the second substrate are aligned by the first and the second features within a predefined accuracy.

Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.

Abstract: A power semiconductor module having a housing with first connecting devices for arrangement on an external cooling component, at least one substrate carrier with power-electronics circuit arrangements constructed thereon and electrical terminal elements extending therefrom to second connecting devices for connection to external power lines, wherein the first and/or the second connecting devices are constructed as essentially hollow cylindrical metallic molded die-cast parts which are connected to the housing by injection molding.

Abstract: A lead frame includes: a chip-mounting region provided on a front surface; a lead region including a plurality of concave and convex sections arranged in an in-plane direction of the chip-mounting region; and a terminal arranged in the concave section. A thickness of the lead region from the front surface is smaller than a thickness of the terminal from the front surface.

Abstract: An ultrasound flow meter unit arranged to measure a fluid flow rate is provided, where the unit comprises a circuit board 502 which comprises an electronic circuit, a first ultrasound transducer 506 and a first conducting path 564 electrically connected to first ultrasound transducer and the electronic circuit, wherein the circuit board is a multi-layer circuit board and the first conducting path 564 is arranged at least partially between a first layer 581 and a second layer 582. In a further embodiment, there is provided an upper electrically conducting layer 586 and/or a lower electrically conducting layer 588 which substantially covers, respectively, the upper surface of the first layer 581 and the lower surface of the second layer 582.

Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.

Abstract: A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier.

Abstract: A first substrate provided with a receiving area made from a first metallic material is supplied. A second substrate provided with an insertion area comprising a base surface and at least two bumps made from a second metallic material is arranged facing the first substrate. The bumps are salient from the base surface. A pressure is applied between the first substrate and the second substrate so as to make the bumps penetrate into the receiving area. The first metallic material reacts with the second metallic material so as to form a continuous layer of an intermetallic compound having a base formed by the first and second metallic materials along the interface between the bumps and the receiving area.

Abstract: In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage.

Abstract: To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact having a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess.

Abstract: A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.

Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

Abstract: A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substract, a semiconductor chip by which the flip chip was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components.

Abstract: A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y1 that is nominally equal to the transverse dimension of the contact area opening, and the second portion having a transverse dimension Y2 that is greater than the transverse dimension of the contact area opening. The active layers can be bit lines or word lines for a 3-D memory device, or other active layers in integrated circuits.

Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.