Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.

Abstract: In general, in one aspect, the invention relates to a method for binding input/output (I/O) objects to nodes. The method includes receiving a request to use an I/O device from a process, determining a resource to service the request, generating a first I/O object corresponding to the resource, wherein the first I/O object is unbound, and generating a proc object, wherein the proc object comprises a reference to the process requesting to use the I/O device. The method also includes sending the first I/O object and the proc object to a Non-Uniform Memory Access (NUMA) I/O Framework, determining that the process is executing on a first NUMA node, selecting the first NUMA, binding the first I/O object to the first NUMA node, and servicing the request by processing, on the first NUMA node, the resource corresponding to the first I/O object.

Abstract: A programmable link training and status state machine is disclosed. The programmable finite state machine includes extra states, or shadow states, which are strategically used to debug a system design or to accommodate unexpected behavior, such as when the specifications of the design change. The programmable finite state machine is thus a mechanism to design in correctable logic, enabling the logic to be corrected in silicon and used in succeeding iterations of a product line.

Abstract: Embodiments of the invention relate to configuring a virtualization controller in SAN data storage system without disrupting I/O operations. One aspect of the invention concerns a method that comprises establishing a first data path between a host and a storage controller in the same communication zone wherein the storage controller comprises storage devices for storing data; adding a virtualization controller to the zone wherein the virtualization controller maps the storage devices to virtual volumes and establishes a second data path between the host and the storage devices through the virtual volumes; removing the first data path in response to the host detecting the second data path; and performing I/O operations between the host and the storage devices through the second data path.

Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.

Abstract: Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.

Abstract: A queue control circuit controls the placement and retrieval of a plurality of tasks in a plurality of types of virtual queues. State registers are associated with respective tasks. Each of the state registers stores a task priority order, a queue ID of a virtual queue, and the order of placement in the virtual queue. Upon receipt of a normal placement command ENQ_TL, the queue control circuit establishes, in the state register for the placed task, QID of the virtual queue as the destination of placement and an order value indicating the end of the queue. When a reverse placement command ENQ_TP is received, QID of the destination virtual queue and an order value indicating the start of the queue are established. When a retrieval command DEQ is received, QID is cleared in the destination virtual queue.

Abstract: This disclosure describes techniques to improve a user experience in a Wireless Display (WD) system. The WD system includes a source device that provides media data to one or more sink devices. The techniques are directed toward reducing end-to-end latency in the WD system while improving video playback quality at the sink devices. More specifically, the techniques include customized buffering at the sink devices based on application awareness for the media data. The techniques include learning the type of application for the media data, and adjusting the size of buffers in the processing pipeline to achieve an appropriate balance between smoothness and latency for the application type. For example, when the media data is for a video playback application, the techniques include increasing the buffer size to increase smoothness in the video playback application.

Abstract: An electronic device executes a certain process when first data for instructing the electronic device to begin the certain process has been received from an external apparatus, and stops the certain process when the external apparatus has not been detected as a certain apparatus and when a first time has elapsed since the certain process was executed, even if second data for instructing the electronic device to stop the certain process has not been received.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.

Abstract: A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

Abstract: A mobile device uses sensor data related to the type of surface in contact with the mobile device to determine an action to perform. The sensors, by way of example, may be one or more of a microphone and noise generator, a light based proximity sensor, and pressure sensors, such as dielectric elastomers, configured to detect a texture of the surface, and/or pressure waves produced by setting the mobile device down or by a noise generator and reflected by the surface. The mobile device may identify the type of surface and perform the action based on the type of surface. The mobile device may further determine its location based on the sensor data and use that location to identify the action to be performed. The location may be determined using additional data, e.g., data not related to determining the type of surface with which the mobile device is in contact.

Abstract: A method and storage device for assessing execution of trim commands are provided. In one embodiment, a trace of trim and write commands sent to a storage device are obtained. For each trim command in the trace, a subsequent write command to a same logical block address (LBA) as the trim command is identified, and an elapsed time between the trim and write commands is calculated. This information can be used to display a histogram and/or to optimize when the storage device executes trim commands and/or when the host device issues trim commands.

Abstract: Technology is provided for selecting a master node of a node group in a storage system. The technology can gather data regarding visibility of one or more storage devices of the storage system to one or more active nodes of the node group, determine a maximum visibility value for the node group and selecting an active node with associated visibility value equal to the maximum visibility value as the master node of the node group.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: A system and method for serial communication between a USB host and a USB device. The USB device is a handheld microprocessor equipped device capable of functioning as a general purpose computer. The USB host places the USB device in an accessory mode which permits the USB host to transmit its configuration information to the USB device. This configuration information can include the manufacturer and product ID of the USB host. The USB device, in accessory mode, uses this configuration information to acquire and load application software (such as by downloading the software from the Internet). The application software enables the USB device to provide a programmable function to the USB host and to enable applications on the USB host and device to communicate on a peer-to-peer basis via the USB communications channel.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task.

Abstract: In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

Abstract: According to one aspect, a backplane controller of a storage backplane is disclosed, the storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices. In one embodiment, the backplane controller is operative to perform functions that include detecting activity status on a first serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to a host bus adapter (HBA), according to a first drive slot assignment. The backplane controller is further operative to detect an activity status on a second serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to the HBA, according to a second drive slot assignment.

Abstract: A computing device and method for hot swapping media are provided. The computing device comprises: a swap media socket; a power supply for powering the swap media socket; a swap media detect apparatus enabled to undergo a state change when swap media removal occurs at the swap media socket; a switch in communication with the swap media detect apparatus, the switch enabled to disconnect the power supply from the swap media socket in response to the state change; and a processor in communication with the swap media detect apparatus, the processor enabled to turn off the power supply in response to the state change.

Abstract: A transportation system includes a passenger vehicle, a mobile device, and a mobile device dock that couples the mobile device to the passenger vehicle. The mobile device dock includes a base coupled to the passenger vehicle and a cradle configured to receive the mobile device. The cradle is coupled to the base to move relative to the base.

Abstract: A verified cluster configuration is collected and stored by a central management entity. Servers within the cluster are connected to network cables, where each of the servers has at least one network port and memory storing a port identification code for each network port, and where each network cable has memory storing a cable identification code. For each verified connection between a network cable and a network port, the port identification code is stored in the memory of the network cable and the cable identification code is stored in the memory of the corresponding server. The data identifying each connection is stored by the central management entity and includes the port identification code for a particular network port in association with the network cable identification code for the corresponding network cable. Any miswiring of the configuration is identified by the central management entity and easily corrected by the administrator.

Abstract: Service dependency is determined for services in a service oriented architecture (SOA) environment. The steps in determining service dependency include: recording a first triple describing a first service call where the first service calls the second service, and determining the first service is dependent upon the second service based, at least in part, upon the first triple. The recording action is performed dynamically, the recording occurring when the first service call is made. Other related steps include recording the first triple to a timestamp indicating when the first service call is made.

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract: Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: Each node in a clustered array is the owner of a set of zero logical disks (LDs). Thinly-provisioned VVs (TPVVs) are partitioned so each is mapped to a group of zero LDs from different sets of zero LDs. When there is a change in ownership, the affected zero LDs are switched one at a time so only a group of the TPVVs is affected each time.

Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

Abstract: A nonvolatile memory system includes a memory area including a nonvolatile memory apparatus divided into a plurality of blocks, and a controller configured to control the memory area. The controller groups the plurality of blocks of the memory area according to wear level and whether each of the plurality of blocks is in use, and manages the blocks of each group in wear level order.

Abstract: A storage device that is aware of I/O transactions and stored data is provided. In one embodiment, a storage device identifies a type of data stored in each logical partition of the storage device. When the storage device receives a request from the host device to access a logical partition of the memory, the storage device handles the request based on the identified type of data stored in the logical partition. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: A flash memory controller, a non-transitory computer readable medium and a method for performing operations with a flash memory device, the method may include receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device; selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation.

Abstract: Modified tracks for write requests to a sequential access storage medium in a sequential access storage device are cached in a non-volatile storage, which is a faster access device than the sequential access storage medium. A request queue includes destage requests to destage the modified tracks in the non-volatile storage device to the sequential access storage medium and read requests to access read requested tracks from the sequential access storage medium. A comparison is made of a current position of a read/write mechanism with respect to physical locations on the sequential access storage medium of the tracks subject to the destage requests indicated in the request queue. A determination is made of one of the destage requests to process based on the comparison. The modified track for the determined destage request is written from the non-volatile storage device to the sequential access storage medium.

Abstract: A method, a computer readable medium and a system for managing flash memory. The method may include receiving multiple data sectors from an interface; writing the multiple data sectors into a data buffer that is nonvolatile; creating a pointer in a data management structure that is stored in a metadata buffer that is nonvolatile, for each data sector corresponding to a storage location of the data sector in the data buffer; if a predefined condition is reached, merging data sectors stored in the data buffer with data sectors that are already stored in a sequential nonvolatile portion of the flash memory device, wherein the sequential nonvolatile portion differs from the data buffer.

Abstract: A flash memory device includes a flash memory unit; and a control unit configured to perform control so that data having a size smaller than a block size of the flash memory unit is sequentially written to the flash memory unit.

Abstract: Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred.

Abstract: A system, a method and a non-transitory computer readable medium for generating soft information. The method may include performing a first set of read attempts of flash memory cells using a first set of read thresholds to provide first read results; calculating for each flash memory cell in response to the first read results, first cell information indicative of a first change-inducing read threshold; performing a second set of read attempts of the flash memory cells using a second set of read thresholds to provide second read results, calculating for each flash memory cell in response to the second read results, second cell information indicative of a second change-inducing read threshold; and generating, for each flash memory cell soft information in response to the first cell information and the second cell information of the flash memory cell.

Abstract: A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.

Abstract: A storage device comprising a non-volatile memory for storing data, and an input device that is operative to select an operating mode of the storage device prior to mounting the storage device, such that each operating mode represents a different type of storage device. A controller interfaces with the input device to establish the selected operating mode of the storage device once the storage device is mounted.

Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.

Abstract: The embodiments described herein are directed to efficient logging and checkpointing of metadata managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The metadata managed by the volume layer, i.e., the volume metadata, is illustratively organized as a multi-level dense tree metadata structure, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the volume metadata. Each volume metadata entry may be a descriptor that embodies one of a plurality of types, including a data entry and an index entry, and a hole (i.e., absence of data) entry.

Abstract: Methods and systems for a network device having a plurality of base-ports, each base-port having a plurality of sub-ports configured to operate independently as a port for sending and receiving information using one of a plurality of network links at a plurality of rates complying with a plurality of protocols. The network device includes a ternary content addressable memory (TCAM) module for storing a plurality of entries for routing frames that are received for the plurality of sub-ports complying with the plurality of protocols. Each TCAM entry has an associated history value that is used by a processor for the network device to purge TCAM entries based on an age of the TCAM entries.

Abstract: A storage system includes a first storage device, and a second storage device retrieving stored data at higher speeds than the first storage device. The storage system further includes a feature calculation unit calculating feature data based on a data content of storage target data, a data management unit storing the storage target data and managing a storing position thereof based on the feature data calculated from the storage target data, and a duplication determination unit determining whether or not the same storage target data as the storage target data to be newly stored is already stored in the first storage device. In a case that the same storage target data as the storage target data to be newly stored is already stored in the first storage device, the data management unit stores the storage target data already stored in the first storage device into the second device.

Abstract: Techniques for deduplication of virtual machine files in a virtualized desktop environment are described, including receiving data into a page cache, the data being received from a virtual machine and indicating a write operation, and deduplicating the data in the page cache prior to committing the data to storage, the data being deduplicated in-band and in substantially real-time.

Abstract: In one embodiment, a storage system includes a server system having a processor and a local buffer pool for storing instances for use in catalog requests, and a Direct Access Storage Device (DASD) subsystem electrically coupled to the server system and to at least one DASD, wherein the at least one DASD is adapted for providing at least one catalog configured according to a Basic Catalog Structure (BCS), wherein the at least one catalog includes at least one of: a user catalog including information related to locations of user data sets and system data sets stored to the at least one DASD, and a tape volume catalog including information related to locations of user data sets and system data sets stored to at least one tape medium, and wherein the data storage system is adapted for providing Record Level Sharing (RLS) for the at least one catalog stored to the at least one DASD.

Abstract: A method and apparatus for determining a disk array enclosure serial number comprising determining logical unit number (LUN) information regarding disk drives within a disk array of a storage system, determining port information for the storage system comprising the disk array, correlating the LUN information with the port information to uniquely identify each disk drive, and defining a disk array enclosure serial number using the LUN and port information related to each disk drive.

Abstract: An apparatus comprising a plurality of storage nodes comprising a plurality of corresponding storage disks and configured to store data in a distributed manner between the storage disks that achieves a Redundant Array of Independent Disks-0 (RAID0) like performance based on positioning information and without indexing the distributed data. A network component comprising a storage disk configured to maintain a plurality of physical files for different user data that are mapped to different volumes, wherein the volumes are distributed between the storage disk and a second storage disk based on a RAID0 like data distribution scheme without being indexed.

Abstract: A mechanism is provided for optimizing and enhancing performance for parity based storage, particularly redundant array of independent disk (RAID) storage. The mechanism optimizes a repetitive pattern write command for performance for storage configurations that require parity calculations. The mechanism eliminates the need for laborious parity calculations that are resource intensive and add to IO latency. For repetitive write commands that span across the full stripe of a RAID5 or similar volume, the mechanism calculates parity by looking at the pattern and the number of columns in the volume. The mechanism may avoid the XOR operation altogether for repetitive pattern write commands. The mechanism may enhance secure delete operations that use repetitive pattern write commands by eliminating data reliability operations like parity generation and writing altogether.