Abstract: Shared cache modules, systems, and methods are provided herein. The shared cache module is useable with at least one initiator on a serial attached small computer system interface system. The shared cache module includes a memory device and a memory interface. The memory device assigns each of the at least one initiator to a portion of a cache memory on the memory device. The memory interface indexes the assignment and communicates with the at least one initiator to perform a memory task.

Abstract: A system and method for auditing memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A determination is made whether content in the memory card is acceptable or unacceptable. A first volume name of the memory card is rewritten to the second volume name in response to determining the content in the memory card is acceptable.

Abstract: A multi-level cache comprises a plurality of cache levels, each configured to cache I/O request data pertaining to I/O requests of a different respective type and/or granularity. A cache device manager may allocate cache storage space to each of the cache levels. Each cache level maintains respective cache metadata that associates I/O request data with respective cache address. The cache levels monitor I/O requests within a storage stack, apply selection criteria to identify cacheable I/O requests, and service cacheable I/O requests using the cache storage device.

Abstract: Various embodiments for improving data storage and retrieval performance, for a tiered storage environment having levels corresponding to storage performance, are provided. In one embodiment, by way of example only, reference count information of at least one data segment maintained in the tiered storage environment is used to determine which of the levels in the tiered storage environment the at least one data segment will be assigned. Those of the at least one data segment having higher reference counts are assigned to a higher performance level than those having lower reference counts.

Abstract: A methods and device for accessing virtual machine (VM) data are described. A computing device for accessing virtual machine comprises an access request process module, a data transfer proxy module and a virtual disk. The access request process module receives a data access request sent by a VM and adds the data access request to a request array. The data transfer proxy module obtains the data access request from the request array, maps the obtained data access request to a corresponding virtual storage unit, and maps the virtual storage unit to a corresponding physical storage unit of a distributed storage system. A corresponding data access operation may be performed based on a type of the data access request.

Abstract: A system and method of detecting cache inconsistencies among distributed data centers is described. Key-based sampling captures a complete history of a key for comparing cache values across data centers. In one phase of a cache inconsistency detection algorithm, a log of operations performed on a sampled key is compared in reverse chronological order for inconsistent cache values. In another phase, a log of operations performed on a candidate key having inconsistent cache values as identified in the previous phase is evaluated in near real time in forward chronological order for inconsistent cache values. In a confirmation phase, a real time comparison of actual cache values stored in the data centers is performed on the candidate keys identified by both the previous phases as having inconsistent cache values. An alert is issued that identifies the data centers in which the inconsistent cache values were reported.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The write-back cache holds data being written back to main memory for a period of time prior to writing the data to main memory. If the data is cached in the write-back cache, the data is removed from the write-back cache and forwarded to the requesting processor. The cache coherency state in the coherency directory entry for the data is updated to reflect the current cache coherency state of the data based on the requesting processor's intended use of the data.

Abstract: Destaging storage tracks from each rank that includes a greater than a predetermined percentage of a predetermined amount of storage space with respect to a current amount of storage space allocated to each rank until the current amount of storage space used by each respective rank is equal to the predetermined percentage of the predetermined amount of storage space. The destage storage tracks are declined from being destaged from each rank that includes less than or equal to the predetermined percentage of the predetermined amount of storage space rank.

Abstract: The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.

Abstract: An integrated circuit (IC) may include a cache memory, and a cache memory controller coupled to the cache memory. The cache memory controller may be configured to receive a cache miss associated with a memory location, issue pre-fetch requests, each pre-fetch request having a quality of service (QoS), and determine if a pre-fetch request has issued for the memory location associated with the cache miss.

Abstract: A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

Abstract: A memory access system may be used to relay data between an electronic device and external memory. The memory access system may include write buffers which may receive and write information from the electronic device to the external memory. The memory access system may also include read buffers which may gather data from the external memory and send it to a main processing component of the electronic device for processing. The memory access system may be configured so that the main processing component of the electronic device may gather data from the write buffers of the memory access system when a condition is satisfied.

Abstract: Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memory. Otherwise, the control circuit sends the memory request to the cache memory.

Abstract: A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: Methods and systems are disclosed for providing resource sharing in a computing environment using file descriptor isomorphism. The methods and systems may perform a method in a computing environment having processor systems executing processes. The method may include receiving a request from a first process to access a first resource. Further, the method may include generating a first Global File Descriptor (GFD) that references a first entry in a GFD table, the first GFD entry including a reference to a first entry in a resource descriptor table pointing to the first resource. Based on the request, at least one GFD field associated with the first GFD entry is configured. Thus, methods and systems may manage access by the first process to the first resource using the first GFD entry.

Abstract: Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

Abstract: A system and method described herein allows a virtual tape library (VTL) to perform multiple simultaneous or parallel read/write or access sessions with disk drives or other storage media, particularly when subject to a sequential SCSI-compliant layer or traditional limitations of VTLs. In one embodiment, a virtualizing or transaction layer can establish multiple sessions with one or more clients to concurrently satisfy the read/write requests of those clients for physical storage resources. A table or other data structure tracks or maps the sessions associated with each client and the location of data on the physical storage devices.

Abstract: A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.

Abstract: A judgment apparatus includes a processor that executes a procedure, the procedure including obtaining a plurality of pieces of data having a certain relationship with a specific number or more of pieces of data included in a first data group, in the case that a piece of data included in a second data group different from the first data group does not have the certain relationship with the specific number or more of pieces of data included in the second data group, judging whether the piece of data has the certain relationship with the specific number or more of pieces of data included in the obtained plurality of pieces of data, and storing the piece of data in a storage device in the case that the piece of data is judged to have the given relationship with the specific number or more pieces of data.

Abstract: Techniques for system recovery using change tracking are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer implemented method for providing system recovery using change tracking comprising receiving a request to write to electronic storage, identifying a region in the electronic storage region associated with the write request, setting a region indicator identifying the electronic storage region as dirty, and setting one or more portion indicators identifying one or more dirty portions of the electronic storage region.

Abstract: In traditional storage arrays, the number of clones permitted inside the storage array may be limited by the amount of available storage. Further, clones stored on the array may require significant storage resources. Thus, the number of clone stored by the storage array may also be limited by the storage system memory and not just by the disk space. Accordingly, example embodiments of the present invention allow for creating and maintaining a plurality (e.g., an unlimited number) of thin asynchronous clones in storage, even if replica storage is capable of storing only a limited number of snapshots. Further, example embodiments of the present invention allow clones to be freely attached and detached from the replication environment for various purposes.

Abstract: Various embodiments provide systems and methods for migrating data. One system includes a small computer system interface logical unit number (SCSI LUN) configured to store protected data, a processor, and memory configured to store a peer-to-peer remote copy (PPRC) application. The processor is configured to execute the PPRC application to modify the protection in transmitted data and received data. One method includes receiving unprotected data, utilizing a PPRC application to add protection to the data to generate protected data, and storing the protected data in a protected SCSI LUN. Another method includes receiving, at a protected SCSI LUN, a request to transmit protected data, utilizing a PPRC application to strip the protection from the protected data to generate unprotected data, and transmitting the unprotected data to an unprotected SCSI LUN.

Abstract: Aspects of the subject matter described herein relate to maintaining consistency in a storage system. In aspects, one or more objects may be updated in the context of a transaction. In conjunction with updating the objects, logical copies of the objects may be obtained and modified. A request to write the updated logical copies is sent to a storage controller. The logical copies do not overwrite the original copies. In conjunction with sending the request, a data structure is provided for the storage controller to store on the disk. The data structure indicates the one or more objects that were supposed to be written to disk and may include verification data to indicate the content that was supposed to be written to disk. During recovery, this data structure may be used to determine whether all of the object(s) were correctly written to disk.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for efficient backup using hashes One of the methods includes forming an image of a storage device, wherein contents of blocks of the storage device are restorable from the contents of blocks of the image. The method includes generating a first plurality of hash values, each hash value generated from contents of a block of the image. The method includes selecting a block of the storage device. The method includes generating a hash value from the contents of the selected block. The method includes determining whether the hash value occurs in the plurality of hash values. The method also includes generating an entry in the image in response to the determination.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: Method and system for providing information regarding a plurality of storage devices managed by a plurality of storage servers are provided. The storage space at the storage devices is presented to a plurality of computing systems as logical storage space. A plurality of searchable data structures having a plurality of data object types are stored at a temporary memory storage device of a management console that interfaces with the plurality of computing systems and the storage servers. Each data object type stores information regarding the storage device. The searchable data structure includes information regarding the storage devices and the logical storage space presented to the computing systems. A lock data structure for tracking locks that are assigned for accessing information pertaining to a storage server and a data object type is maintained to prevent unauthorized access to at least one of the searchable data structures.

Abstract: Described herein are technologies for optimizing different cache configurations of a size-configurable cache. One configuration includes a base cache portion and a removable cache portion, each with different latencies. The latency of the base cache portion is modified to correspond to the latency of the removable portion.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.

Abstract: A provisioning apparatus for provisioning a storage volume to a shared file system in a storage area network, wherein the storage area network comprises a plurality of server nodes and a plurality of storage devices, wherein each server node comprises a shared file system operable for sharing by each of the plurality of server nodes and each server node is operable for communicating with each of the plurality of storage devices, the apparatus comprising: a creator component creates a new storage volume; a messenger component instructs the server nodes to detect the new storage volume and to allocate a device name; an instructor component instructs the shared file system to assign the storage volume to the shared file system; an instructor component associates the device name with the shared file system; a receiver component receives a unique identifier for the storage volume and the device name; and a builder component for determines a relationship between the unique identifier and the device name, storing th

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: A technique provides multi-tenancy within a data storage apparatus. The technique involves dividing, by processing circuitry, storage units of the data storage apparatus into multiple groups of storage units. The technique further involves forming, by the processing circuitry, segregated slice pools from the multiple groups of storage units. Each segregated slice pool is formed from a different group of storage units. The technique further involves allocating, by the processing circuitry, slices from the segregated slice pools to mutually exclusive sets of virtual storage processors (VSPs) on the data storage apparatus. Each mutually exclusive set of VSPs operates as a separate tenant of the data storage apparatus.

Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration. The memory includes a structure that extends through multiple layers of the memory. A method includes storing information at the data storage device. The information identifies a location associated with a variation of the structure. The method further includes accessing the information.

Abstract: A data storage device is disclosed comprising a non-volatile memory comprising a plurality of sectors. A partition map is evaluated that identifies a partition accessed through a plurality of logical block addresses (LBAs), where each LBA maps to a fraction of a sector. A partition offset is determined for the partition relative to a boundary of one of the sectors. N write commands are received each having a write offset relative to a corresponding sector. When the write offset for X of the N write commands matches the partition offset, at least part of the partition is moved to align at least part of the partition to a boundary of one of the sectors.

Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.

Abstract: The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume, located at a second storage system. The hypervolume directs input/output (I/O) from the servers to a primary physical volume comprising either the first or second physical volume, and the primary physical volume may be changed, transparently to the servers, to the other of the first or second physical volume. The present disclosure, in another embodiment, relates to a method for moving operation of a storage device from one data storage location to a second data storage location. A hypervolume is used to redirect input/output (I/O) from the a plurality of servers from the one physical volume to another.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: A method for assigning data in a plurality of physical storage resources for an information handling system is disclosed. The plurality of physical storage resources includes a first tier and a second tier with a lower performance and cost relative to capacity than the first tier. A tier manager hosted on the information handling system and in electronic communication with the plurality of physical storage resources is configured to: determine a seek distance value, operation rate, operation size value, and elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier.

Abstract: A system including a storage device and a controller. The storage device is configured to store a map. The map relates (i) a first portion of a memory to a first order of first dimensions, and (ii) a second portion of the memory to a second order of second dimensions. The first portion of the memory and the second portion of the memory are non-overlapping. Each of the first dimensions and each of the second dimensions has corresponding memory cells in the memory. The controller is configured to control access to the first portion of the memory according to the first order of first dimensions while controlling access to the second portion of the memory according to the second order of the second dimensions.

Abstract: A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.

Abstract: A system, method, and computer program product are provided for efficiently performing a scan operation. In use, an array of elements is traversed by utilizing a parallel processor architecture. Such parallel processor architecture includes a plurality of processors each capable of physically executing a predetermined number of threads in parallel. For efficiency purposes, the predetermined number of threads of at least one of the processors may be executed to perform a scan operation involving a number of the elements that is a function (e.g. multiple, etc.) of the predetermined number of threads.

Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

Abstract: An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Abstract: An information processing device, comprises: a connection unit connected to a predetermined storage part storing therein startup mode determination information in which a startup mode corresponds to a specified hardware configuration and/or software configuration is configured and the plurality types of suspend data, each of which corresponds to the respective startup mode; a startup mode determination part for reading the startup mode determination information and determining the startup mode when being powered on; a suspend data obtaining part for selecting the suspend data corresponds to the startup mode determined by the startup mode determination part and obtaining the selected suspend data in the storage part; a starting up part for performing a startup process using the suspend data obtained by the suspend data obtaining part; and a startup mode updating part for updating the startup mode configured in the startup mode determination information after completion of the startup process.

Abstract: A server system having an auto-reset mechanism is provided. The server system comprises a power control circuit, a power processing circuit, a CPLD and a control circuit. The power control circuit generates a control signal. The power processing circuit operates according to the control signal to receive a first power and generate a second power. The CPLD receives the second power and operates accordingly and generates a power reset signal when the CPLD finishes a update process. The control circuit controls the power control circuit to stop to generate the control signal to turn off the power processing circuit to further disable the CPLD in a certain time period according to the power reset signal and controls the power control circuit to activate the power processing circuit to further activate and reset the CPLD after the certain time period.

Abstract: A host device and method for securely booting the host device with operating system code loaded from a storage device are provided. In one embodiment, a host device is in communication with a storage device having a private memory area storing boot loader code and a public memory area storing operating system code. The host device instructs the storage device to initiate a boot mode and receives the boot loader code from the storage device. The host device executes the boot loader code which performs a security check and executes the operating system code loaded from the storage device only if the security check is successful.

Abstract: An electronic device and a method of booting the electronic device is provided. The electronic device and method include a power supply unit, a volatile memory, a non-volatile memory, and a controller which, in response to power being supplied by the power supply unit, performs booting in a first booting mode that uses a suspend image stored in the volatile memory; and, in response to an error occurring in the first booting mode, performs a next booting in a second booting mode that uses a suspend image stored in the non-volatile memory. In response to power being supplied by the power supply unit, performing booting in a first booting mode that uses a suspend image stored in the volatile memory; and in response to an error occurring in the first booting mode, performing a next booting in a second booting mode using a suspend image stored in the non-volatile memory.

Abstract: Probes are instrumented into a boot sequence of a computer system to enable probing of the boot sequence. As part of the boot sequence, a value stored in a predetermined storage location within a boot device is read and, if the value indicates that probing of the boot sequence has been enabled, executable code for probing the boot sequence is injected into the boot sequence. Outputs of the probing during the boot process are collected into a buffer and analyzed after the completion of the boot process.

Abstract: The method is for downloading applications takes place in a network that has a server, a mobile terminal, a trusted operator and preferably, a personal computer. In the method a user selects an application to be downloaded at his computer or mobile terminal. The user then sends a request to the server for downloading the selected application to the mobile terminal. The server sends a message to the mobile terminal with instructions for downloading of the application. This message is sent via a trusted operator in order to ensure a secure downloading. Thereafter, the application is downloaded to the mobile terminal.