Abstract: A pivotal assembly applied to a board includes a first board, a first pivotal member, and a pivotal plate. The first pivotal member is fixed to the first board and has a first retaining structure. The pivotal plate is pivotally connected to the first pivotal member and has a first protrusion. The first protrusion is retained in the first retaining structure, so as to make the first board limitedly rotate to be perpendicular or parallel to the pivotal plate.

Abstract: Embodiments of the present disclosure provide an assembly comprising circuitry of a wireless module disposed on a first region of a circuit board, and circuitry of a host controller module disposed on a second region of the circuit board. The first region is removably coupled to the second region.

Abstract: A circuit board unit includes a printed circuit board and a terminal block mounted on the printed circuit board and connecting a power module and an electrical wire together. The terminal block includes a terminal connection part to be directly connected to the power module, and a wire connection part to be connected to the electrical wire. In the printed circuit board, a hole having an orthographic projection area larger than that of the terminal connection part as viewed in plane is formed. The terminal connection part is positioned below or above the hole of the printed circuit board.

Abstract: An electrical or electro-optical assembly comprising a substrate comprising an insulating material, at least one conductive track present on at least one surface of the substrate, at least one electrical or electro-optical component connected to at least one of the at least one conductive track, and a continuous coating comprising one or more plasma-polymerized polymers completely covering the at least one surface of the substrate, the at least one conductive track and the at least one electrical or electro-optical component.

Abstract: A connection assembly includes a connection member and a switch. The connection member includes a serial attached small computer system interface (SAS) connector electronically connected to the switch. When the switch is electronically connect to the motherboard, the switch transmits signals from the motherboard to a hard disk drive backplane via the SAS connector. When the switch is electronically connect to the hard disk drive backplane, the switch transmits signals from the hard disk drive backplane to the motherboard via the SAS connector.

Abstract: In accordance with embodiments of the present disclosure, a backplane for electrically coupling modular information handling resources to one or more other information handling resources, may include a printed circuit board, a first plurality of slots, and a second plurality of slots. The printed circuit board may have a first surface and a second surface opposite the first surface. The first plurality of slots may be mounted to the first surface and the second plurality of slots may be mounted to the second surface, such that each of the second plurality of slots are offset from an adjacent slot of the first plurality of slots in a direction parallel to a plane defined by the first surface and each of the second plurality of slots are rotated approximately 180 degrees from an adjacent slot of the first plurality of slots.

Abstract: The invention discloses a keyboard device including a keyboard and a support for protecting the keyboard or accommodating a portable information processing device. The support of the invention is capable of rotate in a direction away from the keyboard to be at a supporting state. The support of the invention is also capable of rotate in a direction toward the keyboard to cover whole of the top of the keyboard.

Abstract: The embodiments disclosed herein describe a method of a controller to maintain a substantially constant average output current at the output of a switching power converter. In one embodiment, the controller uses a regulation voltage that corresponds to the primary peak current regulation level to regulate the average output current.

Abstract: A power electronic converter for high/medium voltage direct current power transmission and reactive power compensation comprises a primary converter unit and an auxiliary converter unit, the primary converter unit including at least one primary converter limb including first and second DC terminals for connection in use to a DC network and an AC terminal, the or each primary converter limb defining first and second limb portions, each limb portion including at least one primary module, the or each primary module including at least one primary switching element connected to an energy storage device, the auxiliary converter unit including at least one auxiliary converter limb including at least one auxiliary module including a plurality of auxiliary switching elements connected to the energy storage device of a corresponding primary module in the first limb portion of a respective primary converter limb, the primary switching elements of the primary modules being controllable in use to switch the respective ene

Abstract: An inverter circuit 40 with reduced loss in semiconductor elements when starting up, having switching elements Q1 and Q2 in series, and connected to both ends of a direct current power source circuit 30 having direct current power sources Psp and Psn in series, and including an alternating current output terminal U connected to a connection point of the switching elements, an alternating current output terminal V connected to a connection point of the direct current power sources, a bidirectional switch element S1, connected between the alternating current output terminal U and a terminal R of an alternating current power source 1, and a bidirectional switch element S2, connected between the alternating current output terminal U and a terminal S of the alternating current power source, causing the bidirectional switch elements to turn on and off when starting up.

Abstract: The disclosure relates to a passive power factor correction circuit. The passive power factor correction circuit comprises: a filtering device being used for decreasing high order harmonic of an input current; a resonance device being coupled to the filtering device for controlling operation time of the input current; and a suppression device being coupled to the resonance device for suppressing ripple of the input current.

Abstract: A power supply circuit system includes a ring oscillator provided with a variable resistance circuit, a charge pump circuit outputting a boosted voltage in response to an oscillation output signal from the ring oscillator, a voltage regulator circuit adjusting the boosted voltage from the charge pump circuit, a first current comparator circuit comparing a first current flowing through the voltage regulator circuit with a first reference current, a second current comparator circuit comparing the first current with a second reference current, and a control circuit outputting control signals to control a resistance value of the variable resistance circuit in accordance with a first comparison signal from the first current comparator circuit and a second comparison signal from the second current comparator circuit.

Abstract: A photovoltaic power conditioning system and method is provided. The system includes an isolated DC/DC converter (41), a DC/AC inverter (42), and a sine filter (43). The isolated DC/DC converter (41) receives a DC voltage from a solar cell through a parallel connection structure and converts the DC voltage into another DC voltage and then outputs the converted DC voltage through a series connection structure. The DC/AC inverter (42) converts the DC voltage output from the isolated DC/DC converter into an AC voltage. The sine filter (43) performs sine filtering on the AC voltage output from the DC/AC inverter and outputs the filtered AC voltage. The system employs a topology allowing it to be responsible for part of the output capacity, thereby significantly reducing the required capacity and increasing the system efficiency, so that the system can be applied to small and large-capacity photovoltaic power generation.

Abstract: A direct current to direct current (DC/DC) converter includes a resonant converter stage, a buck stage, and a processor apparatus. The resonant converter stage includes a bridge circuit. The buck stage is configured to output an output voltage and an output current, is electrically connected in series with the resonant converter stage, and includes a buck switch. The processor apparatus is configured to sense the output voltage and the output current, and, based on the sensed output voltage and the sensed output current, to perform one of: (a) fixing a switching frequency of the bridge circuit to a predetermined maximum switching frequency and controlling the output voltage by controlling a duty cycle of the buck switch, and (b) fixing the duty cycle of the buck switch to a predetermined duty cycle and controlling the output voltage by controlling the switching frequency of the bridge circuit.

Abstract: A power converter and a method of operation thereof is disclosed including an input, an output, a sensor unit, a switched power converter, and a processor module. The power converter may convert an input power into an output power. The power converter may sense real-time measurements of the input power and the output power to determine a real-time calculated efficiency. The power converter may chop the input power into sized and positioned portions of the input power based on a plurality of determined operating parameters. The power converter may determine the operating parameters based on the real-time calculated efficiency and on a plurality of other operating factors/conditions.

Abstract: A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices.

Abstract: A device for producing an alternating current output voltage from a high-frequency, square-wave input voltage comprising, high-frequency, square-wave input a matrix converter and a control system. The matrix converter comprises a plurality of electrical switches. The high-frequency input and the matrix converter are electrically connected to each other. The control system is connected to each switch of the matrix converter. The control system is electrically connected to the input of the matrix converter. The control system is configured to operate each electrical switch of the matrix converter converting a high-frequency, square-wave input voltage across the first input port of the matrix converter and the second input port of the matrix converter to an alternating current output voltage at the output of the matrix converter.

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

Abstract: A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit including PMOS transistors.

Abstract: A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer.

Abstract: A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.

Abstract: The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract: Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming the programmable impedance element can include: (i) receiving a program command to be executed on the programmable impedance element; (ii) performing a program operation on the programmable impedance element in response to the program command; (iii) determining if the program operation successfully programmed the programmable impedance element; and (iv) performing an erase operation for programming the programmable impedance element in response to the program operation failing to successfully program the programmable impedance element.

Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.

Abstract: A method of designing a cross-point non-volatile memory device including memory elements arranged in (N×M) matrix, each of the memory elements including a variable resistance element and a bidirectional current steering element connected in series with the variable resistance element, the method comprises the step of: when an absolute value of a low-resistance state writing voltage is VR and an absolute value of a current flowing through the variable resistance element having changed to a low-resistance state by application of the low-resistance state writing voltage to both ends of the variable resistance element in a high-resistance state is Ion, and a relationship between a voltage V0 applied to both ends of the bidirectional current steering element and a current I flowing through the bidirectional current steering element is approximated as |V0|=a×Log(I)+b, deciding N, M, VR, Ion, a, and b such that b?VR/2>a×[Log {(N?1)×(M?1)}?Log(Ion)] is satisfied (S101).

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Abstract: A memory device can include a plurality of memory cells, each including a dynamic section configured to store data dynamically, and a programmable impedance section comprising at least one programmable element programmable between at least two different data states, the programmable impedance section configured to establish a data value stored by the dynamic section in response to a recall signal.

Abstract: A semiconductor device includes NAND gates and switches to form a circuit to hold data, and a capacitor electrically connected to the circuit via a transistor to store the data held in the circuit. The transistor has a channel formation region including an oxide semiconductor.

Abstract: A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.

Abstract: Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM cell are further disclosed. A gate electrode serves as the gate for a pull-down transistor and a pull-up transistor, a gate of a first partial dummy transistor, and a gate of a second partial dummy transistor. A butt contact connects a long contact to the gate electrode. The long contact further connects to a drain of a pull-down transistor, a drain of a pull-up transistor, a drain of a first pass gate, and a drain of a second pass gate, wherein the first pass gate and the second pass gate share an active region.

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract: An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.

Abstract: A magnetoresistance element is disclosed. The magnetoresistance element includes a magnetic tunnel junction portion configured by sequentially stacking a perpendicularly magnetized first magnetic body, an insulation layer, and a perpendicularly magnetized second magnetic body. The second magnetic body has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer side interface. A heat assist layer that heats the second magnetic body with a heat generated based on a current flowing through the magnetic tunnel junction portion is further provided.

Abstract: A MRAM bit cell including a first magnetic tunnel junction (MTJ) connected to a first data line and a second MTJ connected to a second data line. The MRAM bit cell further includes a first transistor having a first terminal connected to the first MTJ and a second terminal connected to the second MTJ. The MRAM bit cell further includes a second transistor having a first terminal connected to a driving line and a second terminal connected to the first MTJ. The MRAM bit cell further includes a third transistor having a first terminal connected to the driving line and a second terminal connected to the second MTJ. A method of using the MRAM bit cell is also described.

Abstract: According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel barrier layer formed between the storage layer and the reference layer and containing O, and an underlayer formed on a side of the storage layer opposite to the tunnel barrier layer. The reference layer comprises a first reference layer formed on the tunnel barrier layer side and a second reference layer formed opposite the tunnel barrier layer. The second reference layer has a higher standard electrode potential than the underlayer.

Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

Abstract: In a nonvolatile memory that stores data in two or more different data storage formats, such as binary and MLC, a separation scheme is used to distribute blocks containing data in one data storage format (e.g. binary) so that they are separated by at least some minimum number of blocks using another data storage format (e.g. MLC).

Abstract: A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.

Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.

Abstract: A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares common support circuitry (e.g., selecting/deselecting transistors) with one or more upper drain select devices of other strings of memory cells. The support circuitry (e.g., selecting/deselecting transistors) for lower drain select devices can also be shared between a plurality of strings of memory cells.

Abstract: A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy.

Abstract: A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells.

Abstract: A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.