Abstract: A register circuit adapted to store data is described. The register circuit comprises a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and a delay element coupled to the master-slave flip flop, the delay element receiving a reference clock signal and generating a slave clock signal the slave clock signal which is delayed relative to a master clock signal. A method of storing data in a register circuit is also described.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.

Abstract: A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line.

Abstract: An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor.

Abstract: Signals generated by an array of photodiodes are applied to the inputs of corresponding edge detection circuits. Each edge detection circuit generates an output that changes state in response to a detected edge of the photodiode generated signal. The edge detection circuits may be formed by toggle flip-flop circuits. The outputs of the edge detection circuits are logically combined using exclusive OR logic to generate an output. The exclusive OR logic may be formed by a cascaded tree of exclusive OR circuits.

Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.

Abstract: A charge pump device includes a charge pump circuit, for generating an output voltage according to a driving signal, a comparing circuit, for generating a comparison result according to the output voltage and a reference voltage, a detecting circuit, for detecting a frequency range of a ripple of the output voltage according to the comparison result and generating a detection result, and a driving stage, for generating the driving signal according to the comparison result, and adjusting a driving capability corresponding to the driving signal according to the detection result.

Abstract: A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result.

Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Abstract: Apparatus, and associated method, for improving packet data communications upon a communication path including a radio-link. Determination is made of the conditions on the radio-link when selecting the optimal size of a transmission window within which to transmit packets of data. And, retransmission time-out values are also selected responsive to the indications of the radio-link conditions.

Abstract: A system for power amplification is presented. A tile array power amplifier (PA) module for use in a phased array includes a module with a radio frequency (RF) side and a direct current (DC) side, a top edge, a left edge a bottom edge and a right edge. Four PA dies are mounted in each quadrature of the RF side of the module. RF input connectors are mounted on the RF side to bring RF inputs to the PA dies. RF output connectors are mounted to the DC side to output amplified signals from the PA dies. The PA dies are formed, in part, with gallium nitride (GaN) and are mounted to the module in such a way that the tile array PA module is able to generate about 100 watts of RF power and dissipate about 200 watts of heat while amplifying signals over 10 GHz.

Abstract: In general, an RF power amplifier comprises a controller, a driver, a splitter, a final stage, and a combiner coupled together to function as the RF power amplifier. One or more of the above components are arranged on one or more motherboards, e.g., a printed circuit board (PCB). A heat sink defines a base of the RF power amplifier, and in some embodiments includes at least two grooves formed therein, wherein the electrical components of the splitter and electrical components of the controller fit within one or more of the grooves so that these components can substantially disposed within the heat sink. In some embodiments, a power rail is also provided, and is also disposed substantially within the heat sink. The power rail groove of the heat sink and the carrier of the final stage provide an EMI shield of the power rail.

Abstract: A multi-mode amplifier system includes a supply converter and a multi-stage amplifier. The supply converter is configured to generate a plurality of varied supply signals according to an output power mode. The multi-stage amplifier is configured to generate an RF output signal from an RF input signal according to the varied supply signals.

Abstract: The electronic circuit (1) includes, in an automatic gain control loop, an input amplifier (2), an AGC unit connected to the amplifier output to detect the amplitude of an output signal and a unit (10) for attenuating an input signal of the amplifier based on an adaptation signal (VAGC) from the AGC unit. The attenuation unit includes a means of comparing the adaptation signal to a reference signal (VREF) and for supplying an attenuation current as a function of the difference between the adaptation and reference signals, to a diode-connected PMOS replica transistor (M2), which is connected by a source to a common mode voltage (VCM) dependent on the input signal of the amplifier. The replica transistor controls a PMOS shunt transistor (M1) defining a shunt resistance connected to the amplifier input, whose resistive value depends on the attenuation current passing through the replica transistor.

Abstract: In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.

Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.

Abstract: A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A ring oscillator has a plurality of elementary units connected in cascade and linked in order to make a chain with the respective output terminals connected to the input terminals of the successive elementary units of the chain, the elementary units being crossed by a cyclic signal during a time period of activation, each of said elementary units comprising an auxiliary recovery terminal for temporarily resetting each elementary unit during each loop of said cyclic signal, said auxiliary recovery terminal being connected to an output terminal of a successive elementary unit of the chain.

Abstract: A constant-temperature piezoelectric oscillator includes: a piezoelectric vibrator; an oscillation circuit; a frequency voltage control circuit; a temperature control section; and an arithmetic circuit, wherein the temperature control section includes a temperature-sensitive element, a heating element, and a temperature control circuit, the frequency voltage control circuit includes a voltage-controlled capacitance circuit capable of varying the capacitance value in accordance with the voltage, and a compensation voltage generation circuit, and the arithmetic circuit makes the compensation voltage generation circuit generate a voltage for compensating a frequency deviation due to a temperature difference between zero temperature coefficient temperature Tp of the piezoelectric vibrator and setting temperature Tov of the temperature control section based on a frequency-temperature characteristic compensation amount approximate formula adapted to compensate the frequency deviation, and then applies the voltage t

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: A light-emitting device module includes a temperature variable device including a temperature control surface subjected to temperature control, a light-emitting device including a first electrode and mounted on a portion of the temperature control surface, a first terminal for supplying electric power to the first electrode, and a wire that causes the first terminal and the first electrode to conduct. The wire is thermally connected to the other portion of the temperature control surface.

Abstract: An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Abstract: In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.

Abstract: An output matching circuit for electronic amplifiers in the form of an integrated circuit is disclosed. The integrated circuit includes a first circuit, a second circuit, and a power sampling coupler. The first circuit is coupled to output of a first amplifier. The first circuit comprises a first matching section and an impedance inverter. The second circuit is coupled to output of a second amplifier, wherein the second circuit comprises a second matching section. The power sampling coupler is coupled to the first circuit and the second circuit, wherein the first circuit, the second circuit, and the power sampling coupler are fabricated as a single integrated circuit.

Abstract: An improved implementation of a 2×4 divider formed from a bridge junction is described. The bridge junction uses parallel and series connections of coaxial lines to eliminate impedance transformers that are normally required in a 2×4 power divider. In a preferred embodiment, the bridge junction is comprised of UT-085 coax transmission lines, 20 gauge twin lead wire and SB-805-61 ferrite beads with ½ turn windings to provide a wide bandwidth, compact, high power and rugged arrangement.

Abstract: A multilayer power splitter includes a laminate contains two transformers, wherein the inductance ratio of the primary side and secondary side of the first transformer is adjusted to 4:1, whereas the inductance ratio of the primary side and secondary side of the second transformer is adjusted to 1:1. An input port is branched into two for inputting to the primary side and secondary side of the first transformer in opposite phases, with one output made from the first output port. The other output from the first transformer is branched into two for inputting to the primary side and secondary side of the second transformer in opposite phases, with one output made from the second output port and the other output made from the third output port.

Abstract: A high-frequency module enabling sufficient attenuation over a wide frequency range outside of a passband includes a triplexer including a combination of an LPF, a BPF, and HPFs arranged to demultiplex a signal input from a common terminal into a first communication signal, a second communication signal, and a third communication signal in different frequency bands, and to output the first, second, and third communication signals from individual terminals. The individual terminals of the triplexer are connected to respective baluns. The baluns are configured such that the respective passbands of the baluns overlap the respective frequency bands of the communication signals and the respective passbands of the triplexer, and the attenuation of the baluns at the attenuation poles of the triplexer is ?3 dB or greater. This configuration provides high attenuation in the rebound bands of the attenuation poles.

Abstract: A duplexer includes a package substrate having layers stacked, a transmission filter and a reception filter that are provided on an upper surface of a first layer that is one of the layers of the package substrate, the transmission and reception filters being acoustic wave filters, a metal pattern provided on the upper surface of the first layer and formed to surround the transmission and reception filters, a transmission line provided on an upper surface of a second layer that is one of the layers of the package substrate and is positionally lower than the first layer, the transmission line electrically connecting the transmission filter and a transmission terminal together, and a reception line that is provided on the upper surface of the second layer and electrically connects the reception filter and a reception terminal. The thickness of the first layer is greater than that of the second layer.

Abstract: Provided are a branching filter capable of well branching two electrical signals having a wide frequency band, and a wireless communication module and wireless communication device using same. The branching filter is provided with an input terminal (11), a first output terminal (12a), a second output terminal (12b), a first line conductor (14a) which is electromagnetically coupled to a resonator (13a) of an input stage so as to interconnect the input terminal (11) and the first output terminal (12a), a capacitor (15a) which interconnects the first line conductor (14a) and ground, and a second line conductor (14b) which is electromagnetically coupled to a resonator (13b) of an output stage and is connected to the second output terminal (12b), wherein a low pass filter is configured from the first line conductor (14a) and the capacitor (15a), and a band pass filter is configured from the first line conductor (14a), the second line conductor (14b), and a plurality of resonators.

Abstract: In a common mode filter, at least one common mode filter portion is provided for removing a common mode noise, and has a first terminal pair configured to include first and second terminals connected to first and second external terminals, respectively, and has a second terminal pair configured to include third and fourth terminals connected to third and fourth external terminals, respectively. The filter includes an inductor circuit including at least two inductors that are connected in parallel to the first terminal pair of the common mode filter portion and are connected in series to each other, and an external terminal connected to the connection point of the at least two inductors. The external terminal is for being directly or indirectly grounded.

Abstract: A common mode filter with a multi spiral layer structure includes a first coil, a second coil, a third coil connected in series with the first coil, a fourth coil connected in series with the second coil, a first material layer and a second material layer. The second coil is disposed between the first and third coils, and the third coil is disposed between the second and fourth coils. At least one of the first and second material layers comprises magnetic material. The first, second, third, and fourth coils are disposed between the first and second material layers.

Abstract: The invention relates to a dielectric resonator rod in a transverse magnetic mode radio frequency filter comprising a first cylindrical end part (10) of a first diameter (D1) and a second cylindrical end part (20) of a second diameter (D2). The first diameter is different than the second diameter and the first cylindrical end part (10) is connected via a third intermediate part (30) to the second cylindrical end part (20). The third intermediate part (30) comprises a tapered outer circumferential surface connecting the first cylindrical end part (10) to the second cylindrical end part (20).

Abstract: An easily bendable high-frequency signal transmission line includes a dielectric body including a protection layer and dielectric sheets laminated on each other, a surface and an undersurface. A signal line is a linear conductor disposed in the dielectric body. A ground conductor is disposed in the dielectric body, faces the signal line via the dielectric sheet, and continuously extends along the signal line. A ground conductor is disposed in the dielectric body, faces the ground conductor via the signal line sandwiched therebetween, and includes a plurality of openings arranged along the signal line. The surface of the dielectric body on the side of the ground conductor with respect to the signal line is in contact with a battery pack.

Abstract: A transmission line includes two tapered lines having a tapered planar shape and arranged in parallel, opposite lines provided in opposition to the narrower width sides of the two tapered lines, and a bonding wire for connecting the narrower width sides of the two tapered lines and the opposite lines, wherein the width between two outer edges on the narrower width sides of the two tapered lines arranged in parallel is greater than the width between outer edges on the opposite side of the opposite lines in opposition to the narrower width sides of the two tapered lines.

Abstract: The present invention is directed to a protective electrical wiring device that includes at least one first stop member disposed proximate at least one first conductor. The at least one first stop member is configured to limit the movement of the at least one first conductor when the circuit interrupting assembly moves between the reset position and the tripped position such that a gap is established between the plurality of circuit interrupting contacts in the tripped state, the gap being substantially greater than or equal to a predetermined distance.

Abstract: A hinged armature arrangement, for a magnetic tripping device of an electrical switching device, includes a yoke, a hinged armature and a hinged armature spring for embodying a spring force on the hinged armature. The hinged armature is mounted at a first end in a hinged armature bearing. The hinged armature bearing includes a contact surface and a stop surface. The hinged armature spring is arranged on the hinged armature such that at least one first part of the spring force acts against a magnetic force, which is exerted on the hinged armature when a current path is energized. In a particular embodiment, the contact surface and the stop surface are arranged at an angle ? of less than 90° relative to one another.

Abstract: An electromagnetic relay including an electromagnet, a movable contact actuated by the electromagnet, and a fixed contact disposed opposite to the movable contact and capable of contacting and separating from the movable contact. The electromagnetic relay further includes a backstop for stopping movement of the movable contact in a direction separating from the fixed contact, and a backstop positioner for setting the backstop at a position for defining a predetermined contact gap between the fixed contact and the movable contact. In a state where movement of the movable contact is stopped by the backstop, different-sized contact gaps are defined between the fixed contact and the movable contact, depending on the position of the backstop set by the backstop positioner.

Abstract: An electromagnetic relay includes a first stationary contact; a second stationary contact that is aligned with the first stationary contact in a first direction; a first movable contact that is movable toward/away from the first stationary contact in a second direction perpendicular to the first direction; a second movable contact that is movable toward/away from the second stationary contact in the second direction; and a first permanent magnet and a second permanent magnet that face each other. A first contact part, formed by the first stationary contact and the first movable contact, and a second contract part, formed by the second stationary contact and the second movable contact, are interposed between the first permanent magnet and the second permanent magnet in the first direction. The first permanent magnet and the second permanent magnet extend in a third direction, which is perpendicular to the first direction and the second direction.

Abstract: A magnetic assembly for use in a housing of an electronic device can include a first and a second magnet and a magnetic shield. The magnetic shield can reduce magnetic flux density from the first and the second magnets that can appear on the outside of the housing. A magnetic hinge assembly can include magnets configured to correlate with the first and second magnets. The magnetic hinge can magnetically attach to the housing by cooperating with the first and second magnets with magnets that can be included in the magnetic hinge.

Abstract: To provide a reactor with which resin can fully be packed between a core and a coil with ease, and in which the core can easily be handled when the reactor is manufactured. The reactor includes: a coil 10 formed with paired coil elements 10A and 10B that are made of a spirally wound wire, the coil elements being coupled to each other in a paralleled state; internal core portions 22 that are fitted into the coil elements 10A and 10B to structure a part of an annular core 20; and exposed core portions 24 that are exposed outside the coil elements 10A and 10B to couple the internal core portions 22 to each other, to thereby form the rest of the annular core 20. The reactor includes an external resin portion that covers at least a part of an assembled product 1A made up of the coil 10 and the core 20. An interval between the inner end face 24f of the exposed core portion 24 and the end face of the coil 10 is 0.5 mm to 4.0 mm, whereby the resin can easily be packed between the coil 10 and the core 20.

Abstract: A coil-type electronic component having a coil inside or on the surface of a base material is characterized in that the base material of the coil-type electronic component is constituted by a group of soft magnetic alloy grains inter-bonded via oxide layers, multiple crystal grains are present in each soft magnetic alloy grain, and the oxide layers preferably have a two-layer structure whose outer layer is thicker than the inner layer.